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🐛 Fix issues with byte enable signal

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This commit is contained in:
Florian Zaruba 2017-10-31 20:31:11 +01:00
parent 1b432d123b
commit 1d260be1c0
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4 changed files with 15 additions and 14 deletions
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16
.gitlab-ci.yml
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@ -66,14 +66,14 @@ test_core_asm:
# - make run-asm-tests library=core_rand_lib uvm-flags=+rand_mem_if
# - vcover-10.6 report run-asm-rand-tests.ucdb
# test_failed_tests:
# stage: test
# before_script:
# - git submodule update --init --recursive
# - make build library=failed_tests_lib
# script:
# - make run-failed-tests library=failed_tests_lib
# - vcover-10.6 report run-failed-tests.ucdb
test_failed_tests:
stage: test
before_script:
- git submodule update --init --recursive
- make build library=failed_tests_lib
script:
- make run-failed-tests library=failed_tests_lib
- vcover-10.6 report run-failed-tests.ucdb
# test_lsu:
# stage: test

9
src/cache_ctrl.sv
View file

@ -204,8 +204,9 @@ module cache_ctrl #(
// we've got a match on MSHR
if (mashr_addr_matches_i) begin
state_d = WAIT_MSHR;
// save tag
mem_req_d.tag = address_tag_i;
// save tag if we didn't already save it e.g.: we are not in in the Tag saved state
if (state_q != WAIT_TAG_SAVED)
mem_req_d.tag = address_tag_i;
end
// -------------------------
// Check for cache-ability
@ -238,7 +239,7 @@ module cache_ctrl #(
// set the correct byte enable
for (int unsigned i = 0; i < 8; i++) begin
if (mem_req_q.be[i])
be_o.data[cl_offset +: 64] = '1;
be_o.data[cl_offset + i*8 +: 8] = '1;
end
data_o.data[cl_offset +: 64] = mem_req_q.wdata;
@ -253,7 +254,7 @@ module cache_ctrl #(
end
end
// we've got a match on MSHR ~> someone is serving a request
// we've got a match on MSHR ~> miss unit is serving a request
WAIT_MSHR: begin
mshr_addr_o = {mem_req_q.tag, mem_req_q.index};
// we can start a new request

2
src/miss_handler.sv
View file

@ -304,7 +304,7 @@ module miss_handler #(
mashr_addr_matches_o = 'b0;
for (int i = 0; i < NR_PORTS; i++) begin
if (mshr_q.valid && mshr_addr_i[i][55:$clog2(CACHE_LINE_WIDTH)] == mshr_q.addr[55:$clog2(CACHE_LINE_WIDTH)]) begin
if (mshr_q.valid && mshr_addr_i[i][55:$clog2(CACHE_LINE_WIDTH/8)] == mshr_q.addr[55:$clog2(CACHE_LINE_WIDTH/8)]) begin
mashr_addr_matches_o[i] = 1'b1;
end
end

2
tb

@ -1 +1 @@
Subproject commit 1b21c0676c49962d4b9fd7e2a3a4b1ecbfc1c3bc
Subproject commit bbf75b909548c228307acc0e657129e5f3faf154