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[CV-X-IF] Use Spike Yaml ISA to control the addition of CV-X-IF insns.

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This commit is contained in:
Zbigniew Chamski 2025-02-13 17:09:31 +01:00
parent 372f7c84ec
commit 1e0bf14894
6 changed files with 16 additions and 15 deletions
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8
config/gen_from_riscv_config/cv32a60x/spike/spike.yaml
View file

@ -8,12 +8,12 @@ spike_param_tree:
generic_core_config: false
max_steps: 200000
max_steps_enabled: false
isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif
priv: M
core_configs:
-
isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
extensions: cv32a60x,cvxif
isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif
extensions: cv32a60x
boot_addr: 2147483648
marchid_override_mask: 0xFFFFFFFF
marchid_override_value: 0x3
@ -39,7 +39,6 @@ spike_param_tree:
mip_override_mask: 0xfffff77f
mip_override_value: 0x00000000
mtval_write_mask: 0
mtvec_write_mask: 0xFFFFFFFE
tinfo_accessible: 0
mscontext_accessible: 0
mcontext_accessible: 0
@ -58,3 +57,4 @@ spike_param_tree:
unified_traps: true
mcycleh_implemented: false
mhpmevent31_implemented: false
cvxif_x_num_rs: 2

7
config/gen_from_riscv_config/cv32a65x/spike/spike.yaml
View file

@ -8,12 +8,12 @@ spike_param_tree:
generic_core_config: false
max_steps: 200000
max_steps_enabled: false
isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif
priv: M
core_configs:
-
isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
extensions: cv32a60x,cvxif
isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif
extensions: cv32a60x
boot_addr: 2147483648
marchid_override_mask: 0xFFFFFFFF
marchid_override_value: 0x3
@ -57,3 +57,4 @@ spike_param_tree:
unified_traps: true
mcycleh_implemented: false
mhpmevent31_implemented: false
cvxif_x_num_rs: 2

2
config/riscv-config/cv32a60x/generated/isa_gen.yaml
View file

@ -16,7 +16,7 @@
hart_ids: [0]
hart0:
ISA: RV32IMCZicsr_Zcb_Zba_Zbb_Zbc_Zbs
ISA: RV32IMCZicsr_Zcb_Zba_Zbb_Zbc_Zbs_Xcvxif
User_Spec_Version: '2.3'
supported_xlen:
- 32

2
config/riscv-config/cv32a60x/spec/isa_spec.yaml
View file

@ -16,7 +16,7 @@
hart_ids: [0]
hart0: &hart0
ISA: RV32IMCZicsr_Zcb_Zba_Zbb_Zbc_Zbs
ISA: RV32IMCZicsr_Zcb_Zba_Zbb_Zbc_Zbs_Xcvxif
User_Spec_Version: '2.3'
supported_xlen: [32]
physical_addr_sz: 32

2
config/riscv-config/cv32a65x/generated/isa_gen.yaml
View file

@ -16,7 +16,7 @@
hart_ids: [0]
hart0:
ISA: RV32IMCZicsr_Zcb_Zba_Zbb_Zbc_Zbs
ISA: RV32IMCZicsr_Zcb_Zba_Zbb_Zbc_Zbs_Xcvxif
User_Spec_Version: '2.3'
supported_xlen:
- 32

10
config/riscv-config/cv32a65x/spec/isa_spec.yaml
View file

@ -16,7 +16,7 @@
hart_ids: [0]
hart0: &hart0
ISA: RV32IMCZicsr_Zcb_Zba_Zbb_Zbc_Zbs
ISA: RV32IMCZicsr_Zcb_Zba_Zbb_Zbc_Zbs_Xcvxif
User_Spec_Version: '2.3'
supported_xlen: [32]
physical_addr_sz: 32
@ -52,7 +52,7 @@ hart0: &hart0
accessible: true
base:
implemented: true
type:
type:
warl:
dependency_fields: []
legal:
@ -63,7 +63,7 @@ hart0: &hart0
- Unchanged
mode:
implemented: true
type:
type:
warl:
dependency_fields: []
legal:
@ -108,9 +108,9 @@ hart0: &hart0
type:
warl:
dependency_fields: []
legal:
legal:
- mpp[1:0] in [0x3]
wr_illegal:
wr_illegal:
- Unchanged
fs:
implemented: false