mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-22 13:17:41 -04:00
Update to synthesis and simulation gate flow (#947)
This commit is contained in:
Guillaume Chauvon
GitHub
parent
82b300e295
commit
1e2ec41cc0
7 changed files with 129 additions and 29 deletions
32
core/Flist.cv32a60x_gate
Normal file
32
core/Flist.cv32a60x_gate
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@ -0,0 +1,32 @@
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# Copyright 2021 Thales DIS design services SAS
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#
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# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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# You may obtain a copy of the License at https://solderpad.org/licenses/
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#
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# Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
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#
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${CVA6_REPO_DIR}/core/include/cv32a60x_config_pkg.sv
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${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
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${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
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${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
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${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
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${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
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${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv
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${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
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${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
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${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
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${CVA6_REPO_DIR}/core/include/axi_intf.sv
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${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
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# NETLIST
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${LIB_VERILOG}
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${CVA6_REPO_DIR}/pd/synth/cva6_cv32a60x_synth_modified.v
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${CVA6_REPO_DIR}/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv
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${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
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${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
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${CVA6_REPO_DIR}/common/local/util/sram.sv
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@ -23,6 +23,9 @@ ${CVA6_REPO_DIR}/core/include/axi_intf.sv
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${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
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${LIB_VERILOG}
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${CVA6_REPO_DIR}/pd/synth/ariane_synth_modified.v
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${CVA6_REPO_DIR}/pd/synth/cva6_cv64a6_imafdc_sv39_synth_modified.v
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${CVA6_REPO_DIR}/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv
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${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
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${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
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${CVA6_REPO_DIR}/common/local/util/sram.sv
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@ -8,7 +8,7 @@
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# Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
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#
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DESIGN_NAME = ariane
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DESIGN_NAME = cva6
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PERIOD ?= 17
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FOUNDRY_PATH ?=
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TECH_NAME ?=
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@ -19,7 +19,7 @@ DC_SHELL_PATH ?= /opt/synopsys/syn/Q-2019.12/bin/
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NAND2_AREA ?= 1120
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TARGET ?= cv64a6_imafdc_sv39
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EXPORT_LIST=SNPSLMD_QUEUE=TRUE TECH_NAME=$(TECH_NAME) DESIGN_NAME=$(DESIGN_NAME) TERM=vt100 PERIOD=$(PERIOD) FOUNDRY_PATH=$(FOUNDRY_PATH) TARGET_LIBRARY_FILES=$(TARGET_LIBRARY_FILES) INPUT_DELAY=$(INPUT_DELAY) OUTPUT_DELAY=$(OUTPUT_DELAY)
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EXPORT_LIST=SNPSLMD_QUEUE=TRUE TECH_NAME=$(TECH_NAME) DESIGN_NAME=$(DESIGN_NAME) TARGET=$(TARGET) TERM=vt100 PERIOD=$(PERIOD) FOUNDRY_PATH=$(FOUNDRY_PATH) TARGET_LIBRARY_FILES=$(TARGET_LIBRARY_FILES) INPUT_DELAY=$(INPUT_DELAY) OUTPUT_DELAY=$(OUTPUT_DELAY)
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ifndef FOUNDRY_PATH
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$(error "Please provide FOUNDRY techno")
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@ -35,11 +35,14 @@ pre_cva6_synth:
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cva6_synth: pre_cva6_synth
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@echo $(PERIOD)
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@export $(EXPORT_LIST); $(DC_SHELL_PATH)/dc_shell -f ./cva6_synth.tcl -output synthesis_batch.log
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python scripts/gate_analysis.py '$(DESIGN_NAME)/reports/$(PERIOD)/$(DESIGN_NAME)_$(TECH_NAME)_synth_area.rpt' $(NAND2_AREA)
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sed 's/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0 gen/tc_sram_wrapper gen/' ariane_synth.v > ariane_synth_modified.v
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python scripts/gate_analysis.py '$(DESIGN_NAME)_$(TARGET)/reports/$(PERIOD)/$(DESIGN_NAME)_$(TECH_NAME)_synth_area.rpt' $(NAND2_AREA)
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mv $(DESIGN_NAME)_synth.v $(DESIGN_NAME)_$(TARGET)_synth.v
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mv $(DESIGN_NAME)_synth.v.sdf $(DESIGN_NAME)_$(TARGET)_synth.v.sdf
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sed -n -e '/module tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0/,/endmodule/!p' $(DESIGN_NAME)_$(TARGET)_synth.v > $(DESIGN_NAME)_$(TARGET)_synth_modified.v
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sed -i 's/cva6_ /cva6 /g' $(DESIGN_NAME)_$(TARGET)_synth_modified.v
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cva6_read:
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@export $(EXPORT_LIST); $(DC_SHELL_PATH)/dc_shell -f cva6_read.tcl -gui
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clean:
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@rm -rf work alib* *_LIB *log *svf netlist reports ${DESIGN_NAME}
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@rm -rf work alib* *_LIB *log *svf netlist reports ${DESIGN_NAME}_${TARGET}
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@ -34,10 +34,10 @@ link
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create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
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#set_dont_touch to keep sram as black boxes
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set_dont_touch i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[*].i_tag_sram
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set_dont_touch i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[*].i_data_sram
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set_dont_touch i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[*].data_sram
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set_dont_touch i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[*].tag_sram
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set_dont_touch i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[*].i_tag_sram
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set_dont_touch i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[*].i_data_sram
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set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].data_sram
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set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].tag_sram
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write -hierarchy -format ddc -output ${DCRM_ELABORATED_DESIGN_DDC_OUTPUT_FILE}
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@ -47,15 +47,15 @@ change_name -rule verilog -hier
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set_fix_multiple_port_nets -all -buffer_constants
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#constraint the timing to and from the sram black boxes
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set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
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set_output_delay $output_delay -max -clock main_clk i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
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set_output_delay $output_delay -max -clock main_clk i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
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set_output_delay $output_delay -max -clock main_clk i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
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set_output_delay $output_delay -max -clock main_clk i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
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set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
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set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
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set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
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set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
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# Check the current design for consistency
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check_design -summary > ${DCRM_CHECK_DESIGN_REPORT}
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@ -69,17 +69,18 @@ write -format verilog -hierarchy -output ${DESIGN_NAME}_synth.v
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write -format ddc -hierarchy -output ${DCRM_FINAL_DDC_OUTPUT_FILE}
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report_timing -nworst 10 > ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_timing -through i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}
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report_area -hier -nosplit > ${DCRM_FINAL_AREA_REPORT}
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write_parasitics -output ${DCRM_FINAL_SPEF_OUTPUT_FILE}
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write_sdc ${DCRM_FINAL_SDC_OUTPUT_FILE}
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write_sdf ${DESIGN_NAME}_synth.v.sdf
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exit
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@ -11,6 +11,7 @@
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# Variables common to all reference methodology scripts
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set PERIOD [getenv PERIOD];
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set DESIGN_NAME [getenv DESIGN_NAME] ;# The name of the top-level design
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set TARGET [getenv TARGET];
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set TECH [getenv TECH_NAME];
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set techno [getenv TECH_NAME];
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set FOUNDRY_PATH [getenv FOUNDRY_PATH];
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@ -17,9 +17,9 @@ puts "RM-Info: Running script [info script]\n"
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# Copyright (C) 2010-2015 Synopsys, Inc. All rights reserved.
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#################################################################################
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set INPUTS_DIR ${DESIGN_NAME}/inputs/
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set REPORTS_DIR ${DESIGN_NAME}/reports/${PERIOD}/
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set OUTPUTS_DIR ${DESIGN_NAME}/outputs/${PERIOD}/
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set INPUTS_DIR ${DESIGN_NAME}_${TARGET}/inputs/
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set REPORTS_DIR ${DESIGN_NAME}_${TARGET}/reports/${PERIOD}/
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set OUTPUTS_DIR ${DESIGN_NAME}_${TARGET}/outputs/${PERIOD}/
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file mkdir ${INPUTS_DIR}
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file mkdir ${REPORTS_DIR}
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file mkdir ${OUTPUTS_DIR}
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@ -0,0 +1,60 @@
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// Copyright 2022 Thales DIS design services SAS
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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// You may obtain a copy of the License at https://solderpad.org/licenses/
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//
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// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
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module tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0 #(
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parameter int unsigned NumWords = 32'd256, // Number of Words in data array
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parameter int unsigned DataWidth = 32'd64, // Data signal width
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parameter int unsigned ByteWidth = 32'd8, // Width of a data byte
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parameter int unsigned NumPorts = 32'd1, // Number of read and write ports
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parameter int unsigned Latency = 32'd1, // Latency when the read data is available
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parameter SimInit = "none", // Simulation initialization
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parameter bit PrintSimCfg = 1'b0, // Print configuration
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// DEPENDENT PARAMETERS, DO NOT OVERWRITE!
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parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
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parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div
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parameter type addr_t = logic [AddrWidth-1:0],
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parameter type data_t = logic [DataWidth-1:0],
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parameter type be_t = logic [BeWidth-1:0]
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) (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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// input ports
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input logic [NumPorts-1:0] req_i, // request
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input logic [NumPorts-1:0] we_i, // write enable
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input addr_t [NumPorts-1:0] addr_i, // request address
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input data_t [NumPorts-1:0] wdata_i, // write data
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input be_t [NumPorts-1:0] be_i, // write byte enable
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// output ports
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output data_t [NumPorts-1:0] rdata_o // read data
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);
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// synthesis translate_off
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tc_sram #(
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.NumWords(NumWords),
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.DataWidth(DataWidth),
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.ByteWidth(ByteWidth),
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.NumPorts(NumPorts),
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.Latency(Latency),
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.SimInit(SimInit),
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.PrintSimCfg(PrintSimCfg)
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) i_tc_sram (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.req_i ( req_i ),
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.we_i ( we_i ),
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.be_i ( be_i ),
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.wdata_i ( wdata_i ),
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.addr_i ( addr_i ),
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.rdata_o ( rdata_o )
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);
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// synthesis translate_on
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endmodule
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