ariane: Replace branchpredict_t with bp_resolve_t

The new name better captures the meaning of the signal.

docs/_docs/arch/pcgen_stage.md

@@ -32,7 +32,7 @@ precedence):
     to correct prediction). Branch information which is passed down the
     pipeline is encapsulated in a structure called `branchpredict_sbe_t`.
     In contrast to branch prediction information which is passed up the
-    pipeline which is just called `branchpredict_t`. This is used for
+    pipeline which is just called `bp_resolve_t`. This is used for
     corrective actions (see next bullet point). This naming convention
     should make it easy to detect the flow of branch information in the source code.
 

include/ariane_pkg.sv

@@ -309,7 +309,7 @@ package ariane_pkg;
         logic        valid;           // prediction with all its values is valid
         logic        clear;           // invalidate this entry
         cf_t         cf_type;         // Type of control flow change
-    } branchpredict_t;
+    } bp_resolve_t;
 
     // branchpredict scoreboard entry
     // this is the struct which we will inject into the pipeline to guide the various

src/ariane.sv

@@ -46,7 +46,7 @@ module ariane #(
   // ------------------------------------------
   riscv::priv_lvl_t           priv_lvl;
   exception_t                 ex_commit; // exception from commit stage
-  branchpredict_t             resolved_branch;
+  bp_resolve_t                resolved_branch;
   logic [63:0]                pc_commit;
   logic                       eret;
   logic [NR_COMMIT_PORTS-1:0] commit_ack;

src/branch_unit.sv

@@ -24,7 +24,7 @@ module branch_unit (
     output logic [63:0]               branch_result_o,
 
     input  branchpredict_sbe_t        branch_predict_i,       // this is the address we predicted
-    output branchpredict_t            resolved_branch_o,      // this is the actual address we are targeting
+    output bp_resolve_t               resolved_branch_o,      // this is the actual address we are targeting
     output logic                      resolve_branch_o,       // to ID to clear that we resolved the branch and we can
                                                               // accept new entries to the scoreboard
     output exception_t                branch_exception_o      // branch exception out

src/controller.sv

@@ -33,7 +33,7 @@ module controller (
     input  logic            eret_i,                 // Return from exception
     input  logic            ex_valid_i,             // We got an exception, flush the pipeline
     input  logic            set_debug_pc_i,         // set the debug pc from CSR
-    input  branchpredict_t  resolved_branch_i,      // We got a resolved branch, check if we need to flush the front-end
+    input  bp_resolve_t     resolved_branch_i,      // We got a resolved branch, check if we need to flush the front-end
     input  logic            flush_csr_i,            // We got an instruction which altered the CSR, flush the pipeline
     input  logic            fence_i_i,              // fence.i in
     input  logic            fence_i,                // fence in

src/ex_stage.sv

@@ -38,7 +38,7 @@ module ex_stage #(
     // Branch Unit
     input  logic                                   branch_valid_i,        // we are using the branch unit
     input  branchpredict_sbe_t                     branch_predict_i,
-    output branchpredict_t                         resolved_branch_o,     // the branch engine uses the write back from the ALU
+    output bp_resolve_t                            resolved_branch_o,     // the branch engine uses the write back from the ALU
     output logic                                   resolve_branch_o,      // to ID signaling that we resolved the branch
     // CSR
     input  logic                                   csr_valid_i,

src/frontend/frontend.sv

@@ -27,7 +27,7 @@ module frontend #(
     input  logic [63:0]        boot_addr_i,
     // Set a new PC
     // mispredict
-    input  branchpredict_t     resolved_branch_i,  // from controller signaling a branch_predict -> update BTB
+    input  bp_resolve_t        resolved_branch_i,  // from controller signaling a branch_predict -> update BTB
     // from commit, when flushing the whole pipeline
     input  logic               set_pc_commit_i,    // Take the PC from commit stage
     input  logic [63:0]        pc_commit_i,        // PC of instruction in commit stage

src/issue_stage.sv

@@ -57,7 +57,7 @@ module issue_stage #(
 
     // write back port
     input logic [NR_WB_PORTS-1:0][TRANS_ID_BITS-1:0] trans_id_i,
-    input branchpredict_t                            resolved_branch_i,
+    input bp_resolve_t                               resolved_branch_i,
     input logic [NR_WB_PORTS-1:0][63:0]              wbdata_i,
     input exception_t [NR_WB_PORTS-1:0]              ex_ex_i, // exception from execute stage
     input logic [NR_WB_PORTS-1:0]                    wt_valid_i,

src/perf_counters.sv

@@ -40,10 +40,9 @@ module perf_counters (
   // from PC Gen
   input  exception_t                              ex_i,
   input  logic                                    eret_i,
-  input  branchpredict_t                          resolved_branch_i
+  input  bp_resolve_t                             resolved_branch_i
 );
-
-  localparam logic [6:0] RegOffset = riscv::CSR_ML1_ICACHE_MISS>>5;
+  localparam logic [6:0] RegOffset = riscv::CSR_ML1_ICACHE_MISS >> 5;
 
   logic [riscv::CSR_MIF_EMPTY : riscv::CSR_ML1_ICACHE_MISS][63:0] perf_counter_d, perf_counter_q;
 

src/scoreboard.sv

@@ -58,7 +58,7 @@ module scoreboard #(
     input  logic                                      issue_ack_i,
 
     // write-back port
-    input branchpredict_t                             resolved_branch_i,
+    input bp_resolve_t                                resolved_branch_i,
     input logic [NR_WB_PORTS-1:0][TRANS_ID_BITS-1:0]  trans_id_i,  // transaction ID at which to write the result back
     input logic [NR_WB_PORTS-1:0][63:0]               wbdata_i,    // write data in
     input exception_t [NR_WB_PORTS-1:0]               ex_i,        // exception from a functional unit (e.g.: ld/st exception)

src/util/instruction_trace_item.svh

@@ -29,13 +29,13 @@ class instruction_trace_item;
     logic [63:0]       result;
     logic [63:0]       paddr;
     string             priv_lvl;
-    branchpredict_t    bp;
+    bp_resolve_t       bp;
 
     logic [4:0] rs1, rs2, rs3, rd;
 
     // constructor creating a new instruction trace item, e.g.: a single instruction with all relevant information
     function new (time simtime, longint unsigned cycle, scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32],
-                logic [63:0] fp_reg_file [32], logic [63:0] result, logic [63:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, branchpredict_t bp);
+                logic [63:0] fp_reg_file [32], logic [63:0] result, logic [63:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp);
         this.simtime  = simtime;
         this.cycle    = cycle;
         this.pc       = sbe.pc;

src/util/instruction_tracer.sv

@@ -34,7 +34,7 @@ module instruction_tracer (
   scoreboard_entry_t issue_sbe_queue [$];
   scoreboard_entry_t issue_sbe;
   // store resolved branches, get (mis-)predictions
-  branchpredict_t bp [$];
+  bp_resolve_t bp [$];
   // shadow copy of the register files
   logic [63:0] gp_reg_file [32];
   logic [63:0] fp_reg_file [32];
@@ -65,7 +65,7 @@ module instruction_tracer (
     fp_reg_file  = '{default:0};
 
     forever begin
-      automatic branchpredict_t bp_instruction = '0;
+      automatic bp_resolve_t bp_instruction = '0;
       // new cycle, we are only interested if reset is de-asserted
       @(tracer_if.pck iff tracer_if.pck.rstn);
       // increment clock tick
@@ -186,7 +186,7 @@ module instruction_tracer (
     bp              = {};
   endfunction
 
-  function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [63:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, branchpredict_t bp);
+  function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [63:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp);
     automatic instruction_trace_item iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp);
     // print instruction to console
     automatic string print_instr = iti.printInstr();

src/util/instruction_tracer_if.sv

@@ -46,7 +46,7 @@ interface instruction_tracer_if (
     logic              ld_kill;
     logic [63:0]       ld_paddr;
     // misprediction
-    branchpredict_t    resolve_branch;
+    bp_resolve_t       resolve_branch;
     // exceptions
     exception_t        exception;
     // current privilege level