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https://github.com/openhwgroup/cva6.git
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Code_coverage: condition RTL with the debug parameter (#1582)
This commit is contained in:
parent
a34aca924e
commit
1faaec09bc
22 changed files with 114 additions and 71 deletions
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@ -1,2 +1,2 @@
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cv32a6_embedded:
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gates: 123953
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gates: 121071
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@ -341,7 +341,9 @@ module wt_dcache_wbuffer
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for (genvar k = 0; k < DCACHE_WBUF_DEPTH; k++) begin : gen_flags
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// only for debug, will be pruned
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assign debug_paddr[k] = {{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[k].wtag << riscv::XLEN_ALIGN_BYTES};
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if(CVA6Cfg.DebugEn) begin
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assign debug_paddr[k] = {{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[k].wtag << riscv::XLEN_ALIGN_BYTES};
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end
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// dirty bytes that are ready for transmission.
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// note that we cannot retransmit a word that is already in-flight
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@ -154,7 +154,7 @@ module controller
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// 1. Exception
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// 2. Return from exception
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// ---------------------------------
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if (ex_valid_i || eret_i || set_debug_pc_i) begin
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if (ex_valid_i || eret_i || (CVA6Cfg.DebugEn && set_debug_pc_i)) begin
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// don't flush pcgen as we want to take the exception: Flush PCGen is not a flush signal
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// for the PC Gen stage but instead tells it to take the PC we gave it
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set_pc_commit_o = 1'b0;
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@ -224,10 +224,18 @@ module csr_regfile
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end
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end
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// debug registers
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riscv::CSR_DCSR: csr_rdata = {{riscv::XLEN - 32{1'b0}}, dcsr_q};
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riscv::CSR_DPC: csr_rdata = dpc_q;
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riscv::CSR_DSCRATCH0: csr_rdata = dscratch0_q;
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riscv::CSR_DSCRATCH1: csr_rdata = dscratch1_q;
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riscv::CSR_DCSR:
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if (CVA6Cfg.DebugEn) csr_rdata = {{riscv::XLEN - 32{1'b0}}, dcsr_q};
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else read_access_exception = 1'b1;
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riscv::CSR_DPC:
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if (CVA6Cfg.DebugEn) csr_rdata = dpc_q;
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else read_access_exception = 1'b1;
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riscv::CSR_DSCRATCH0:
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if (CVA6Cfg.DebugEn) csr_rdata = dscratch0_q;
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else read_access_exception = 1'b1;
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riscv::CSR_DSCRATCH1:
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if (CVA6Cfg.DebugEn) csr_rdata = dscratch1_q;
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else read_access_exception = 1'b1;
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// trigger module registers
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riscv::CSR_TSELECT: read_access_exception = 1'b1; // not implemented
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riscv::CSR_TDATA1: read_access_exception = 1'b1; // not implemented
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@ -662,17 +670,27 @@ module csr_regfile
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end
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// debug CSR
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riscv::CSR_DCSR: begin
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dcsr_d = csr_wdata[31:0];
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// debug is implemented
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dcsr_d.xdebugver = 4'h4;
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// currently not supported
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dcsr_d.nmip = 1'b0;
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dcsr_d.stopcount = 1'b0;
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dcsr_d.stoptime = 1'b0;
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if (CVA6Cfg.DebugEn) begin
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dcsr_d = csr_wdata[31:0];
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// debug is implemented
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dcsr_d.xdebugver = 4'h4;
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// currently not supported
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dcsr_d.nmip = 1'b0;
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dcsr_d.stopcount = 1'b0;
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dcsr_d.stoptime = 1'b0;
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end else begin
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update_access_exception = 1'b1;
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end
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end
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riscv::CSR_DPC: dpc_d = csr_wdata;
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riscv::CSR_DSCRATCH0: dscratch0_d = csr_wdata;
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riscv::CSR_DSCRATCH1: dscratch1_d = csr_wdata;
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riscv::CSR_DPC:
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if (CVA6Cfg.DebugEn) dpc_d = csr_wdata;
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else update_access_exception = 1'b1;
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riscv::CSR_DSCRATCH0:
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if (CVA6Cfg.DebugEn) dscratch0_d = csr_wdata;
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else update_access_exception = 1'b1;
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riscv::CSR_DSCRATCH1:
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if (CVA6Cfg.DebugEn) dscratch1_d = csr_wdata;
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else update_access_exception = 1'b1;
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// trigger module CSRs
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riscv::CSR_TSELECT: update_access_exception = 1'b1 ; // not implemented
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riscv::CSR_TDATA1: update_access_exception = 1'b1; // not implemented
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@ -1124,7 +1142,7 @@ module csr_regfile
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// trigger module fired
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// caused by a breakpoint
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if (ex_i.valid && ex_i.cause == riscv::BREAKPOINT) begin
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if (CVA6Cfg.DebugEn && ex_i.valid && ex_i.cause == riscv::BREAKPOINT) begin
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dcsr_d.prv = priv_lvl_o;
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// check that we actually want to enter debug depending on the privilege level we are currently in
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unique case (priv_lvl_o)
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@ -1152,7 +1170,7 @@ module csr_regfile
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end
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// we've got a debug request
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if (ex_i.valid && ex_i.cause == riscv::DEBUG_REQUEST) begin
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if (CVA6Cfg.DebugEn && ex_i.valid && ex_i.cause == riscv::DEBUG_REQUEST) begin
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dcsr_d.prv = priv_lvl_o;
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// save the PC
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dpc_d = {{riscv::XLEN - riscv::VLEN{pc_i[riscv::VLEN-1]}}, pc_i};
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@ -1165,7 +1183,7 @@ module csr_regfile
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end
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// single step enable and we just retired an instruction
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if (dcsr_q.step && commit_ack_i[0]) begin
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if (CVA6Cfg.DebugEn && dcsr_q.step && commit_ack_i[0]) begin
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dcsr_d.prv = priv_lvl_o;
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// valid CTRL flow change
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if (commit_instr_i[0].fu == CTRL_FLOW) begin
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@ -1193,7 +1211,7 @@ module csr_regfile
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end
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end
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// go in halt-state again when we encounter an exception
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if (debug_mode_q && ex_i.valid && ex_i.cause == riscv::BREAKPOINT) begin
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if (CVA6Cfg.DebugEn && debug_mode_q && ex_i.valid && ex_i.cause == riscv::BREAKPOINT) begin
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set_debug_pc_o = 1'b1;
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end
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@ -1242,7 +1260,7 @@ module csr_regfile
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end
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// return from debug mode
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if (dret) begin
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if (CVA6Cfg.DebugEn && dret) begin
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// return from exception, IF doesn't care from where we are returning
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eret_o = 1'b1;
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// restore the previous privilege level
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@ -1283,10 +1301,12 @@ module csr_regfile
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mret = 1'b1; // signal a return from machine mode
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end
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DRET: begin
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// the return should not have any write or read side-effects
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csr_we = 1'b0;
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csr_read = 1'b0;
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dret = 1'b1; // signal a return from debug mode
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if (CVA6Cfg.DebugEn) begin
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// the return should not have any write or read side-effects
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csr_we = 1'b0;
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csr_read = 1'b0;
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dret = 1'b1; // signal a return from debug mode
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end
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end
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default: begin
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csr_we = 1'b0;
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@ -1369,7 +1389,7 @@ module csr_regfile
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wfi_d = wfi_q;
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// if there is any (enabled) interrupt pending un-stall the core
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// also un-stall if we want to enter debug mode
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if (|(mip_q & mie_q) || debug_req_i || irq_i[1]) begin
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if (|(mip_q & mie_q) || (CVA6Cfg.DebugEn && debug_req_i) || irq_i[1]) begin
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wfi_d = 1'b0;
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// or alternatively if there is no exception pending and we are not in debug mode wait here
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// for the interrupt
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@ -1387,7 +1407,7 @@ module csr_regfile
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end
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// if we are in debug mode jump to a specific address
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if (debug_mode_q) begin
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if (CVA6Cfg.DebugEn && debug_mode_q) begin
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trap_vector_base_o = CVA6Cfg.DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.ExceptionAddress[riscv::VLEN-1:0];
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end
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@ -1408,7 +1428,7 @@ module csr_regfile
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epc_o = sepc_q[riscv::VLEN-1:0];
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end
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// we are returning from debug mode, to take the dpc register
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if (dret) begin
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if (CVA6Cfg.DebugEn && dret) begin
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epc_o = dpc_q[riscv::VLEN-1:0];
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end
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end
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@ -1437,7 +1457,7 @@ module csr_regfile
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end
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// in debug mode we execute with privilege level M
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assign priv_lvl_o = (debug_mode_q) ? riscv::PRIV_LVL_M : priv_lvl_q;
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assign priv_lvl_o = (CVA6Cfg.DebugEn && debug_mode_q) ? riscv::PRIV_LVL_M : priv_lvl_q;
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// FPU outputs
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assign fflags_o = fcsr_q.fflags;
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assign frm_o = fcsr_q.frm;
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@ -1461,29 +1481,31 @@ module csr_regfile
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`else
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assign icache_en_o = icache_q[0] & (~debug_mode_q);
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`endif
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assign dcache_en_o = dcache_q[0];
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assign acc_cons_en_o = CVA6Cfg.EnableAccelerator ? acc_cons_q[0] : 1'b0;
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assign dcache_en_o = dcache_q[0];
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assign acc_cons_en_o = CVA6Cfg.EnableAccelerator ? acc_cons_q[0] : 1'b0;
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// determine if mprv needs to be considered if in debug mode
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assign mprv = (debug_mode_q && !dcsr_q.mprven) ? 1'b0 : mstatus_q.mprv;
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assign debug_mode_o = debug_mode_q;
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assign single_step_o = dcsr_q.step;
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assign mprv = (CVA6Cfg.DebugEn && debug_mode_q && !dcsr_q.mprven) ? 1'b0 : mstatus_q.mprv;
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assign debug_mode_o = debug_mode_q;
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assign single_step_o = dcsr_q.step;
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assign mcountinhibit_o = {{29 - MHPMCounterNum{1'b0}}, mcountinhibit_q};
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// sequential process
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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priv_lvl_q <= riscv::PRIV_LVL_M;
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priv_lvl_q <= riscv::PRIV_LVL_M;
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// floating-point registers
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fcsr_q <= '0;
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fcsr_q <= '0;
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// debug signals
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debug_mode_q <= 1'b0;
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dcsr_q <= '0;
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dcsr_q.prv <= riscv::PRIV_LVL_M;
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dcsr_q.xdebugver <= 4'h4;
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dpc_q <= '0;
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dscratch0_q <= {riscv::XLEN{1'b0}};
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dscratch1_q <= {riscv::XLEN{1'b0}};
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debug_mode_q <= 1'b0;
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if (CVA6Cfg.DebugEn) begin
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dcsr_q <= '0;
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dcsr_q.prv <= riscv::PRIV_LVL_M;
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dcsr_q.xdebugver <= 4'h4;
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dpc_q <= '0;
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dscratch0_q <= {riscv::XLEN{1'b0}};
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dscratch1_q <= {riscv::XLEN{1'b0}};
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end
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// machine mode registers
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mstatus_q <= 64'b0;
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// set to boot address + direct mode + 4 byte offset which is the initial trap
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pmpcfg_q <= '0;
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pmpaddr_q <= '0;
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end else begin
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priv_lvl_q <= priv_lvl_d;
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priv_lvl_q <= priv_lvl_d;
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// floating-point registers
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fcsr_q <= fcsr_d;
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fcsr_q <= fcsr_d;
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// debug signals
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debug_mode_q <= debug_mode_d;
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dcsr_q <= dcsr_d;
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dpc_q <= dpc_d;
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dscratch0_q <= dscratch0_d;
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dscratch1_q <= dscratch1_d;
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if (CVA6Cfg.DebugEn) begin
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debug_mode_q <= debug_mode_d;
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dcsr_q <= dcsr_d;
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dpc_q <= dpc_d;
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dscratch0_q <= dscratch0_d;
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dscratch1_q <= dscratch1_d;
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end
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// machine mode registers
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mstatus_q <= mstatus_d;
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mtvec_rst_load_q <= 1'b0;
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@ -213,7 +213,8 @@ module cva6
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CVA6Cfg.NrCachedRegionRules,
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CVA6Cfg.CachedRegionAddrBase,
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CVA6Cfg.CachedRegionLength,
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CVA6Cfg.MaxOutstandingStores
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CVA6Cfg.MaxOutstandingStores,
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CVA6Cfg.DebugEn
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};
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@ -1304,7 +1305,7 @@ module cva6
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cycles <= 0;
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end else begin
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byte mode = "";
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if (debug_mode) mode = "D";
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if (CVA6Cfg.DebugEn && debug_mode) mode = "D";
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else begin
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case (priv_lvl)
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riscv::PRIV_LVL_M: mode = "M";
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@ -1322,7 +1323,7 @@ module cva6
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$fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h) PC=%h\n",
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commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc);
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end else begin
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if (debug_mode) begin
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if (CVA6Cfg.DebugEn && debug_mode) begin
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$fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc,
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mode, commit_instr_id_commit[i].ex.tval[31:0],
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commit_instr_id_commit[i].ex.tval[31:0]);
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@ -1369,7 +1370,7 @@ module cva6
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// when trap, the instruction is not executed
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rvfi_o[i].trap = mem_exception;
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rvfi_o[i].cause = ex_commit.cause;
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rvfi_o[i].mode = debug_mode ? 2'b10 : priv_lvl;
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rvfi_o[i].mode = (CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl;
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rvfi_o[i].ixl = riscv::XLEN == 64 ? 2 : 1;
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rvfi_o[i].rs1_addr = commit_instr_id_commit[i].rs1[4:0];
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rvfi_o[i].rs2_addr = commit_instr_id_commit[i].rs2[4:0];
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@ -1405,7 +1405,7 @@ module decoder
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end
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// a debug request has precendece over everything else
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if (debug_req_i && !debug_mode_i) begin
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if (CVA6Cfg.DebugEn && debug_req_i && !debug_mode_i) begin
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instruction_o.ex.valid = 1'b1;
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instruction_o.ex.cause = riscv::DEBUG_REQUEST;
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end
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@ -361,7 +361,7 @@ module frontend
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end
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// 7. Debug
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// enter debug on a hard-coded base-address
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if (set_debug_pc_i)
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if (CVA6Cfg.DebugEn && set_debug_pc_i)
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npc_d = CVA6Cfg.DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.HaltAddress[riscv::VLEN-1:0];
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icache_dreq_o.vaddr = fetch_address;
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end
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@ -111,6 +111,7 @@ package config_pkg;
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logic [NrMaxRules-1:0][63:0] CachedRegionLength;
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/// Maximum number of outstanding stores.
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int unsigned MaxOutstandingStores;
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bit DebugEn;
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} cva6_cfg_t;
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@ -137,7 +137,8 @@ package cva6_config_pkg;
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),
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CachedRegionAddrBase: 1024'({64'h8000_0000}),
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CachedRegionLength: 1024'({64'h40000000}),
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MaxOutstandingStores: unsigned'(7)
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MaxOutstandingStores: unsigned'(7),
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DebugEn: bit'(1)
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};
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endpackage
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@ -136,7 +136,8 @@ package cva6_config_pkg;
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),
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CachedRegionAddrBase: 1024'({64'h8000_0000}),
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CachedRegionLength: 1024'({64'h40000000}),
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MaxOutstandingStores: unsigned'(7)
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MaxOutstandingStores: unsigned'(7),
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DebugEn: bit'(0)
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};
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endpackage
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@ -137,7 +137,8 @@ package cva6_config_pkg;
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),
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CachedRegionAddrBase: 1024'({64'h8000_0000}),
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CachedRegionLength: 1024'({64'h40000000}),
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MaxOutstandingStores: unsigned'(7)
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MaxOutstandingStores: unsigned'(7),
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DebugEn: bit'(1)
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};
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endpackage
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@ -137,6 +137,7 @@ package cva6_config_pkg;
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),
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CachedRegionAddrBase: 1024'({64'h8000_0000}),
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CachedRegionLength: 1024'({64'h40000000}),
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MaxOutstandingStores: unsigned'(7)
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MaxOutstandingStores: unsigned'(7),
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DebugEn: bit'(1)
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};
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endpackage
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@ -137,7 +137,8 @@ package cva6_config_pkg;
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),
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CachedRegionAddrBase: 1024'({64'h8000_0000}),
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CachedRegionLength: 1024'({64'h40000000}),
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MaxOutstandingStores: unsigned'(7)
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MaxOutstandingStores: unsigned'(7),
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DebugEn: bit'(1)
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};
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endpackage
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@ -137,7 +137,8 @@ package cva6_config_pkg;
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),
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CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
MaxOutstandingStores: unsigned'(7)
|
||||
MaxOutstandingStores: unsigned'(7),
|
||||
DebugEn: bit'(1)
|
||||
};
|
||||
|
||||
endpackage
|
||||
|
|
|
@ -136,7 +136,8 @@ package cva6_config_pkg;
|
|||
),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
MaxOutstandingStores: unsigned'(7)
|
||||
MaxOutstandingStores: unsigned'(7),
|
||||
DebugEn: bit'(1)
|
||||
};
|
||||
|
||||
endpackage
|
||||
|
|
|
@ -137,7 +137,8 @@ package cva6_config_pkg;
|
|||
),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
MaxOutstandingStores: unsigned'(7)
|
||||
MaxOutstandingStores: unsigned'(7),
|
||||
DebugEn: bit'(1)
|
||||
};
|
||||
|
||||
endpackage
|
||||
|
|
|
@ -143,7 +143,8 @@ package cva6_config_pkg;
|
|||
1
|
||||
),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000})
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
DebugEn: bit'(1)
|
||||
};
|
||||
|
||||
endpackage
|
||||
|
|
|
@ -137,7 +137,8 @@ package cva6_config_pkg;
|
|||
),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
MaxOutstandingStores: unsigned'(7)
|
||||
MaxOutstandingStores: unsigned'(7),
|
||||
DebugEn: bit'(1)
|
||||
};
|
||||
|
||||
endpackage
|
||||
|
|
|
@ -137,7 +137,8 @@ package cva6_config_pkg;
|
|||
),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
MaxOutstandingStores: unsigned'(7)
|
||||
MaxOutstandingStores: unsigned'(7),
|
||||
DebugEn: bit'(1)
|
||||
};
|
||||
|
||||
endpackage
|
||||
|
|
|
@ -136,6 +136,7 @@ package cva6_config_pkg;
|
|||
),
|
||||
CachedRegionAddrBase: 1024'({64'h8000_0000}),
|
||||
CachedRegionLength: 1024'({64'h40000000}),
|
||||
MaxOutstandingStores: unsigned'(7)
|
||||
MaxOutstandingStores: unsigned'(7),
|
||||
DebugEn: bit'(1)
|
||||
};
|
||||
endpackage
|
||||
|
|
|
@ -176,7 +176,9 @@ module scoreboard #(
|
|||
mem_n[trans_id_i[i]].sbe.valid = 1'b1;
|
||||
mem_n[trans_id_i[i]].sbe.result = wbdata_i[i];
|
||||
// save the target address of a branch (needed for debug in commit stage)
|
||||
mem_n[trans_id_i[i]].sbe.bp.predict_address = resolved_branch_i.target_address;
|
||||
if(CVA6Cfg.DebugEn) begin
|
||||
mem_n[trans_id_i[i]].sbe.bp.predict_address = resolved_branch_i.target_address;
|
||||
end
|
||||
if (mem_n[trans_id_i[i]].sbe.fu == ariane_pkg::CVXIF && ~x_we_i) begin
|
||||
mem_n[trans_id_i[i]].sbe.rd = 5'b0;
|
||||
end
|
||||
|
|
|
@ -208,7 +208,8 @@ localparam config_pkg::cva6_cfg_t CVA6Cfg = '{
|
|||
NrCachedRegionRules: unsigned'(1),
|
||||
CachedRegionAddrBase: 1024'({ariane_soc::DRAMBase}),
|
||||
CachedRegionLength: 1024'({ariane_soc::DRAMLength}),
|
||||
MaxOutstandingStores: unsigned'(7)
|
||||
MaxOutstandingStores: unsigned'(7),
|
||||
DebugEn: bit'(1)
|
||||
};
|
||||
|
||||
localparam type rvfi_instr_t = logic;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue