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Add detailed simulation flow installation info & helper scripts (#740)
* Add information for verilator flow setup to README.md * Prevent re-download if RISCV64_UNKNOWN_ELF_GCC already exists. Use variable for archive version. * Add RISC-V proxy kernel and bootloader install script * Integrate tool installation into getting-started section * Remove $ sign in command snippets to allow command copy & paste * Add information for verilator flow setup to README.md * Prevent re-download if RISCV64_UNKNOWN_ELF_GCC already exists. Use variable for archive version. * Add RISC-V proxy kernel and bootloader install script * Integrate tool installation into getting-started section * Remove $ sign in command snippets to allow command copy & paste * Replace manual install command for riscv-pk by script * Fix README.md merge conflict mismatches * Fix script name Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch> Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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Andreas Kuster
GitHub
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3 changed files with 82 additions and 59 deletions
118
README.md
118
README.md
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@ -60,7 +60,10 @@ Table of Contents
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* [CVA6 RISC-V CPU](#cva6-risc-v-cpu)
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* [Table of Contents](#table-of-contents)
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* [Getting Started](#getting-started)
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* [Running User-Space Applications](#running-user-space-applications)
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* [Checkout Repo](#checkout-repo)
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* [Install Verilator Simulation Flow](#install-verilator-simulation-flow)
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* [Build Model and Run Simulations](#build-model-and-run-simulations)
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* [Running User-Space Applications](#running-user-space-applications)
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* [FPGA Emulation](#fpga-emulation)
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* [Programming the Memory Configuration File](#programming-the-memory-configuration-file)
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* [Preparing the SD Card](#preparing-the-sd-card)
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@ -77,52 +80,50 @@ Table of Contents
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Created by [gh-md-toc](https://github.com/ekalinin/github-markdown-toc)
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## Tool Requirements
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* `verilator >= 4.002`
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> There is currently a known issue with version 4.106 and 4.108. 4.106 does not
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> compile and 4.108 hangs after a couple of cycles simulation time.
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## Getting Started
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Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools).
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Make sure that your `RISCV` environment variable points to your RISC-V installation (see the RISC-V tools and related projects for further information).
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<br><br>
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Checkout the repository and initialize all submodules:
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### Checkout Repo
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Checkout the repository and initialize all submodules
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```
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$ git clone -b cva6_reorg https://github.com/openhwgroup/cva6.git cva6_reorg
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$ cd cva6_reorg
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$ git submodule update --init --recursive
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git clone https://github.com/openhwgroup/cva6.git
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git submodule update --init --recursive
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```
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Build the Verilator model of the COREV-APU by using the Makefile:
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### Install Verilator Simulation Flow
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1. Setup install directory `RISCV` environment variable i.e. `export RISCV=/YOUR/TOOLCHAIN/INSTALLATION/DIRECTORY`
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2. Run `./ci/setup.sh` to install all required tools (i.e. verilator, device-tree-compiler, riscv64-unknown-elf-*, ..)
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You can install verilator from source using `./ci/install-verilator.sh` or by manually installing `verilator >= 4.002`
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Note: There is currently a known issue with version 4.106 and 4.108. 4.106 does not compile and 4.108 hangs after a
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couple of cycles simulation time.)
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### Build Model and Run Simulations
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Build the Verilator model of CVA6 by using the Makefile:
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```
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$ make verilate
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make verilate
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```
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To build the verilator model with support for vcd files run
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```
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$ make verilate DEBUG=1
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make verilate DEBUG=1
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```
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This will create a C++ model of the core including a SystemVerilog wrapper and link it against a C++ testbench (in the `tb` subfolder).
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The binary can be found in the `work-ver` and accepts a RISC-V ELF binary as an argument, e.g.:
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This will create a C++ model of the core including a SystemVerilog wrapper and link it against a C++ testbench (in the `tb` subfolder). The binary can be found in the `work-ver` and accepts a RISC-V ELF binary as an argument, e.g.:
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```
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$ work-ver/Variane_testharness rv64um-v-divuw
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work-ver/Variane_testharness rv64um-v-divuw
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```
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The Verilator testbench makes use of the `riscv-fesvr`.
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This means that you can use the `riscv-tests` repository as well as `riscv-pk` out-of-the-box.
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As a general rule of thumb the Verilator model will behave like Spike (exception for being orders of magnitudes slower).
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The Verilator testbench makes use of the `riscv-fesvr`. This means that you can use the `riscv-tests` repository as well as `riscv-pk` out-of-the-box. As a general rule of thumb the Verilator model will behave like Spike (exception for being orders of magnitudes slower).
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Both the Verilator model as well as the Questa simulation will produce trace logs.
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The Verilator trace is more basic but you can feed the log to `spike-dasm` to resolve instructions to mnemonics.
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Unfortunately value inspection is currently not possible for the Verilator trace file.
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Both, the Verilator model as well as the Questa simulation will produce trace logs. The Verilator trace is more basic but you can feed the log to `spike-dasm` to resolve instructions to mnemonics. Unfortunately value inspection is currently not possible for the Verilator trace file.
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```
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$ spike-dasm < trace_hart_00.dasm > logfile.txt
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spike-dasm < trace_hart_00.dasm > logfile.txt
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```
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To build, compile and run the CVA6 core-only in its example testbench using Verilator (known to work with V4.108):
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@ -135,37 +136,38 @@ $ make veri_run
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### Running User-Space Applications
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It is possible to run user-space binaries on CVA6 with `riscv-pk` ([link](https://github.com/riscv/riscv-pk)).
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It is possible to run user-space binaries on CVA6 with ([RISC-V Proxy Kernel and Boot Loader](https://github.com/riscv/riscv-pk)).
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RISC-V PK can be installed by running: `./ci/install-riscvpk.sh`
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```
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$ mkdir build
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$ cd build
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$ ../configure --prefix=$RISCV --host=riscv64-unknown-elf
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$ make
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$ make install
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mkdir build
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cd build
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../configure --prefix=$RISCV --host=riscv64-unknown-elf
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make
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make install
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```
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Then to run a RISC-V ELF using the Verilator model do:
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```
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$ echo '
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echo '
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#include <stdio.h>
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int main(int argc, char const *argv[]) {
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printf("Hello CVA6!\\n");
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return 0;
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}' > hello.c
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$ riscv64-unknown-elf-gcc hello.c -o hello.elf
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riscv64-unknown-elf-gcc hello.c -o hello.elf
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```
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```
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$ make verilate
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$ work-ver/Variane_testharness $RISCV/riscv64-unknown-elf/bin/pk hello.elf
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make verilate
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work-ver/Variane_testharness $RISCV/riscv64-unknown-elf/bin/pk hello.elf
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```
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If you want to use QuestaSim to run it you can use the following command:
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```
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$ make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf batch-mode=1
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make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf batch-mode=1
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```
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> Be patient! RTL simulation is way slower than Spike. If you think that you ran into problems you can inspect the trace files.
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@ -202,7 +204,7 @@ The first stage bootloader will boot from SD Card by default. Get yourself a sui
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Connect a terminal to the USB serial device opened by the FTDI chip e.g.:
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```
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$ screen /dev/ttyUSB0 115200
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screen /dev/ttyUSB0 115200
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```
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Default baudrate set by the bootlaoder and Linux is `115200`.
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@ -214,7 +216,7 @@ After you've inserted the SD Card and programmed the FPGA you can connect to the
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To generate the FPGA bitstream (and memory configuration) yourself for the Genesys II board run:
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```
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$ make fpga
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make fpga
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```
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This will produce a bitstream file and memory configuration file (in `fpga/work-fpga`) which you can permanently flash by running the above commands.
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@ -239,7 +241,8 @@ Bus 005 Device 019: ID 0403:6010 Future Technology Devices International, Ltd FT
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If this is the case, you can go on and start openocd with the `fpga/ariane.cfg` configuration file:
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```
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$ openocd -f fpga/ariane.cfg
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openocd -f fpga/ariane.cfg
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Open On-Chip Debugger 0.10.0+dev-00195-g933cb87 (2018-09-14-19:32)
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Licensed under GNU GPL v2
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For bug reports, read
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@ -261,7 +264,8 @@ Info : accepting 'gdb' connection on tcp/3333
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Then you will be able to either connect through `telnet` or with `gdb`:
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```
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$ riscv64-unknown-elf-gdb /path/to/elf
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riscv64-unknown-elf-gdb /path/to/elf
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(gdb) target remote localhost:3333
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(gdb) load
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Loading section .text, size 0x6508 lma 0x80000000
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@ -306,7 +310,7 @@ The core has been developed with a full licensed version of QuestaSim. If you ha
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To specify the test to run use (e.g.: you want to run `rv64ui-p-sraw` inside the `tmp/risc-tests/build/isa` folder:
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```
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$ make sim elf-bin=path/to/rv64ui-p-sraw
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make sim elf-bin=path/to/rv64ui-p-sraw
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```
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If you call `sim` with `batch-mode=1` it will run without the GUI. QuestaSim uses `riscv-fesvr` for communication as well.
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@ -320,17 +324,17 @@ If you would like to run the CI test suites locally on your machine, follow any
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Once everything is set up and installed, you can run the tests suites as follows (using Verilator):
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```
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$ make verilate
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$ make run-asm-tests-verilator
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$ make run-benchmarks-verilator
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make verilate
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make run-asm-tests-verilator
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make run-benchmarks-verilator
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```
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In order to run randomized Torture tests, you first have to generate the randomized program prior to running the simulation:
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```
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$ ./ci/get-torture.sh
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$ make torture-gen
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$ make torture-rtest-verilator
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./ci/get-torture.sh
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make torture-gen
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make torture-rtest-verilator
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```
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This runs the randomized program on Spike and on the RTL target, and checks whether the two signatures match. The random instruction mix can be configured in the `./tmp/riscv-torture/config/default.config` file.
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@ -345,12 +349,12 @@ This will dump a file called `trace_hart_*_*_commit.log`.
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This can be helpful for debugging long traces (e.g.: torture traces). To compile Spike with the commit log feature do:
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```
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$ apt-get install device-tree-compiler
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$ mkdir build
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$ cd build
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$ ../configure --prefix=$RISCV --with-fesvr=$RISCV --enable-commitlog
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$ make
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$ [sudo] make install
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apt-get install device-tree-compiler
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mkdir build
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cd build
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../configure --prefix=$RISCV --with-fesvr=$RISCV --enable-commitlog
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make
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make install
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```
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### Memory Preloading
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@ -362,7 +366,7 @@ to a binary which will be preloaded.
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> You will loose all `riscv-fesvr` communcation like sytemcalls and eoc capabilities.
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```
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$ make sim preload=elf
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make sim preload=elf
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```
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<!-- ### Tandem Verification with Spike
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16
ci/install-riscvpk.sh
Executable file
16
ci/install-riscvpk.sh
Executable file
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@ -0,0 +1,16 @@
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#!/bin/bash
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set -e
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ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
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PATH=$RISCV/bin:/bin:$PATH
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cd $ROOT/tmp
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echo "Installing RISC-V Proxy Kernel and Boot Loader"
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git clone https://github.com/riscv-software-src/riscv-pk.git
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cd riscv-pk
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mkdir -p build
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cd build
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../configure --prefix=$RISCV --host=riscv64-unknown-elf
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make
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make install
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@ -15,7 +15,10 @@ sudo apt install verilator-4.100 device-tree-compiler
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ci/make-tmp.sh
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sudo mkdir -p $RISCV && sudo chmod 777 $RISCV
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wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14.tar.gz
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tar -x -f riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14.tar.gz --strip-components=1 -C $RISCV
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RISCV64_UNKNOWN_ELF_GCC=riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14.tar.gz
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if [ ! -f "$RISCV64_UNKNOWN_ELF_GCC" ]; then
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wget https://static.dev.sifive.com/dev-tools/$RISCV64_UNKNOWN_ELF_GCC
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fi
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tar -x -f $RISCV64_UNKNOWN_ELF_GCC --strip-components=1 -C $RISCV
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ci/install-fesvr.sh
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ci/build-riscv-tests.sh
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