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Performance tb (#2562)

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For reminder, the option --issrun_opts="+tb_performance_mode" allows to disable UVM features like assertion and log generation to reduce simulation time.
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Anouar 2024-10-23 12:11:25 +01:00 • committed by GitHub
parent 21dc824040
commit 20b64e8939
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5 changed files with 29 additions and 5 deletions
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3
verif/regress/coremark.sh
View file

@ -38,6 +38,8 @@ if ! [ -n "$UVM_VERBOSITY" ]; then
export UVM_VERBOSITY=UVM_NONE
fi
export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
make clean
make -C verif/sim clean_all
@ -92,5 +94,4 @@ python3 cva6.py \
--c_tests "$src0" \
--gcc_opts "${srcA[*]} ${cflags[*]}" \
--iss_timeout=2000 \
--issrun_opts="+tb_performance_mode" \
$DV_OPTS

7
verif/regress/dhrystone.sh
View file

@ -29,6 +29,12 @@ if ! [ -n "$DV_HWCONFIG_OPTS" ]; then
DV_HWCONFIG_OPTS="cv32a65x"
fi
if ! [ -n "$UVM_VERBOSITY" ]; then
export UVM_VERBOSITY=UVM_NONE
fi
export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
make clean
make -C verif/sim clean_all
@ -63,5 +69,4 @@ python3 cva6.py \
--iss="$DV_SIMULATORS" \
--iss_yaml=cva6.yaml \
--c_tests "$src0" \
--issrun_opts="+tb_performance_mode" \
--gcc_opts "${srcA[*]} ${cflags[*]}"

8
verif/regress/dv-riscv-arch-test.sh
View file

@ -35,5 +35,11 @@ else
TESTLIST=../tests/testlist_riscv-arch-test-$DV_TARGET.yaml
fi
if ! [ -n "$UVM_VERBOSITY" ]; then
export UVM_VERBOSITY=UVM_NONE
fi
export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
cd verif/sim
python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS --issrun_opts="+tb_performance_mode" $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld

8
verif/regress/dv-riscv-compliance.sh
View file

@ -28,6 +28,12 @@ if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness,spike
fi
if ! [ -n "$UVM_VERBOSITY" ]; then
export UVM_VERBOSITY=UVM_NONE
fi
export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
cd verif/sim
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS --issrun_opts="+tb_performance_mode" $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS
cd -

8
verif/regress/dv-riscv-tests.sh
View file

@ -33,9 +33,15 @@ if ! [ -n "$DV_TESTLISTS" ]; then
../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
fi
if ! [ -n "$UVM_VERBOSITY" ]; then
export UVM_VERBOSITY=UVM_NONE
fi
export DV_OPTS="$DV_OPTS --issrun_opts=+tb_performance_mode+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
cd verif/sim
for TESTLIST in $DV_TESTLISTS
do
python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --issrun_opts="+tb_performance_mode" $DV_OPTS
python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS
done
cd -