manage all HW config parameters (#1047)

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cathales 2023-02-07 23:35:38 +01:00 committed by GitHub
parent cfef3e9c12
commit 215b45037e
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GPG key ID: 4AEE18F83AFDEB23
2 changed files with 24 additions and 0 deletions

3
.gitignore vendored
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@ -40,3 +40,6 @@ tb/riscv-isa-sim/
work-*/*
install/
xrun_results/
/core/include/gen32_config_pkg.sv
/core/include/gen64_config_pkg.sv
__pycache__

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@ -49,6 +49,20 @@ def setup_parser_config_generator():
help="Data User Width ? [1-64]")
parser.add_argument("--RenameEn", type=int, default=None, choices=[0,1],
help="RenameEn ? 1 : enable, 0 : disable")
parser.add_argument("--IcacheSetAssoc", type=int, default=None,
help="Instruction cache associativity")
parser.add_argument("--DcacheSetAssoc", type=int, default=None,
help="Data cache associativity")
parser.add_argument("--NrCommitPorts", type=int, default=None, choices=[1,2],
help="Number of commit ports")
parser.add_argument("--NrScoreboardEntries", type=int, default=None,
help="Number of scoreboard entries")
parser.add_argument("--FPGAEn", type=int, default=None, choices=[0,1],
help="Use FPGA-specific hardware")
parser.add_argument("--NrLoadPipeRegs", type=int, default=None,
help="Load latency")
parser.add_argument("--NrStorePipeRegs", type=int, default=None,
help="Store latency")
return parser
ISA = ""
@ -70,6 +84,13 @@ MapArgsToParameter={
"duser_en" : "CVA6ConfigDataUserEn",
"duser_w" : "CVA6ConfigDataUserWidth",
"RenameEn" : "CVA6ConfigRenameEn",
"IcacheSetAssoc" : "CVA6ConfigIcacheSetAssoc",
"DcacheSetAssoc" : "CVA6ConfigDcacheSetAssoc",
"NrCommitPorts" : "CVA6ConfigNrCommitPorts",
"NrScoreboardEntries" : "CVA6ConfigNrScoreboardEntries",
"FPGAEn" : "CVA6ConfigFPGAEn",
"NrLoadPipeRegs" : "CVA6ConfigNrLoadPipeRegs",
"NrStorePipeRegs" : "CVA6ConfigNrStorePipeRegs",
}
MapParametersToArgs = {i:k for k, i in MapArgsToParameter.items()} #reverse map