Add initial riscv-config input specs, validation harness and YAML outputs for CV32A65X. (#2133)

config/riscv-config/Makefile

@@ -0,0 +1,46 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Zbigniew CHAMSKI - Thales
+
+RVCONFIG_DIR ?= $(shell pwd)/../../vendor/riscv/riscv-config
+
+# Name of the target to process
+TARGET ?= cv32a65x
+
+# List of component files (inputs and processed)
+COMPONENTS = isa custom platform
+SPEC_DIR = $(TARGET)/spec
+GEN_DIR  = $(TARGET)/generated
+RVCONFIG_INPUTS = $(patsubst %,$(SPEC_DIR)/%_spec.yaml,$(COMPONENTS))
+# NOTE: names of the generated files are imposed by riscv-config.
+RVCONFIG_OUTPUTS= $(patsubst %,$(GEN_DIR)/%_spec_checked.yaml,$(COMPONENTS))
+OUTPUT_FILES    = $(patsubst %,$(GEN_DIR)/%_gen.yaml,$(COMPONENTS))
+
+all: $(OUTPUT_FILES)
+
+$(GEN_DIR)/%_gen.yaml: $(GEN_DIR)/%_spec_checked.yaml
+	cp $< $@
+
+$(RVCONFIG_OUTPUTS): $(RVCONFIG_INPUTS) Makefile
+	cd $(RVCONFIG_DIR) ; pip3 install -r requirements.txt
+	export PYTHONPATH=$(RVCONFIG_DIR) ; \
+	  python3 -m riscv_config.main \
+	  --work_dir $(GEN_DIR) \
+	  -ispec $(SPEC_DIR)/isa_spec.yaml \
+	  -cspec $(SPEC_DIR)/custom_spec.yaml \
+	  -pspec $(SPEC_DIR)/platform_spec.yaml
+
+clean:
+	$(RM) $(OUTPUT_FILES) $(RVCONFIG_OUTPUTS)

config/riscv-config/README.md

@@ -0,0 +1,43 @@
+<!--
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Zbigniew CHAMSKI - Thales
+-->
+
+# File organization
+
+- `Makefile`: the makefile needed to regenerate the Yaml files using `riscv-config`.
+- `TARGET`: directory holding input and output files for configuration named `TARGET` (currently only `cv32a65x`)
+  - `spec`: Directory holding input files
+    - `isa_spec.yaml`: specification of the ISA, including CSRs and privileges (expressed as canonical extension letters)
+    - `custom_spec.yaml`: specification of custom CSRs
+    - `platform_spec.yaml`: specification of platform-level values/properties
+  - `generated`: Directory holding generated files produced by `riscv-config` from the spec files
+    - `isa_gen.yaml`: ISA definition completed y `riscv-config`
+    - `custom_gen.yaml`: Custom CSR definitions completed by `riscv-config`
+    - `platform_gen.yaml`: Platform-specific values/properties completed by `riscv-config`
+
+# Prerequisites
+
+- Python3 (tested with 3.9 on RedHat Enterprise Linux 8)
+
+# Invocation
+
+From any directory, run
+
+```
+make -C <CVA6_top_directory>/config/riscv-config all
+```
+

config/riscv-config/cv32a65x/generated/custom_gen.yaml

@@ -0,0 +1,73 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Zbigniew CHAMSKI - Thales
+
+hart_ids: [0]
+hart0:
+    icache:
+        reset-val: 0x1
+        rv64:
+            accessible: false
+        rv32:
+            accessible: true
+            icache:
+                implemented: true
+                type:
+                    rw: true
+                description: bit for cache-enable of instruction cache
+                shadow:
+                shadow_type:
+                msb: 0
+                lsb: 0
+            reserved_0:
+                implemented: true
+                description: reserved for future use
+                type:
+                    ro_constant: 0x0
+                shadow:
+                shadow_type:
+                msb: 31
+                lsb: 1
+            fields:
+              - icache
+              - reserved_0
+        description: the register controls the operation of the i-cache unit.
+        address: 0x7c0
+        priv_mode: M
+    dcache:
+        reset-val: 0x1
+        rv64:
+            accessible: false
+        rv32:
+            accessible: true
+            dcache:
+                implemented: true
+                type:
+                    rw: true
+                description: bit for cache-enable of data cache
+                shadow:
+                shadow_type:
+                msb: 0
+                lsb: 0
+            fields:
+              - dcache
+              -
+                  -
+                      - 1
+                      - 31
+        description: the register controls the operation of the d-cache unit.
+        address: 0x7c1
+        priv_mode: M
+

config/riscv-config/cv32a65x/generated/platform_gen.yaml

@@ -0,0 +1,33 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Zbigniew CHAMSKI - Thales
+
+nmi:
+    label: nmi_vector
+reset:
+    label: reset_vector
+mtime:
+    implemented: true
+    address: 0x20000
+mtimecmp:
+    implemented: false
+mtval_condition_writes:
+    implemented: false
+scause_non_standard:
+    implemented: false
+stval_condition_writes:
+    implemented: false
+zicbo_cache_block_sz:
+    implemented: false

config/riscv-config/cv32a65x/spec/custom_spec.yaml

@@ -0,0 +1,64 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Zbigniew CHAMSKI - Thales
+
+hart_ids: [0]
+hart0:
+    icache:
+      reset-val: 0x1
+      rv64:
+        accessible: false
+      rv32:
+        accessible: true
+        icache:
+          implemented: true
+          type:
+            rw: true
+          description: bit for cache-enable of instruction cache
+          shadow:
+          shadow_type:
+          msb: 0
+          lsb: 0
+        reserved_0:
+          implemented: true
+          description: reserved for future use
+          type:
+            ro_constant: 0x0
+          shadow:
+          shadow_type:
+          msb: 31
+          lsb: 1
+      description: the register controls the operation of the i-cache unit.
+      address: 0x7c0
+      priv_mode: M
+    dcache:
+      reset-val: 0x1
+      rv64:
+        accessible: false
+      rv32:
+        accessible: true
+        dcache:
+          implemented: true
+          type:
+            rw: true
+          description: bit for cache-enable of data cache
+          shadow:
+          shadow_type:
+          msb: 0
+          lsb: 0
+      description: the register controls the operation of the d-cache unit.
+      address: 0x7c1
+      priv_mode: M
+

config/riscv-config/cv32a65x/spec/platform_spec.yaml

@@ -0,0 +1,23 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# Original Author: Zbigniew CHAMSKI - Thales
+
+nmi:
+  label: nmi_vector
+reset:
+  label: reset_vector
+mtime:
+  implemented: True
+  address: 0x20000