Include pcgen and controller stub

include/ariane_pkg.svh

@@ -44,7 +44,7 @@ package ariane_pkg;
         logic [63:0] target_address;
         logic        is_taken;
         logic        valid; // is miss-predict
-    } misspredict;
+    } mispredict;
 
     typedef enum logic[3:0] {
         NONE, LSU, ALU, MULT, CSR

src/btb.sv

@@ -28,7 +28,7 @@ module btb #(
     input  logic            flush_i,                   // flush the btb
 
     input  logic [63:0]     vpc_i,                     // virtual PC from IF stage
-    input  misspredict      misspredict_i,             // a miss-predict happened -> update data structure
+    input  mispredict       mispredict_i,             // a miss-predict happened -> update data structure
 
     output logic            is_branch_o,               // instruction at vpc_i is a branch
     output logic            predict_taken_o,           // the branch is taken
@@ -51,7 +51,7 @@ module btb #(
     // get actual index positions
     // we ignore the 0th bit since all instructions are aligned on
     // a half word boundary
-    assign update_pc = misspredict_i.pc[$clog2(NR_ENTRIES) + OFFSET - 1:OFFSET];
+    assign update_pc = mispredict_i.pc[$clog2(NR_ENTRIES) + OFFSET - 1:OFFSET];
     assign index     = vpc_i[$clog2(NR_ENTRIES) + OFFSET - 1:OFFSET];
 
     // we combinatorially predict the branch and the target address
@@ -60,29 +60,29 @@ module btb #(
     assign branch_target_address_o = btb_q[$unsigned(index)].target_address;
 
     // update on a miss-predict
-    always_comb begin : update_misspredict
+    always_comb begin : update_mispredict
         btb_n              = btb_q;
         saturation_counter = btb_q[$unsigned(update_pc)].saturation_counter;
 
-        if (misspredict_i.valid) begin
+        if (mispredict_i.valid) begin
             btb_n[$unsigned(update_pc)].valid = 1'b1;
             // update saturation counter
             // first check if counter is already saturated in the positive regime e.g.: branch taken
-            if (saturation_counter == {BITS_SATURATION_COUNTER{1'b1}} && ~misspredict_i.is_taken) begin
+            if (saturation_counter == {BITS_SATURATION_COUNTER{1'b1}} && ~mispredict_i.is_taken) begin
                 // we can safely decrease it
                 btb_n[$unsigned(update_pc)].saturation_counter = saturation_counter - 1;
             // then check if it saturated in the negative regime e.g.: branch not taken
-            end else if (saturation_counter == {BITS_SATURATION_COUNTER{1'b0}} && misspredict_i.is_taken) begin
+            end else if (saturation_counter == {BITS_SATURATION_COUNTER{1'b0}} && mispredict_i.is_taken) begin
                 // we can safely increase it
                 btb_n[$unsigned(update_pc)].saturation_counter = saturation_counter + 1;
             end else begin // otherwise we are not in any boundaries and can decrease or increase it
-                if (misspredict_i.is_taken)
+                if (mispredict_i.is_taken)
                     btb_n[$unsigned(update_pc)].saturation_counter = saturation_counter + 1;
                 else
                     btb_n[$unsigned(update_pc)].saturation_counter = saturation_counter - 1;
             end
             // the target address is simply updated
-            btb_n[$unsigned(update_pc)].target_address = misspredict_i.target_address;
+            btb_n[$unsigned(update_pc)].target_address = mispredict_i.target_address;
         end
     end
 

src/controller.sv

@@ -0,0 +1,32 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 08.05.2017
+// Description: Flush controller
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+//
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+//
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+//
+
+import ariane_pkg::*;
+
+module controller (
+    input  logic      clk_i,    // Clock
+    input  logic      rst_ni,   // Asynchronous reset active low
+
+    input  logic      flush_commit_i, // flush request from commit stage in
+    input  logic      mispredict_i,
+
+    output mispredict mispredict_o // to pcgen update branch history table
+);
+
+endmodule

src/pcgen.sv

@@ -15,4 +15,37 @@
 // SolderPad open hardware license in the context of the PULP platform
 // (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
 // University of Bologna.
-//
+//
+
+import ariane_pkg::*;
+
+module pcgen (
+    input  logic        clk_i,                    // Clock
+    input  logic        rst_ni,                   // Asynchronous reset active low
+
+    input  logic        flush_i,
+    input  logic [63:0] pc_if_i,
+    input  mispredict   mispredict_i,             // from controller signaling a mispredict -> update BTB
+    // to IF
+    output logic [63:0] branch_target_address_o,
+    output logic        predict_taken_o,          // btb thinks we should take that branch
+    output logic        is_branch_o               // to check if we mispredicted
+);
+
+
+    btb #(
+        .NR_ENTRIES(64),
+        .BITS_SATURATION_COUNTER(2)
+    )
+    btb_i
+    (
+        .vpc_i                   ( pc_if_i                 ),
+        .misspredict_i           ( misspredict_i           ),
+        .is_branch_o             ( is_branch_o             ),
+        .predict_taken_o         ( predict_taken_o         ),
+        .branch_target_address_o ( branch_target_address_o ),
+        .*
+    );
+
+
+endmodule

test/add_test.S

@@ -10,6 +10,7 @@
     add  x6, x4, x5
     add  x7, x5, x6
     add  x8, x6, x7
+    csrw mstatus, x7
     add  x9, x7, x8
     csrr x1, mstatus
     nop