First release identifier is v0.1.0 (#994)

docs/.gitignore

@@ -1,2 +1,3 @@
 *~
 /_build
+*.swp

docs/design_spec/source/conf.py

@@ -37,7 +37,7 @@
 
 # -- Project information -----------------------------------------------------
 
-project = u'CORE-V CV32A6-step1 Design Document'
+project = u'CORE-V CV32A6 v0.1.0 Design Document'
 copyright = u'2022, Thales Group'
 author = u'Thales and OpenHW Group'
 
@@ -134,7 +134,7 @@ html_static_path = []
 # -- Options for HTMLHelp output ---------------------------------------------
 
 # Output file base name for HTML help builder.
-htmlhelp_basename = 'CORE-V_CV32A6-step1_DESIGN_DOC'
+htmlhelp_basename = 'CORE-V_CV32A6_V0.1.0_DESIGN_DOC'
 
 
 # -- Options for LaTeX output ------------------------------------------------
@@ -161,7 +161,7 @@ latex_elements = {
 # (source start file, target name, title,
 #  author, documentclass [howto, manual, or own class]).
 latex_documents = [
-    (master_doc, 'CV32A6-step1_Design_Spec.tex', u'CORE-V-Docs Documentation',
+    (master_doc, 'CV32A6-v0.1.0_Design_Spec.tex', u'CORE-V-Docs Documentation',
      u'Jean-Roch Coulon', 'manual'),
 ]
 
@@ -171,7 +171,7 @@ latex_documents = [
 # One entry per manual page. List of tuples
 # (source start file, name, description, authors, manual section).
 man_pages = [
-    (master_doc, 'CV32A6-step1_Design_Spec.tex', u'CORE-V-Docs Documentation',
+    (master_doc, 'CV32A6-v0.1.0_Design_Spec.tex', u'CORE-V-Docs Documentation',
      [author], 1)
 ]
 
@@ -182,8 +182,8 @@ man_pages = [
 # (source start file, target name, title, author,
 #  dir menu entry, description, category)
 texinfo_documents = [
-    (master_doc, 'CV32A6-step1_Design_Spec.tex', u'CORE-V-Docs Documentation',
-     author, 'UserManual', 'User Manual for CV32A6-step1 CORE-V processor core.',
+    (master_doc, 'CV32A6-v0.1.0_Design_Spec.tex', u'CORE-V-Docs Documentation',
+     author, 'UserManual', 'User Manual for CV32A6 v0.1.0 CORE-V processor core.',
      'Miscellaneous'),
 ]
 

docs/design_spec/source/cva6_frontend.rst

@@ -173,7 +173,7 @@ PC gen generates the next program counter. The next PC can originate from the fo
 
   + 3) If instruction is a RET and RAS (Return Address Stack) returns a valid address and RET has already been consummed by instruction queue. Else RET is considered as a control flow instruction but next PC is not predicted. A mispredict wil be generated.
 
-  Then the PC gen informs the Fetch stage that it performed a prediction on the PC. *In CV32A6-step1, Branch Prediction is simplified: no information is stored in BTB, BHT and RAS. JALR, branch and RET instructions are not considered as control flow instruction and will generates mispredict.*
+  Then the PC gen informs the Fetch stage that it performed a prediction on the PC. *In CV32A6 v0.1.0, Branch Prediction is simplified: no information is stored in BTB, BHT and RAS. JALR, branch and RET instructions are not considered as control flow instruction and will generates mispredict.*
 
 * **Default:** PC + 4 is fetched. PC Gen always fetches on a word boundary (32-bit). Compressed instructions are handled by fetch stage.
 
@@ -187,9 +187,9 @@ PC gen generates the next program counter. The next PC can originate from the fo
 
 * **Pipeline Flush:** When a CSR with side-effects gets written the whole pipeline is flushed by CONTROLLER and FRONTEND starts fetching from the next instruction again in order to take the up-dated information into account (for example virtual memory base pointer changes). The PC related to the flush action is provided by the COMMIT. Moreover flush is also transmitted to the CACHES through the next fetch CACHES access and instruction queue is reset.
 
-* **Debug:** Debug has the highest order of precedence as it can interrupt any control flow requests. It also the only source of control flow change which can actually happen simultaneously to any other of the forced control flow changes. The debug jump is requested by CSR. The address to be jumped into is HW coded. This debug feature is not supported by  cv32a6-step1.
+* **Debug:** Debug has the highest order of precedence as it can interrupt any control flow requests. It also the only source of control flow change which can actually happen simultaneously to any other of the forced control flow changes. The debug jump is requested by CSR. The address to be jumped into is HW coded. This debug feature is not supported by CV32A6 v0.1.0.
 
-All program counters are logical addressed. If the logical to physical mapping changes a fence.vm instruction should used to flush the pipeline *and TLBs (MMU is not enabled in CV32A6-step1)*.
+All program counters are logical addressed. If the logical to physical mapping changes a fence.vm instruction should used to flush the pipeline *and TLBs (MMU is not enabled in CV32A6 v0.1.0)*.
 
 
 
@@ -198,9 +198,9 @@ Fetch Stage
 
 Fetch stage controls by handshake protocol the CACHE module. Fetched data are 32-bit block with word aligned address. A granted fetch is realigned into instr_realign submodule to produce instructions. Then instructions are pushed into an internal instruction FIFO called instruction queue (instr_queue submodule). This submodule stores the instructions and related information which allow to identify the outstanding transactions. In the case CONTROLLER decides to flush the instruction queue, the outstanding transactions are discarded.
 
-*The Fetch stage asks the MMU (MMU is not enabled in CV32A6-step1) to translate the requested address.*
+*The Fetch stage asks the MMU (MMU is not enabled in CV32A6 v0.1.0) to translate the requested address.*
 
-Memory *and MMU (MMU is not enabled in CV32A6-step1)* can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults.
+Memory *and MMU (MMU is not enabled in CV32A6 v0.1.0)* can feedback potential exceptions generated by the memory fetch request. They can be bus errors, invalid accesses or instruction page faults.
 
 
 

docs/design_spec/source/cva6_intro.rst

@@ -12,10 +12,12 @@
 Introduction
 =============
 
-The objective of this document is to provide enough information to allow the RTL modification (by designers) and the RTL verification (by verificators). This document is not dedicated to CVA6 users looking at information to develop software like instructions or registers.
-
-CVA6 is a 6-stage in-order and single issue processor core which implements the RISC-V instruction set. Many features in the RISC-V specification are optional, and CVA6 can be parameterized to enable or disable some of them. CVA6 can be configured as a 32- or 64-bit core (RV32 or RV64), called CV32A6 or CV64A6. This document describes the CV32A6 processor configuration which allows to connect coprocessor through CV-X-IF but without Linux support, called CV32A6-step1. It is a first step towards the verification of CV32A6.
+CVA6 is a 6-stage in-order and single issue processor core which implements the RISC-V instruction set.
+CVA6 can be configured as a 32- or 64-bit core (RV32 or RV64), called CV32A6 or CV64A6.
+This document describes an initial version (v0.1.0) of the CV32A6 processor configuration.
 
+The objective of this document is to provide enough information to allow the RTL modification (by designers) and the RTL verification (by verificators).
+This document is not dedicated to CVA6 users looking for information to develop software like instructions or registers.
 
 The CVA6 architecture is illustrated in the following figure extracted from a paper written by F.Zaruba and L.Benini.
 

docs/design_spec/source/cva6_system.rst

@@ -10,18 +10,37 @@
 .. _CVA6_SUBSYSTEM:
 
 
-CV32A6-step1 Subsystem
-======================
+CV32A6 v0.1.0 Subsystem
+========================
 
 Description
 -----------
 
-The CV32A6-step1 is a subsystem composed of the modules and protocol interfaces as illustrated in the figure. The processor is a Harvard-based modern architecture. Instructions are issued in-order through the DECODE stage and executed out-of-order but committed in-order. The processor is Single issue, that means that at maximum one instruction per cycle can be issued to the EXECUTE stage.
+The CV32A6 v0.1.0 is a subsystem composed of the modules and protocol interfaces as illustrated `CV32A6 v0.1.0 modules`_
+The processor is a Harvard-based modern architecture.
+Instructions are issued in-order through the DECODE stage and executed out-of-order but committed in-order.
+The processor is Single issue, that means that at maximum one instruction per cycle can be issued to the EXECUTE stage.
 
-The CV32A6 implements a 6-stage pipeline composed of PC Generation, Instruction Detch, Instruction Decode, Issue stage, Execute stage and Commit stage. At least 6 cycles are needed to execute one instruction.
+The CV32A6 implements a 6-stage pipeline composed of PC Generation, Instruction Detch, Instruction Decode, Issue stage, Execute stage and Commit stage.
+At least 6 cycles are needed to execute one instruction.
 
+Instantiation
+^^^^^^^^^^^^^
 
-.. list-table:: cv32a6-step1 interface signals
+.. list-table:: CV32A6 v0.1.0 parameterization
+   :header-rows: 1
+
+   * - Parameter
+     - Type
+     - Value
+     - Description
+
+   * - ``ArianeCfg``
+     - ariane_pkg::ariane_cfg_t
+     - ariane_pkg::v0.1.0_Config
+     - CVA6 v0.1.0 configuration
+
+.. list-table:: CV32A6 v0.1.0 interface signals
    :header-rows: 1
 
    * - Signal
@@ -99,9 +118,9 @@ The CV32A6 implements a 6-stage pipeline composed of PC Generation, Instruction
 Functionality
 -------------
 
-CV32A6-step1 implements a configuration which allows to connect coprocessor through CV-X-IF coprocessor interface, but the lack of MMU, A extension and data cache prevent from executing Linux.
+CV32A6 v0.1.0 implements a configuration which allows to connect coprocessor through CV-X-IF coprocessor interface, but the lack of MMU, A extension and data cache prevent from executing Linux.
 
-.. list-table:: CV32A6-step1 Standard Configuration
+.. list-table:: CV32A6 v0.1.0 Standard Configuration
    :header-rows: 1
 
    * - Standard Extension
@@ -165,7 +184,7 @@ CV32A6-step1 implements a configuration which allows to connect coprocessor thro
      - OFF
 
 
-.. list-table:: CV32A6-step1 Micro-Architecture Configuration
+.. list-table:: CV32A6 v0.1.0 Micro-Architecture Configuration
    :header-rows: 1
 
    * - Micro-architecture
@@ -197,7 +216,7 @@ CVA6 memory interface complies with AXI5 specification including the Atomic_Tran
 
 CVA6 coprocessor interface complies with CV-X-IF protocol specification as defined in [CV-X-IF].
 
-The CV32A4-step1 core is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.
+The CV32A6 v0.1.0 core is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.
 
 For ASIC synthesis, the whole design is completely synchronous and uses positive-edge triggered flip-flops. The core occupies an area of about 80 kGE. The clock frequency can be more than 1GHz depending of technology.
 
@@ -205,14 +224,14 @@ For ASIC synthesis, the whole design is completely synchronous and uses positive
 Architecture and Modules
 ----------------------------
 
-The cv32a6-step1 subsystem is composed of 8 modules.
+The CV32A6 v0.1.0 subsystem is composed of 8 modules.
 
 .. figure:: ../images/subsystems.png
-   :name: CVA6 modules
+   :name: CV32A6 v0.1.0 modules
    :align: center
    :alt:
 
-   CV32A6-step1 modules
+   CV32A6 v0.1.0 modules
 
 Connections between modules are illustrated in the following block diagram. FRONTEND, DECODE, ISSUE, EXECUTE, COMMIT and CONTROLLER are part of the pipeline. And CACHES implements the instruction and data caches and CSRFILE contains registers.
 
@@ -221,5 +240,5 @@ Connections between modules are illustrated in the following block diagram. FRON
    :align: center
    :alt:
 
-   CV32A6-step1 pipeline and modules
+   CV32A6 v0.1.0 pipeline and modules
 

docs/design_spec/source/index.rst

@@ -15,8 +15,8 @@
 
    SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-OpenHW Group CV32A6-step1 design Document
-=========================================
+OpenHW Group CV32A6 v0.1.0 Design Document
+==========================================
 
 .. toctree::
    :maxdepth: 3