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Instantiate csr address buffer in ex

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This commit is contained in:
Florian Zaruba 2017-05-05 12:42:03 +02:00
parent decde29bb3
commit 2430599328
4 changed files with 65 additions and 22 deletions
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2
include/ariane_pkg.svh
View file

@ -15,7 +15,7 @@ package ariane_pkg;
localparam NR_SB_ENTRIES = 4; // number of scoreboard entries
localparam TRANS_ID_BITS = $clog2(NR_SB_ENTRIES); // depending on the number of scoreboard entries we need that many bits
// to uniquely identify the entry in the scoreboard
localparam NR_WB_PORTS = 2;
localparam NR_WB_PORTS = 3;
localparam ISA_CODE = (1 << 2) // C - Compressed extension
| (1 << 8) // I - RV32I/64I/128I base ISA
| (1 << 12) // M - Integer Multiply/Divide extension

44
src/ariane.sv
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@ -121,11 +121,18 @@ module ariane
logic mult_ready_ex_id;
logic mult_valid_ex_id;
// CSR
logic csr_ready_ex_id;
logic csr_valid_id_ex;
logic [TRANS_ID_BITS-1:0] csr_trans_id_ex_id;
logic [63:0] csr_result_ex_id;
logic csr_valid_ex_id;
// --------------
// EX <-> COMMIT
// --------------
// LSU Commit
logic csr_commit_commit_ex;
logic lsu_commit_commit_ex;
// CSR Commit
// --------------
// ID <-> COMMIT
@ -155,6 +162,8 @@ module ariane
logic [37:0] pd_ppn_csr_ex;
logic [0:0] asid_csr_ex;
logic flush_tlb_csr_ex;
logic [11:0] csr_addr_ex_csr;
// TODO: Preliminary signal assignments
logic flush_tlb;
@ -201,6 +210,7 @@ module ariane
.pc_if_i ( pc_if_if_id ), // PC from if
.ex_if_i ( exception_if_id ), // exception from if
.ready_o ( ready_id_if ),
// Functional Units
.operator_o ( operator_id_ex ),
.operand_a_o ( operand_a_id_ex ),
.operand_b_o ( operand_b_id_ex ),
@ -233,6 +243,14 @@ module ariane
.*
);
ex_stage ex_stage_i (
.flush_i ( flush ),
.operator_i ( operator_id_ex ),
@ -241,33 +259,41 @@ module ariane
.imm_i ( imm_id_ex ),
.trans_id_i ( trans_id_id_ex ),
.comparison_result_o ( ),
// ALU
.alu_ready_o ( alu_ready_ex_id ),
.alu_valid_i ( alu_valid_id_ex ),
.alu_result_o ( alu_result_ex_id ),
.alu_trans_id_o ( alu_trans_id_ex_id ),
.alu_valid_o ( alu_valid_ex_id ),
// LSU
.lsu_ready_o ( lsu_ready_ex_id ),
.lsu_valid_i ( lsu_valid_id_ex ),
.lsu_result_o ( lsu_result_ex_id ),
.lsu_trans_id_o ( lsu_trans_id_ex_id ),
.lsu_valid_o ( lsu_valid_ex_id ),
.lsu_commit_i ( ), // from commit
.lsu_commit_i ( lsu_commit_commit_ex ), // from commit
.lsu_exception_o ( lsu_exception_ex_id ),
// CSR
.csr_ready_o ( csr_ready_ex_id ),
.csr_valid_i ( csr_valid_id_ex ),
.csr_trans_id_o ( csr_trans_id_ex_id ),
.csr_result_o ( csr_result_ex_id ),
.csr_valid_o ( csr_valid_ex_id ),
.csr_addr_o ( csr_addr_ex_csr ),
.csr_commit_i ( csr_commit_commit_ex ), // from commit
// memory management
.enable_translation_i ( 1'b0 ), // from CSR
.enable_translation_i ( 1'b0 ), // from CSR
.fetch_req_i ( fetch_req_if_ex ),
.fetch_gnt_o ( fetch_gnt_ex_if ),
.fetch_valid_o ( fetch_valid_ex_if ),
.fetch_err_o ( fetch_err_o ),
.fetch_vaddr_i ( fetch_vaddr_if_ex ),
.fetch_rdata_o ( fetch_rdata_ex_if ),
.priv_lvl_i ( priv_lvl ), // from CSR
.flag_pum_i ( flag_pum_csr_ex ), // from CSR
.flag_mxr_i ( flag_mxr_csr_ex ), // from CSR
.pd_ppn_i ( pd_ppn_csr_ex ), // from CSR
.asid_i ( asid_csr_ex ), // from CSR
.priv_lvl_i ( priv_lvl ), // from CSR
.flag_pum_i ( flag_pum_csr_ex ), // from CSR
.flag_mxr_i ( flag_mxr_csr_ex ), // from CSR
.pd_ppn_i ( pd_ppn_csr_ex ), // from CSR
.asid_i ( asid_csr_ex ), // from CSR
.flush_tlb_i ( flush_tlb ),
.mult_ready_o ( mult_ready_ex_id ),

35
src/ex_stage.sv
View file

@ -47,6 +47,14 @@ module ex_stage #(
output logic [TRANS_ID_BITS-1:0] lsu_trans_id_o,
input logic lsu_commit_i,
output exception lsu_exception_o,
// CSR
output logic csr_ready_o,
input logic csr_valid_i,
output logic [TRANS_ID_BITS-1:0] csr_trans_id_o,
output logic [63:0] csr_result_o,
output logic csr_valid_o,
output logic [11:0] csr_addr_o,
input logic csr_commit_i,
// memory management
input logic enable_translation_i,
input logic fetch_req_i,
@ -88,7 +96,9 @@ module ex_stage #(
assign alu_ready_o = 1'b1;
assign alu_valid_o = alu_valid_i;
assign alu_trans_id_o = trans_id_i;
// -----
// ALU
// -----
alu alu_i (
.adder_result_o ( ),
.adder_result_ext_o ( ),
@ -97,17 +107,24 @@ module ex_stage #(
.is_equal_result_o ( ),
.*
);
// ----------------
// Multiplication
// ----------------
// TODO
// ----------------
// Load-Store Unit
lsu i_lsu (
.lsu_trans_id_i ( trans_id_i ),
.commit_i ( lsu_commit_i ),
// ----------------
lsu lsu_i (
.commit_i ( lsu_commit_i ),
.*
);
// -----
// CSR
// -----
csr_buffer csr_buffer_i (
.commit_i ( csr_commit_i ),
.*
);
// pass through
endmodule

6
src/lsu.sv
View file

@ -31,7 +31,7 @@ module lsu #(
input logic [63:0] imm_i,
output logic lsu_ready_o, // FU is ready e.g. not busy
input logic lsu_valid_i, // Input is valid
input logic [TRANS_ID_BITS-1:0] lsu_trans_id_i, // transaction id, needed for WB
input logic [TRANS_ID_BITS-1:0] trans_id_i, // transaction id, needed for WB
output logic [TRANS_ID_BITS-1:0] lsu_trans_id_o, // ID of scoreboard entry at which to write back
output logic [63:0] lsu_result_o,
output logic lsu_valid_o, // transaction id for which the output is the requested one
@ -602,7 +602,7 @@ module lsu #(
vaddr = vaddr_i;
data = operand_b_i;
operator = operator_i;
trans_id = lsu_trans_id_i;
trans_id = trans_id_i;
end
end
@ -620,7 +620,7 @@ module lsu #(
vaddr_q <= vaddr_i;
data_q <= operand_b_i;
operator_q <= operator_i;
trans_id_q <= lsu_trans_id_i;
trans_id_q <= trans_id_i;
end
end
end