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🐛 Fix missing flush in PTW
This commit is contained in:
Florian Zaruba
parent
d59ab86e10
commit
2570aa4bb1
2 changed files with 41 additions and 34 deletions
11
src/mmu.sv
11
src/mmu.sv
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@ -29,6 +29,7 @@ module mmu #(
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(
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input logic clk_i,
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input logic rst_ni,
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input logic flush_i,
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input logic enable_translation_i,
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// IF interface
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input logic fetch_req_i,
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@ -168,7 +169,6 @@ module mmu #(
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(
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( flush_tlb_i ),
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.ptw_active_o ( ptw_active ),
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.walking_instr_o ( walking_instr ),
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.ptw_error_o ( ptw_error ),
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@ -189,7 +189,6 @@ module mmu #(
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.dtlb_access_i ( dtlb_lu_access ),
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.dtlb_miss_i ( ~dtlb_lu_hit ),
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.dtlb_vaddr_i ( lsu_vaddr_i ),
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.*
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);
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@ -251,10 +250,10 @@ module mmu #(
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// ---------
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// watch out for exceptions happening during walking the page table
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if (ptw_active && walking_instr) begin
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// on an error pass through fetch with an error signaled
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fetch_gnt_o = ptw_error;
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ierr_valid_n = ptw_error; // signal valid/error on next cycle
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fetch_ex_n = {INSTR_PAGE_FAULT, {25'b0, update_vaddr}, 1'b1};
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// on an error pass through fetch with an error signaled
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fetch_gnt_o = ptw_error;
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ierr_valid_n = ptw_error; // signal valid/error on next cycle
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fetch_ex_n = {INSTR_PAGE_FAULT, {25'b0, update_vaddr}, 1'b1};
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end
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end
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// the fetch is valid if we either got an error in the previous cycle or the I$ gave us a valid signal.
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64
src/ptw.sv
64
src/ptw.sv
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@ -75,11 +75,11 @@ module ptw #(
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assign pte = pte_t'(data_rdata_i);
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enum logic[1:0] {
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PTW_READY,
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PTW_WAIT_GRANT,
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PTW_PTE_LOOKUP,
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PTW_PROPAGATE_ERROR
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} ptw_state_q, ptw_state_n;
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IDLE,
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WAIT_GRANT,
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PTE_LOOKUP,
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PROPAGATE_ERROR
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} CS, NS;
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// SV39 defines three levels of page tables
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enum logic [1:0] {
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@ -100,7 +100,7 @@ module ptw #(
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// Assignments
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assign update_vaddr_o = vaddr_q;
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assign ptw_active_o = (ptw_state_q != PTW_READY);
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assign ptw_active_o = (CS != IDLE);
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assign walking_instr_o = is_instr_ptw_q;
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// directly output the correct physical address
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assign address_index_o = ptw_pptr_q[11:0];
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@ -154,18 +154,18 @@ module ptw #(
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is_instr_ptw_n = is_instr_ptw_q;
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ptw_lvl_n = ptw_lvl_q;
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ptw_pptr_n = ptw_pptr_q;
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ptw_state_n = ptw_state_q;
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NS = CS;
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global_mapping_n = global_mapping_q;
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// input registers
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tlb_update_asid_n = tlb_update_asid_q;
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vaddr_n = vaddr_q;
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case (ptw_state_q)
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case (CS)
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PTW_READY: begin
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IDLE: begin
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// by default we start with the top-most page table
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ptw_lvl_n = LVL1;
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ptw_lvl_n = LVL1;
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global_mapping_n = 1'b0;
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// if we got an ITLB miss
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if (enable_translation_i & itlb_access_i & itlb_miss_i & ~dtlb_access_i) begin
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@ -173,18 +173,18 @@ module ptw #(
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is_instr_ptw_n = 1'b1;
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tlb_update_asid_n = asid_i;
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vaddr_n = itlb_vaddr_i;
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ptw_state_n = PTW_WAIT_GRANT;
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NS = WAIT_GRANT;
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// we got an DTLB miss
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end else if (enable_translation_i & dtlb_access_i & dtlb_miss_i) begin
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ptw_pptr_n = {satp_ppn_i, dtlb_vaddr_i[38:30], 3'b0};
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is_instr_ptw_n = 1'b0;
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tlb_update_asid_n = asid_i;
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vaddr_n = dtlb_vaddr_i;
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ptw_state_n = PTW_WAIT_GRANT;
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NS = WAIT_GRANT;
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end
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end
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PTW_WAIT_GRANT: begin
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WAIT_GRANT: begin
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// send a request out
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data_req_o = 1'b1;
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@ -195,15 +195,15 @@ module ptw #(
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if (ptw_lvl_q == LVL3)
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ptw_pptr_n = {pte.ppn, vaddr_q[20:12], 3'b0};
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// wait for the grant
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// wait for the WAIT_GRANT
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if (data_gnt_i) begin
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// send the tag valid signal one cycle later
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tag_valid_n = 1'b1;
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ptw_state_n = PTW_PTE_LOOKUP;
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NS = PTE_LOOKUP;
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end
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end
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PTW_PTE_LOOKUP: begin
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PTE_LOOKUP: begin
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// we wait for the valid signal
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if (data_rvalid_i) begin
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// check if the global mapping bit is set
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@ -215,12 +215,12 @@ module ptw #(
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// -------------
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// If pte.v = 0, or if pte.r = 0 and pte.w = 1, stop and raise a page-fault exception.
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if (!pte.v || (!pte.r && pte.w))
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ptw_state_n = PTW_PROPAGATE_ERROR;
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NS = PROPAGATE_ERROR;
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// -----------
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// Valid PTE
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// -----------
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else begin
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ptw_state_n = PTW_READY;
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NS = IDLE;
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// it is a valid PTE
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// if pte.r = 1 or pte.x = 1 it is a valid PTE
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if (pte.r || pte.x) begin
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@ -233,7 +233,7 @@ module ptw #(
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// doesn't put a useless entry into the TLB. The same idea applies
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// to the access flag since we let the access flag be managed by SW.
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if (!pte.x || !pte.a)
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ptw_state_n = PTW_PROPAGATE_ERROR;
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NS = PROPAGATE_ERROR;
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else
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itlb_update_o = 1'b1;
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@ -249,14 +249,14 @@ module ptw #(
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if (pte.a && (pte.r || (pte.x && mxr_i))) begin
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dtlb_update_o = 1'b1;
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end else begin
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ptw_state_n = PTW_PROPAGATE_ERROR;
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NS = PROPAGATE_ERROR;
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end
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// Request is a store: perform some additional checks
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// If the request was a store and the page is not write-able, raise an error
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// the same applies if the dirty flag is not set
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if (lsu_is_store_i && (!pte.w || !pte.d)) begin
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dtlb_update_o = 1'b0;
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ptw_state_n = PTW_PROPAGATE_ERROR;
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NS = PROPAGATE_ERROR;
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end
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end
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// this is a pointer to the next TLB level
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@ -268,30 +268,38 @@ module ptw #(
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if (ptw_lvl_q == LVL2)
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ptw_lvl_n = LVL3;
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ptw_state_n = PTW_WAIT_GRANT;
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NS = WAIT_GRANT;
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if (ptw_lvl_q == LVL3) begin
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// Should already be the last level page table => Error
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ptw_lvl_n = LVL3;
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ptw_state_n = PTW_PROPAGATE_ERROR;
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NS = PROPAGATE_ERROR;
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end
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end
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end
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end
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// we've got a data grant so tell the cache that the tag is valid
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// we've got a data WAIT_GRANT so tell the cache that the tag is valid
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end
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// Propagate error to MMU/LSU
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PTW_PROPAGATE_ERROR: begin
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ptw_state_n = PTW_READY;
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PROPAGATE_ERROR: begin
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NS = IDLE;
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ptw_error_o = 1'b1;
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end
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endcase
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// -------
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// Flush
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// -------
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// check if we are walking a store, if not than go back to IDLE because
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// all other operations are speculative
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if (flush_i && !lsu_is_store_i) begin
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NS = IDLE;
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end
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end
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// sequential process
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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ptw_state_q <= PTW_READY;
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CS <= IDLE;
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is_instr_ptw_q <= 1'b0;
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ptw_lvl_q <= LVL1;
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tag_valid_q <= 1'b0;
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@ -300,7 +308,7 @@ module ptw #(
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ptw_pptr_q <= '{default: 0};
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global_mapping_q <= 1'b0;
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end else begin
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ptw_state_q <= ptw_state_n;
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CS <= NS;
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ptw_pptr_q <= ptw_pptr_n;
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is_instr_ptw_q <= is_instr_ptw_n;
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ptw_lvl_q <= ptw_lvl_n;
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