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https://github.com/openhwgroup/cva6.git
synced 2025-04-24 14:17:16 -04:00
Fix Questa flow
This commit is contained in:
Florian Zaruba
Michael Schaffner
parent
bcc5eb0bde
commit
25dae772b3
4 changed files with 54 additions and 23 deletions
12
Makefile
12
Makefile
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@ -124,27 +124,31 @@ $(library):
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sim: build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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-gblso tmp/riscv-fesvr/build/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
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simc: build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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-gblso tmp/riscv-fesvr/build/libfesvr.so -sv_lib $(library)/ariane_dpi -do " run -all; exit" \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do " do tb/wave/wave_core.do; run -all; exit" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
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$(riscv-asm-tests): build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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-gblso tmp/riscv-fesvr/build/libfesvr.so -sv_lib $(library)/ariane_dpi \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log
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$(riscv-benchmarks): build $(library)/ariane_dpi.so
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
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+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
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-gblso tmp/riscv-fesvr/build/libfesvr.so -sv_lib $(library)/ariane_dpi \
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$(QUESTASIM_FLAGS) \
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-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
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-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
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${top_level}_optimized +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log
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@ -11,7 +11,7 @@ It has configurable size, separate TLBs, a hardware PTW and branch-prediction (b
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## Getting Started
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Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools). Make sure that your `RISCV` environment variable points to your RISC-V installation.
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Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools). Make sure that your `RISCV` environment variable points to your RISC-V installation (see the RISC-V tools and related projects for futher information).
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Checkout the repository and initialize all submodules
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```
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@ -4,6 +4,8 @@
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#include <vpi_user.h>
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#include <svdpi.h>
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#include <stdio.h>
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#include <string.h>
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#include <vector>
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dtm_t* dtm;
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@ -20,22 +22,48 @@ extern "C" int debug_tick
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int debug_resp_bits_data
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)
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{
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bool permissive_on = false;
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if (!dtm) {
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s_vpi_vlog_info info;
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if (!vpi_get_vlog_info(&info))
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abort();
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std::vector<std::string> htif_args;
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// sanitize arguments
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for (int i = 0; i < info.argc; i++) {
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for (int i = 1; i < info.argc; i++) {
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if (strcmp(info.argv[i], "+permissive") == 0) {
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permissive_on = true;
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printf("Found permissive %s\n", info.argv[i]);
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}
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// remove any two double pluses at the beginning (those are target arguments)
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if (info.argv[i][0] == '+' && info.argv[i][1] == '+' && strlen(info.argv[i]) > 3) {
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for (int j = 0; j < strlen(info.argv[i]) - 1; j++) {
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info.argv[i][j] = info.argv[i][j + 2];
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}
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}
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// printf("Argument %d: %s\n", i, info.argv[i]);
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if (!permissive_on) {
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htif_args.push_back(info.argv[i]);
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}
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if (strcmp(info.argv[i], "+permissive-off") == 0) {
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permissive_on = false;
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printf("Found permissive-off %s\n", info.argv[i]);
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}
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}
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dtm = new dtm_t(info.argc, info.argv);
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// convert vector to argc and argv
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int argc = htif_args.size() + 1;
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char * argv[argc];
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argv[0] = (char *) "htif";
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for (unsigned int i = 0; i < htif_args.size(); i++) {
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argv[i+1] = (char *) htif_args[i].c_str();
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}
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dtm = new dtm_t(argc, argv);
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}
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dtm_t::resp resp_bits;
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@ -1,11 +1,11 @@
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add wave -noupdate -group core /ariane_tb/dut/i_ariane/*
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add wave -noupdate -group frontend /ariane_tb/dut/i_ariane/i_frontend/*
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add wave -noupdate -group frontend -group icache /ariane_tb/dut/i_ariane/i_frontend/i_icache/*
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add wave -noupdate -group frontend -group icache /ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_icache/*
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add wave -noupdate -group frontend -group ras /ariane_tb/dut/i_ariane/i_frontend/i_ras/*
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add wave -noupdate -group frontend -group btb /ariane_tb/dut/i_ariane/i_frontend/i_btb/*
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add wave -noupdate -group frontend -group bht /ariane_tb/dut/i_ariane/i_frontend/i_bht/*
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# add wave -noupdate -group frontend -group instr_scan /ariane_tb/dut/i_ariane/i_frontend/*i_instr_scan/*
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add wave -noupdate -group frontend -group instr_scan /ariane_tb/dut/i_ariane/i_frontend/*/i_instr_scan/*
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add wave -noupdate -group frontend -group fetch_fifo /ariane_tb/dut/i_ariane/i_frontend/i_fetch_fifo/*
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add wave -noupdate -group id_stage -group decoder /ariane_tb/dut/i_ariane/id_stage_i/decoder_i/*
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@ -22,7 +22,6 @@ add wave -noupdate -group ex_stage -group alu /ariane_tb/dut/i_ariane/ex_stage_i
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add wave -noupdate -group ex_stage -group mult /ariane_tb/dut/i_ariane/ex_stage_i/i_mult/*
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add wave -noupdate -group ex_stage -group mult -group mul /ariane_tb/dut/i_ariane/ex_stage_i/i_mult/i_mul/*
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add wave -noupdate -group ex_stage -group mult -group div /ariane_tb/dut/i_ariane/ex_stage_i/i_mult/i_div/*
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add wave -noupdate -group ex_stage -group mult -group ff1 /ariane_tb/dut/i_ariane/ex_stage_i/i_mult/i_ff1/*
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add wave -noupdate -group ex_stage -group lsu /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/*
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add wave -noupdate -group ex_stage -group lsu -group lsu_bypass /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/lsu_bypass_i/*
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@ -48,23 +47,23 @@ add wave -noupdate -group csr_file /ariane_tb/dut/i_ariane/csr_regfile_i/*
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add wave -noupdate -group controller /ariane_tb/dut/i_ariane/controller_i/*
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add wave -noupdate -group nbdcache /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/*
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add wave -noupdate -group nbdcache -group miss_handler /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/i_miss_handler/*
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add wave -noupdate -group nbdcache /ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/*
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add wave -noupdate -group nbdcache -group miss_handler /ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/i_miss_handler/*
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add wave -noupdate -group nbdcache -group bypass_arbiter /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/i_miss_handler/i_bypass_arbiter/*
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add wave -noupdate -group nbdcache -group bypass_axi /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/i_miss_handler/i_bypass_axi_adapter/*
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add wave -noupdate -group nbdcache -group bypass_arbiter /ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/i_miss_handler/i_bypass_arbiter/*
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add wave -noupdate -group nbdcache -group bypass_axi /ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/i_miss_handler/i_bypass_axi_adapter/*
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add wave -noupdate -group nbdcache -group miss_axi /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/i_miss_handler/i_miss_axi_adapter/*
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add wave -noupdate -group nbdcache -group lfsr /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/i_miss_handler/i_lfsr/*
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add wave -noupdate -group nbdcache -group miss_axi /ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/i_miss_handler/i_miss_axi_adapter/*
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add wave -noupdate -group nbdcache -group lfsr /ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/i_miss_handler/i_lfsr/*
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add wave -noupdate -group nbdcache -group dirty_ram /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/dirty_sram/*
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add wave -noupdate -group nbdcache -group tag_cmp /ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/i_tag_cmp/*
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add wave -noupdate -group nbdcache -group dirty_ram /ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/valid_dirty_sram/*
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add wave -noupdate -group nbdcache -group tag_cmp /ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/i_tag_cmp/*
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add wave -noupdate -group nbdcache -group ptw {/ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/master_ports[0]/i_cache_ctrl/*}
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add wave -noupdate -group nbdcache -group load {/ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/master_ports[1]/i_cache_ctrl/*}
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add wave -noupdate -group nbdcache -group store {/ariane_tb/dut/i_ariane/ex_stage_i/lsu_i/i_nbdcache/master_ports[2]/i_cache_ctrl/*}
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add wave -noupdate -group nbdcache -group ptw {/ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/master_ports[0]/i_cache_ctrl/*}
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add wave -noupdate -group nbdcache -group load {/ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/master_ports[1]/i_cache_ctrl/*}
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add wave -noupdate -group nbdcache -group store {/ariane_tb/dut/i_ariane/i_std_cache_subsystem/i_nbdcache/master_ports[2]/i_cache_ctrl/*}
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add wave -noupdate -group perf_counters {/ariane_tb/dut/i_ariane/i_perf_counters/*}
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add wave -noupdate -group perf_counters /ariane_tb/dut/i_ariane/i_perf_counters/*
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add wave -noupdate -group dm_top /ariane_tb/dut/i_dm_top/*
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add wave -noupdate -group dm_top -group dm_csrs /ariane_tb/dut/i_dm_top/i_dm_csrs/*
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