github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-06-27 17:00:57 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Indicate dirty in mstatus.FS correctly (#2936)

Browse source 
This commit makes two changes to the commit stage:
- It fixes incorrect parenthesis, causing dirty_fp_state_o not to be set
  on floating point instructions such as fld.
- It adds a condition for dirty_fp_state_o that only asserts the flag
  for floating point instructions that change any FPU registers.

Co-authored-by: Guillaume Chauvon <94678394+Gchauvon@users.noreply.github.com>
This commit is contained in:
Eric Ackermann 2025-05-19 23:06:42 +02:00 • committed by GitHub
parent 6f78ff4d0c
commit 2700d14471
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
2 changed files with 15 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

6
core/commit_stage.sv
View file

@ -113,10 +113,12 @@ module commit_stage
always_comb begin : dirty_fp_state
dirty_fp_state_o = 1'b0;
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
dirty_fp_state_o |= commit_ack_o[i] & ((commit_instr_i[i].fu inside {FPU, FPU_VEC} & CVA6Cfg.FpPresent & ariane_pkg::fd_changes_rd_state(
commit_instr_i[i].op
)) || (CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr(
commit_instr_i[i].op
// Check if we issued a vector floating-point instruction to the accellerator
))) | commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp;
))) | (commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp);
end
end

11
core/include/ariane_pkg.sv
View file

@ -607,6 +607,17 @@ package ariane_pkg;
endcase
endfunction
function automatic logic fd_changes_rd_state(input fu_op op);
unique case (op) inside
FSD, FSW, FSH, FSB, // stores
FCVT_F2I, // conversion to int
FMV_F2X, // move as-is to int
FCLASS: // classification (writes output to integer register)
return 1'b0; // floating-point registers are only read
default: return 1'b1; // other ops - floating-point registers are written as well
endcase
endfunction
function automatic logic is_amo(fu_op op);
case (op) inside
[AMO_LRW : AMO_MINDU]: begin