github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-19 11:54:46 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Define RVFI as cva6 parameter (#1293)

Browse source
This commit is contained in:
JeanRochCoulon 2023-07-19 08:21:39 +02:00 • committed by GitHub
parent edafd8e01d
commit 279ce9fb9b
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
86 changed files with 344 additions and 408 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
Bender.yml
View file

@ -25,7 +25,6 @@ sources:
files:
- core/include/cv64a6_imafdcv_sv39_config_pkg.sv
- core/include/riscv_pkg.sv
- common/local/rvfi/rvfi_pkg.sv
- core/include/ariane_dm_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv39/tlb.sv
@ -37,7 +36,6 @@ sources:
files:
- core/include/cv64a6_imafdc_sv39_config_pkg.sv
- core/include/riscv_pkg.sv
- common/local/rvfi/rvfi_pkg.sv
- core/include/ariane_dm_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv39/tlb.sv
@ -49,7 +47,6 @@ sources:
files:
- core/include/cv32a6_imac_sv0_config_pkg.sv
- core/include/riscv_pkg.sv
- common/local/rvfi/rvfi_pkg.sv
- core/include/ariane_dm_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv32/cva6_tlb_sv32.sv
@ -61,7 +58,6 @@ sources:
files:
- core/include/cv32a6_imac_sv32_config_pkg.sv
- core/include/riscv_pkg.sv
- common/local/rvfi/rvfi_pkg.sv
- core/include/ariane_dm_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv32/cva6_tlb_sv32.sv

2
Makefile
View file

@ -525,7 +525,7 @@ xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchma
verilate_command := $(verilator) verilator_config.vlt \
-f core/Flist.cva6 \
$(filter-out %.vhd, $(ariane_pkg)) \
$(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
$(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(filter-out %_config_pkg.sv, $(src)))) \
+define+$(defines)$(if $(TRACE_FAST),+VM_TRACE)$(if $(TRACE_COMPACT),+VM_TRACE+VM_TRACE_FST) \
corev_apu/tb/common/mock_uart.sv \
+incdir+corev_apu/axi_node \

44
common/local/rvfi/rvfi_pkg.sv
View file

@ -1,44 +0,0 @@
// Copyright 2020 Thales DIS design services SAS
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Original Author: Jean-Roch COULON - Thales
package rvfi_pkg;
localparam NRET = 1;
localparam ILEN = 32;
typedef struct packed {
logic [NRET-1:0] valid;
logic [NRET*64-1:0] order;
logic [NRET*ILEN-1:0] insn;
logic [NRET-1:0] trap;
logic [NRET*riscv::XLEN-1:0] cause;
logic [NRET-1:0] halt;
logic [NRET-1:0] intr;
logic [NRET*2-1:0] mode;
logic [NRET*2-1:0] ixl;
logic [NRET*5-1:0] rs1_addr;
logic [NRET*5-1:0] rs2_addr;
logic [NRET*riscv::XLEN-1:0] rs1_rdata;
logic [NRET*riscv::XLEN-1:0] rs2_rdata;
logic [NRET*5-1:0] rd_addr;
logic [NRET*riscv::XLEN-1:0] rd_wdata;
logic [NRET*riscv::XLEN-1:0] pc_rdata;
logic [NRET*riscv::XLEN-1:0] pc_wdata;
logic [NRET*riscv::VLEN-1:0] mem_addr;
logic [NRET*riscv::PLEN-1:0] mem_paddr;
logic [NRET*(riscv::XLEN/8)-1:0] mem_rmask;
logic [NRET*(riscv::XLEN/8)-1:0] mem_wmask;
logic [NRET*riscv::XLEN-1:0] mem_rdata;
logic [NRET*riscv::XLEN-1:0] mem_wdata;
} rvfi_instr_t;
endpackage

1
config_pkg_generator.py
View file

@ -154,7 +154,6 @@ MapArgsToParameter={
"PerfCounterEn": "CVA6ConfigPerfCounterEn",
"DcacheType": "CVA6ConfigDcacheType",
"MmuPresent": "CVA6ConfigMmuPresent",
"RvfiTrace": "RVFI_PORT",
# Ignored parameters
"ignored": "CVA6ConfigRvfiTrace",
}

1
core/Flist.cva6
View file

@ -57,7 +57,6 @@ ${CVA6_REPO_DIR}/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mv
${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/common/local/rvfi/rvfi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
// Note: depends on fpnew_pkg, above
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv

1
core/Flist.cva6_gate
View file

@ -10,7 +10,6 @@
${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/common/local/rvfi/rvfi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.

7
core/acc_dispatcher.sv
View file

@ -14,6 +14,7 @@
// Description: Functional unit that dispatches CVA6 instructions to accelerators.
module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter type acc_req_t = acc_pkg::accelerator_req_t,
parameter type acc_resp_t = acc_pkg::accelerator_resp_t
) (
@ -31,7 +32,7 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
input logic issue_instr_hs_i,
output logic issue_stall_o,
input fu_data_t fu_data_i,
input scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i,
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
output logic [TRANS_ID_BITS-1:0] acc_trans_id_o,
output xlen_t acc_result_o,
output logic acc_valid_o,
@ -39,7 +40,7 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
// Interface with the execute stage
output logic acc_valid_ex_o, // FU executed
// Interface with the commit stage
input logic [NR_COMMIT_PORTS-1:0] commit_ack_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
input logic commit_st_barrier_i, // A store barrier was commited
// Interface with the load/store unit
input logic acc_no_st_pending_i,
@ -286,7 +287,7 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
// Dirty the V state if we are committing anything related to the vector accelerator
always_comb begin : dirty_v_state
dirty_v_state_o = 1'b0;
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
dirty_v_state_o |= commit_ack_i[i] & (commit_instr_i[i].fu == ACCEL);
end
end

2
core/alu.sv
View file

@ -19,7 +19,7 @@
module alu import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

2
core/amo_buffer.sv
View file

@ -15,7 +15,7 @@
// Furthermore it handles interfacing with the commit stage
module amo_buffer #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

23
core/ariane_regfile.sv
View file

@ -24,10 +24,9 @@
//
module ariane_regfile_lol #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned NR_READ_PORTS = 2,
parameter int unsigned NR_WRITE_PORTS = 2,
parameter bit ZERO_REG_ZERO = 0
)(
// clock and reset
@ -39,9 +38,9 @@ module ariane_regfile_lol #(
input logic [NR_READ_PORTS-1:0][4:0] raddr_i,
output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o,
// write port
input logic [NR_WRITE_PORTS-1:0][4:0] waddr_i,
input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i,
input logic [NR_WRITE_PORTS-1:0] we_i
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
input logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] we_i
);
localparam ADDR_WIDTH = 5;
@ -50,8 +49,8 @@ module ariane_regfile_lol #(
logic [NUM_WORDS-1:ZERO_REG_ZERO] mem_clocks;
logic [DATA_WIDTH-1:0] mem[NUM_WORDS];
logic [NR_WRITE_PORTS-1:0][NUM_WORDS-1:1] waddr_onehot,waddr_onehot_q;
logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_q;
logic [CVA6Cfg.NrCommitPorts-1:0][NUM_WORDS-1:1] waddr_onehot,waddr_onehot_q;
logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_q;
// decode addresses
@ -62,7 +61,7 @@ module ariane_regfile_lol #(
if (~rst_ni) begin
wdata_q <= '0;
end else begin
for (int unsigned i = 0; i < NR_WRITE_PORTS; i++)
for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++)
// enable flipflop will most probably infer clock gating
if (we_i[i]) begin
wdata_q[i] <= wdata_i[i];
@ -73,7 +72,7 @@ module ariane_regfile_lol #(
// WRITE : Write Address Decoder (WAD), combinatorial process
always_comb begin : decode_write_addess
for (int unsigned i = 0; i < NR_WRITE_PORTS; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
for (int unsigned j = 1; j < NUM_WORDS; j++) begin
if (we_i[i] && (waddr_i[i] == j))
waddr_onehot[i][j] = 1'b1;
@ -86,9 +85,9 @@ module ariane_regfile_lol #(
// WRITE : Clock gating (if integrated clock-gating cells are available)
for (genvar x = ZERO_REG_ZERO; x < NUM_WORDS; x++) begin
logic [NR_WRITE_PORTS-1:0] waddr_ored;
logic [CVA6Cfg.NrCommitPorts-1:0] waddr_ored;
for (genvar i = 0; i < NR_WRITE_PORTS; i++)
for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++)
assign waddr_ored[i] = waddr_onehot[i][x];
cluster_clock_gating i_cg (
@ -111,7 +110,7 @@ module ariane_regfile_lol #(
if (ZERO_REG_ZERO)
mem[0] = '0;
for (int unsigned i = 0; i < NR_WRITE_PORTS; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
for (int unsigned k = ZERO_REG_ZERO; k < NUM_WORDS; k++) begin
if (mem_clocks[k] && waddr_onehot_q[i][k])
mem[k] = wdata_q[i];

15
core/ariane_regfile_ff.sv
View file

@ -23,10 +23,9 @@
//
module ariane_regfile #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned NR_READ_PORTS = 2,
parameter int unsigned NR_WRITE_PORTS = 2,
parameter bit ZERO_REG_ZERO = 0
)(
// clock and reset
@ -38,20 +37,20 @@ module ariane_regfile #(
input logic [NR_READ_PORTS-1:0][4:0] raddr_i,
output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o,
// write port
input logic [NR_WRITE_PORTS-1:0][4:0] waddr_i,
input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i,
input logic [NR_WRITE_PORTS-1:0] we_i
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
input logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] we_i
);
localparam ADDR_WIDTH = 5;
localparam NUM_WORDS = 2**ADDR_WIDTH;
logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] mem;
logic [NR_WRITE_PORTS-1:0][NUM_WORDS-1:0] we_dec;
logic [CVA6Cfg.NrCommitPorts-1:0][NUM_WORDS-1:0] we_dec;
always_comb begin : we_decoder
for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin
for (int unsigned i = 0; i < NUM_WORDS; i++) begin
if (waddr_i[j] == i)
we_dec[j][i] = we_i[j];
@ -66,7 +65,7 @@ module ariane_regfile #(
if (~rst_ni) begin
mem <= '{default: '0};
end else begin
for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin
for (int unsigned i = 0; i < NUM_WORDS; i++) begin
if (we_dec[j][i]) begin
mem[i] <= wdata_i[j];

25
core/ariane_regfile_fpga.sv
View file

@ -26,10 +26,9 @@
//
module ariane_regfile_fpga #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned NR_READ_PORTS = 2,
parameter int unsigned NR_WRITE_PORTS = 2,
parameter bit ZERO_REG_ZERO = 0
)(
// clock and reset
@ -41,25 +40,25 @@ module ariane_regfile_fpga #(
input logic [NR_READ_PORTS-1:0][4:0] raddr_i,
output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o,
// write port
input logic [NR_WRITE_PORTS-1:0][4:0] waddr_i,
input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i,
input logic [NR_WRITE_PORTS-1:0] we_i
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
input logic [CVA6Cfg.NrCommitPorts-1:0][DATA_WIDTH-1:0] wdata_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] we_i
);
localparam ADDR_WIDTH = 5;
localparam NUM_WORDS = 2**ADDR_WIDTH;
localparam LOG_NR_WRITE_PORTS = NR_WRITE_PORTS == 1 ? 1 : $clog2(NR_WRITE_PORTS);
localparam LOG_NR_WRITE_PORTS = CVA6Cfg.NrCommitPorts == 1 ? 1 : $clog2(CVA6Cfg.NrCommitPorts);
// Distributed RAM usually supports one write port per block - duplicate for each write port.
logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] mem [NR_WRITE_PORTS];
logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] mem [CVA6Cfg.NrCommitPorts];
logic [NR_WRITE_PORTS-1:0][NUM_WORDS-1:0] we_dec;
logic [CVA6Cfg.NrCommitPorts-1:0][NUM_WORDS-1:0] we_dec;
logic [NUM_WORDS-1:0][LOG_NR_WRITE_PORTS-1:0] mem_block_sel;
logic [NUM_WORDS-1:0][LOG_NR_WRITE_PORTS-1:0] mem_block_sel_q;
// write adress decoder (for block selector)
always_comb begin
for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) begin
for (int unsigned i = 0; i < NUM_WORDS; i++) begin
if (waddr_i[j] == i) begin
we_dec[j][i] = we_i[j];
@ -77,7 +76,7 @@ module ariane_regfile_fpga #(
always_comb begin
mem_block_sel = mem_block_sel_q;
for (int i = 0; i<NUM_WORDS; i++) begin
for (int j = 0; j<NR_WRITE_PORTS; j++) begin
for (int j = 0; j<CVA6Cfg.NrCommitPorts; j++) begin
if (we_dec[j][i] == 1'b1) begin
mem_block_sel[i] = LOG_NR_WRITE_PORTS'(j);
end
@ -95,8 +94,8 @@ module ariane_regfile_fpga #(
end
// distributed RAM blocks
logic [NR_READ_PORTS-1:0] [DATA_WIDTH-1:0] mem_read [NR_WRITE_PORTS];
for (genvar j=0; j<NR_WRITE_PORTS; j++) begin : regfile_ram_block
logic [NR_READ_PORTS-1:0] [DATA_WIDTH-1:0] mem_read [CVA6Cfg.NrCommitPorts];
for (genvar j=0; j<CVA6Cfg.NrCommitPorts; j++) begin : regfile_ram_block
always_ff @(posedge clk_i) begin
if (we_i[j] && ~waddr_i[j] != 0) begin
mem[j][waddr_i[j]] <= wdata_i[j];
@ -118,7 +117,7 @@ module ariane_regfile_fpga #(
// random initialization of the memory to suppress assert warnings on Questa.
initial
begin
for(int i = 0; i < NR_WRITE_PORTS; i++) begin
for(int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
for(int j = 0; j < NUM_WORDS; j++) begin
mem[i][j] = $random();
end

2
core/axi_shim.sv
View file

@ -20,7 +20,7 @@
module axi_shim #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned AxiUserWidth = 64, // data width in dwords, this is also the maximum burst length, must be >=2
parameter int unsigned AxiNumWords = 4, // data width in dwords, this is also the maximum burst length, must be >=2
parameter int unsigned AxiAddrWidth = 0,

2
core/branch_unit.sv
View file

@ -13,7 +13,7 @@
// Description: Branch target calculation and comparison
module branch_unit #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,

2
core/cache_subsystem/amo_alu.sv
View file

@ -12,7 +12,7 @@
// Date: 15.09.2018
// Description: Combinatorial AMO unit
module amo_alu #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
// AMO interface
input ariane_pkg::amo_t amo_op_i,

2
core/cache_subsystem/axi_adapter.sv
View file

@ -17,7 +17,7 @@
//import std_cache_pkg::*;
module axi_adapter #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned DATA_WIDTH = 256,
parameter logic CRITICAL_WORD_FIRST = 0, // the AXI subsystem needs to support wrapping reads for this feature
parameter int unsigned CACHELINE_BYTE_OFFSET = 8,

2
core/cache_subsystem/cache_ctrl.sv
View file

@ -19,7 +19,7 @@
module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig // contains cacheable regions
) (
input logic clk_i, // Clock

2
core/cache_subsystem/cva6_icache.sv
View file

@ -26,7 +26,7 @@
module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0, // ID to be used for read transactions
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
) (

6
core/cache_subsystem/cva6_icache_axi_wrapper.sv
View file

@ -14,7 +14,7 @@
//
module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned AxiAddrWidth = 0,
parameter int unsigned AxiDataWidth = 0,
@ -101,7 +101,7 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #(
// -------
cva6_icache #(
// use ID 0 for icache reads
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.RdTxId ( 0 ),
.ArianeCfg ( ArianeCfg )
) i_cva6_icache (
@ -125,7 +125,7 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #(
// AXI shim
// --------
axi_shim #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.AxiNumWords ( AxiNumWords ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),

6
core/cache_subsystem/miss_handler.sv
View file

@ -17,7 +17,7 @@
// --------------
module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned NR_PORTS = 3,
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
@ -570,7 +570,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
assign bypass_addr = bypass_adapter_req.addr;
axi_adapter #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.DATA_WIDTH ( 64 ),
.CACHELINE_BYTE_OFFSET ( DCACHE_BYTE_OFFSET ),
.AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),
@ -608,7 +608,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
assign miss_addr = req_fsm_miss_addr;
axi_adapter #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.DATA_WIDTH ( DCACHE_LINE_WIDTH ),
.CACHELINE_BYTE_OFFSET ( DCACHE_BYTE_OFFSET ),
.AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),

6
core/cache_subsystem/std_cache_subsystem.sv
View file

@ -16,7 +16,7 @@
module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned AxiAddrWidth = 0,
parameter int unsigned AxiDataWidth = 0,
@ -68,7 +68,7 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
axi_rsp_t axi_resp_data;
cva6_icache_axi_wrapper #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
@ -95,7 +95,7 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
// Port 1: Load Unit
// Port 2: Store Unit
std_nbdcache #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),

8
core/cache_subsystem/std_nbdcache.sv
View file

@ -14,7 +14,7 @@
module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned AXI_ADDR_WIDTH = 0,
parameter int unsigned AXI_DATA_WIDTH = 0,
@ -94,7 +94,7 @@ import std_cache_pkg::*;
generate
for (genvar i = 0; i < 3; i++) begin : master_ports
cache_ctrl #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg )
) i_cache_ctrl (
.bypass_i ( ~enable_i ),
@ -134,7 +134,7 @@ import std_cache_pkg::*;
// Miss Handling Unit
// ------------------
miss_handler #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.NR_PORTS ( 3 ),
.AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
@ -248,7 +248,7 @@ import std_cache_pkg::*;
// Tag Comparison and memory arbitration
// ------------------------------------------------
tag_cmp #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.NR_PORTS ( 4 ),
.ADDR_WIDTH ( DCACHE_INDEX_WIDTH ),
.DCACHE_SET_ASSOC ( DCACHE_SET_ASSOC )

2
core/cache_subsystem/tag_cmp.sv
View file

@ -16,7 +16,7 @@
// checks for hit or miss on cache
//
module tag_cmp #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned NR_PORTS = 3,
parameter int unsigned ADDR_WIDTH = 64,
parameter type l_data_t = std_cache_pkg::cache_line_t,

4
core/cache_subsystem/wt_axi_adapter.sv
View file

@ -15,7 +15,7 @@
module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned ReqFifoDepth = 2,
parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX,
parameter int unsigned AxiAddrWidth = 0,
@ -606,7 +606,7 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
///////////////////////////////////////////////////////
axi_shim #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.AxiNumWords ( AxiNumWords ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),

10
core/cache_subsystem/wt_cache_subsystem.sv
View file

@ -20,7 +20,7 @@
module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned NumPorts = 3,
parameter int unsigned AxiAddrWidth = 0,
@ -85,7 +85,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
cva6_icache #(
// use ID 0 for icache reads
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.RdTxId ( 0 ),
.ArianeCfg ( ArianeCfg )
) i_cva6_icache (
@ -111,7 +111,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
// they have equal prio and are RR arbited
// Port 2 is write only and goes into the merging write buffer
wt_dcache #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.AxiDataWidth ( AxiDataWidth ),
// use ID 1 for dcache reads and amos. note that the writebuffer
// uses all IDs up to DCACHE_MAX_TX-1 for write transactions.
@ -146,7 +146,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
`ifdef PITON_ARIANE
wt_l15_adapter #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.SwapEndianess ( ArianeCfg.SwapEndianess )
) i_adapter (
.clk_i ( clk_i ),
@ -166,7 +166,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
);
`else
wt_axi_adapter #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
.AxiIdWidth ( AxiIdWidth ),

10
core/cache_subsystem/wt_dcache.sv
View file

@ -14,7 +14,7 @@
module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned AxiDataWidth = 0,
parameter int unsigned NumPorts = 3, // number of miss ports
// ID to be used for read and AMO transactions.
@ -113,7 +113,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
///////////////////////////////////////////////////////
wt_dcache_missunit #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.AxiCompliant ( ArianeCfg.AxiCompliant ),
.AmoTxId ( RdAmoTxId ),
.NumPorts ( NumPorts ),
@ -176,7 +176,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
assign rd_prio[k] = 1'b1;
wt_dcache_ctrl #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.RdTxId ( RdAmoTxId ),
.ArianeCfg ( ArianeCfg )
) i_wt_dcache_ctrl (
@ -222,7 +222,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
assign rd_prio[2] = 1'b0;
wt_dcache_wbuffer #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg )
) i_wt_dcache_wbuffer (
.clk_i ( clk_i ),
@ -280,7 +280,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
///////////////////////////////////////////////////////
wt_dcache_mem #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.AxiCompliant ( ArianeCfg.AxiCompliant ),
.AxiDataWidth ( AxiDataWidth ),
.NumPorts ( NumPorts )

2
core/cache_subsystem/wt_dcache_ctrl.sv
View file

@ -14,7 +14,7 @@
module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1, // ID to use for read transactions
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
) (

2
core/cache_subsystem/wt_dcache_mem.sv
View file

@ -27,7 +27,7 @@
module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter
parameter int unsigned AxiDataWidth = 0,
parameter int unsigned NumPorts = 3

2
core/cache_subsystem/wt_dcache_missunit.sv
View file

@ -15,7 +15,7 @@
module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter
parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs
parameter int unsigned NumPorts = 3, // number of miss ports

2
core/cache_subsystem/wt_dcache_wbuffer.sv
View file

@ -50,7 +50,7 @@
module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
) (
input logic clk_i, // Clock

2
core/cache_subsystem/wt_l15_adapter.sv
View file

@ -50,7 +50,7 @@
module wt_l15_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter bit SwapEndianess = 1
) (
input logic clk_i,

21
core/commit_stage.sv
View file

@ -14,8 +14,7 @@
module commit_stage import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned NR_COMMIT_PORTS = 2
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
)(
input logic clk_i,
input logic rst_ni,
@ -25,13 +24,13 @@ module commit_stage import ariane_pkg::*; #(
output logic dirty_fp_state_o, // mark the F state as dirty
input logic single_step_i, // we are in single step debug mode
// from scoreboard
input scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i, // the instruction we want to commit
output logic [NR_COMMIT_PORTS-1:0] commit_ack_o, // acknowledge that we are indeed committing
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // the instruction we want to commit
output logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_o, // acknowledge that we are indeed committing
// to register file
output logic [NR_COMMIT_PORTS-1:0][4:0] waddr_o, // register file write address
output logic [NR_COMMIT_PORTS-1:0][riscv::XLEN-1:0] wdata_o, // register file write data
output logic [NR_COMMIT_PORTS-1:0] we_gpr_o, // register file write enable
output logic [NR_COMMIT_PORTS-1:0] we_fpr_o, // floating point register enable
output logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_o, // register file write address
output logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_o, // register file write data
output logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_o, // register file write enable
output logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_o, // floating point register enable
// Atomic memory operations
input amo_resp_t amo_resp_i, // result of AMO operation
// to CSR file and PC Gen (because on certain CSR instructions we'll need to flush the whole pipeline)
@ -69,7 +68,7 @@ module commit_stage import ariane_pkg::*; #(
// .probe9(1'b0) // input wire [0:0] probe9
// );
for (genvar i = 0; i < NR_COMMIT_PORTS; i++) begin : gen_waddr
for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_waddr
assign waddr_o[i] = commit_instr_i[i].rd[4:0];
end
@ -77,7 +76,7 @@ module commit_stage import ariane_pkg::*; #(
// Dirty the FP state if we are committing anything related to the FPU
always_comb begin : dirty_fp_state
dirty_fp_state_o = 1'b0;
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
dirty_fp_state_o |= commit_ack_o[i] & (commit_instr_i[i].fu inside {FPU, FPU_VEC} || is_rd_fpr(commit_instr_i[i].op));
// Check if we issued a vector floating-point instruction to the accellerator
dirty_fp_state_o |= commit_instr_i[i].fu == ACCEL && commit_instr_i[i].vfp;
@ -208,7 +207,7 @@ module commit_stage import ariane_pkg::*; #(
end
end
if (NR_COMMIT_PORTS > 1) begin
if (CVA6Cfg.NrCommitPorts > 1) begin
commit_ack_o[1] = 1'b0;
we_gpr_o[1] = 1'b0;

2
core/compressed_decoder.sv
View file

@ -20,7 +20,7 @@
module compressed_decoder #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic [31:0] instr_i,
output logic [31:0] instr_o,

2
core/controller.sv
View file

@ -14,7 +14,7 @@
module controller import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,

2
core/csr_buffer.sv
View file

@ -15,7 +15,7 @@
module csr_buffer import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

9
core/csr_regfile.sv
View file

@ -14,10 +14,9 @@
module csr_regfile import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter logic [63:0] DmBaseAddress = 64'h0, // debug module base address
parameter int AsidWidth = 1,
parameter int unsigned NrCommitPorts = 2,
parameter int unsigned NrPMPEntries = 8,
parameter int unsigned MHPMCounterNum = 6
) (
@ -28,8 +27,8 @@ module csr_regfile import ariane_pkg::*; #(
output logic flush_o,
output logic halt_csr_o, // halt requested
// commit acknowledge
input scoreboard_entry_t [NrCommitPorts-1:0] commit_instr_i, // the instruction we want to commit
input logic [NrCommitPorts-1:0] commit_ack_i, // Commit acknowledged a instruction -> increase instret CSR
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // the instruction we want to commit
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // Commit acknowledged a instruction -> increase instret CSR
// Core and Cluster ID
input logic[riscv::VLEN-1:0] boot_addr_i, // Address from which to start booting, mtvec is set to the same address
input logic[riscv::XLEN-1:0] hart_id_i, // Hart id in a multicore environment (reflected in a CSR)
@ -488,7 +487,7 @@ module csr_regfile import ariane_pkg::*; #(
instret_d = instret_q;
if (!debug_mode_q) begin
// increase instruction retired counter
for (int i = 0; i < NrCommitPorts; i++) begin
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
if (commit_ack_i[i] && !ex_i.valid && !mcountinhibit_q[2]) instret++;
end
instret_d = instret;

89
core/cva6.sv
View file

@ -14,6 +14,36 @@
module cva6 import ariane_pkg::*; #(
// Pipeline
parameter int unsigned NrCommitPorts = cva6_config_pkg::CVA6ConfigNrCommitPorts,
// RVFI
parameter int unsigned IsRVFI = cva6_config_pkg::CVA6ConfigRvfiTrace,
parameter type rvfi_instr_t = struct packed {
logic [ariane_pkg::NRET-1:0] valid;
logic [ariane_pkg::NRET*64-1:0] order;
logic [ariane_pkg::NRET*ariane_pkg::ILEN-1:0] insn;
logic [ariane_pkg::NRET-1:0] trap;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] cause;
logic [ariane_pkg::NRET-1:0] halt;
logic [ariane_pkg::NRET-1:0] intr;
logic [ariane_pkg::NRET*2-1:0] mode;
logic [ariane_pkg::NRET*2-1:0] ixl;
logic [ariane_pkg::NRET*5-1:0] rs1_addr;
logic [ariane_pkg::NRET*5-1:0] rs2_addr;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs1_rdata;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs2_rdata;
logic [ariane_pkg::NRET*5-1:0] rd_addr;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] rd_wdata;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_rdata;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_wdata;
logic [ariane_pkg::NRET*riscv::VLEN-1:0] mem_addr;
logic [ariane_pkg::NRET*riscv::PLEN-1:0] mem_paddr;
logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask;
logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_rdata;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_wdata;
},
//
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig,
parameter type cvxif_req_t = cvxif_pkg::cvxif_req_t,
parameter type cvxif_resp_t = cvxif_pkg::cvxif_resp_t,
@ -31,7 +61,6 @@ module cva6 import ariane_pkg::*; #(
// Core ID, Cluster ID and boot address are considered more or less static
input logic [riscv::VLEN-1:0] boot_addr_i, // reset boot address
input logic [riscv::XLEN-1:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR)
// Interrupt inputs
input logic [1:0] irq_i, // level sensitive IR lines, mip & sip (async)
input logic ipi_i, // inter-processor interrupts (async)
@ -40,7 +69,7 @@ module cva6 import ariane_pkg::*; #(
input logic debug_req_i, // debug request (async)
// RISC-V formal interface port (`rvfi`):
// Can be left open when formal tracing is not needed.
output ariane_pkg::rvfi_port_t rvfi_o,
output rvfi_instr_t [NrCommitPorts-1:0] rvfi_o,
output cvxif_req_t cvxif_req_o,
input cvxif_resp_t cvxif_resp_i,
// L15 (memory side)
@ -51,7 +80,10 @@ module cva6 import ariane_pkg::*; #(
input axi_rsp_t axi_resp_i
);
localparam ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty;
localparam ariane_pkg::cva6_cfg_t CVA6Cfg = {
int'(NrCommitPorts),
int'(IsRVFI)
};
// ------------------------------------------
// Global Signals
@ -62,7 +94,7 @@ module cva6 import ariane_pkg::*; #(
bp_resolve_t resolved_branch;
logic [riscv::VLEN-1:0] pc_commit;
logic eret;
logic [NR_COMMIT_PORTS-1:0] commit_ack;
logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack;
localparam NumPorts = 3;
cvxif_pkg::cvxif_req_t cvxif_req;
@ -175,14 +207,14 @@ module cva6 import ariane_pkg::*; #(
// --------------
// ID <-> COMMIT
// --------------
scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_id_commit;
scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_id_commit;
// --------------
// COMMIT <-> ID
// --------------
logic [NR_COMMIT_PORTS-1:0][4:0] waddr_commit_id;
logic [NR_COMMIT_PORTS-1:0][riscv::XLEN-1:0] wdata_commit_id;
logic [NR_COMMIT_PORTS-1:0] we_gpr_commit_id;
logic [NR_COMMIT_PORTS-1:0] we_fpr_commit_id;
logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_commit_id;
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_commit_id;
logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_commit_id;
logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_commit_id;
// --------------
// CSR <-> *
// --------------
@ -283,7 +315,7 @@ module cva6 import ariane_pkg::*; #(
// Frontend
// --------------
frontend #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg )
) i_frontend (
.flush_i ( flush_ctrl_if ), // not entirely correct
@ -310,7 +342,7 @@ module cva6 import ariane_pkg::*; #(
// ID
// ---------
id_stage #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) id_stage_i (
.clk_i,
.rst_ni,
@ -368,10 +400,9 @@ module cva6 import ariane_pkg::*; #(
// Issue
// ---------
issue_stage #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.NR_ENTRIES ( NR_SB_ENTRIES ),
.NR_WB_PORTS ( NR_WB_PORTS ),
.NR_COMMIT_PORTS ( NR_COMMIT_PORTS )
.NR_WB_PORTS ( NR_WB_PORTS )
) issue_stage_i (
.clk_i,
.rst_ni,
@ -445,7 +476,7 @@ module cva6 import ariane_pkg::*; #(
// EX
// ---------
ex_stage #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ASID_WIDTH ( ASID_WIDTH ),
.ArianeCfg ( ArianeCfg )
) ex_stage_i (
@ -562,8 +593,7 @@ module cva6 import ariane_pkg::*; #(
assign no_st_pending_commit = no_st_pending_ex & dcache_commit_wbuffer_empty;
commit_stage #(
.cva6_cfg ( cva6_cfg ),
.NR_COMMIT_PORTS ( NR_COMMIT_PORTS )
.CVA6Cfg ( CVA6Cfg )
) commit_stage_i (
.clk_i,
.rst_ni,
@ -602,10 +632,9 @@ module cva6 import ariane_pkg::*; #(
// CSR
// ---------
csr_regfile #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.AsidWidth ( ASID_WIDTH ),
.DmBaseAddress ( ArianeCfg.DmBaseAddress ),
.NrCommitPorts ( NR_COMMIT_PORTS ),
.NrPMPEntries ( ArianeCfg.NrPMPEntries ),
.MHPMCounterNum ( MHPMCounterNum )
) csr_regfile_i (
@ -672,7 +701,7 @@ module cva6 import ariane_pkg::*; #(
// ------------------------
if (PERF_COUNTER_EN) begin: gen_perf_counter
perf_counters #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.NumPorts ( NumPorts )
) perf_counters_i (
.clk_i ( clk_i ),
@ -708,7 +737,7 @@ module cva6 import ariane_pkg::*; #(
// Controller
// ------------
controller #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) controller_i (
// flush ports
.set_pc_commit_o ( set_pc_ctrl_pcgen ),
@ -746,7 +775,7 @@ module cva6 import ariane_pkg::*; #(
if (DCACHE_TYPE == int'(cva6_config_pkg::WT)) begin
// this is a cache subsystem that is compatible with OpenPiton
wt_cache_subsystem #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.NumPorts ( NumPorts ),
.AxiAddrWidth ( AxiAddrWidth ),
@ -799,7 +828,7 @@ module cva6 import ariane_pkg::*; #(
// note: this only works with one cacheable region
// not as important since this cache subsystem is about to be
// deprecated
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
@ -921,10 +950,10 @@ module cva6 import ariane_pkg::*; #(
logic piton_pc_vld;
logic [riscv::VLEN-1:0] piton_pc;
logic [NR_COMMIT_PORTS-1:0][riscv::VLEN-1:0] pc_data;
logic [NR_COMMIT_PORTS-1:0] pc_pop, pc_empty;
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::VLEN-1:0] pc_data;
logic [CVA6Cfg.NrCommitPorts-1:0] pc_pop, pc_empty;
for (genvar i = 0; i < NR_COMMIT_PORTS; i++) begin : gen_pc_fifo
for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_pc_fifo
fifo_v3 #(
.DATA_WIDTH(64),
.DEPTH(PC_QUEUE_DEPTH))
@ -944,7 +973,7 @@ module cva6 import ariane_pkg::*; #(
end
rr_arb_tree #(
.NumIn(NR_COMMIT_PORTS),
.NumIn(CVA6Cfg.NrCommitPorts),
.DataWidth(64))
i_rr_arb_tree (
.clk_i ( clk_i ),
@ -1028,7 +1057,7 @@ module cva6 import ariane_pkg::*; #(
default: ; // Do nothing
endcase
end
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin
$fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]);
end else if (commit_ack[i] && commit_instr_id_commit[i].ex.valid) begin
@ -1053,9 +1082,9 @@ module cva6 import ariane_pkg::*; #(
`endif // VERILATOR
//pragma translate_on
if (ariane_pkg::RVFI) begin
if (CVA6Cfg.IsRVFI) begin
always_comb begin
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
logic exception, mem_exception;
exception = commit_instr_id_commit[i].valid && ex_commit.valid;
mem_exception = exception &&

2
core/cvxif_fu.sv
View file

@ -11,7 +11,7 @@
module cvxif_fu import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,

2
core/decoder.sv
View file

@ -20,7 +20,7 @@
//
module decoder import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic debug_req_i, // external debug request
input logic [riscv::VLEN-1:0] pc_i, // PC from IF

14
core/ex_stage.sv
View file

@ -15,7 +15,7 @@
module ex_stage import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned ASID_WIDTH = 1,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
) (
@ -169,7 +169,7 @@ module ex_stage import ariane_pkg::*; #(
assign alu_data = (alu_valid_i | branch_valid_i) ? fu_data_i : '0;
alu #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) alu_i (
.clk_i,
.rst_ni,
@ -182,7 +182,7 @@ module ex_stage import ariane_pkg::*; #(
// we don't silence the branch unit as this is already critical and we do
// not want to add another layer of logic
branch_unit #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) branch_unit_i (
.clk_i,
.rst_ni,
@ -203,7 +203,7 @@ module ex_stage import ariane_pkg::*; #(
// 3. CSR (sequential)
csr_buffer #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) csr_buffer_i (
.clk_i,
.rst_ni,
@ -246,7 +246,7 @@ module ex_stage import ariane_pkg::*; #(
assign mult_data = mult_valid_i ? fu_data_i : '0;
mult #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) i_mult (
.clk_i,
.rst_ni,
@ -300,7 +300,7 @@ module ex_stage import ariane_pkg::*; #(
assign lsu_data = lsu_valid_i ? fu_data_i : '0;
load_store_unit #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ASID_WIDTH ( ASID_WIDTH ),
.ArianeCfg ( ArianeCfg )
) lsu_i (
@ -357,7 +357,7 @@ module ex_stage import ariane_pkg::*; #(
fu_data_t cvxif_data;
assign cvxif_data = x_valid_i ? fu_data_i : '0;
cvxif_fu #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) cvxif_fu_i (
.clk_i,
.rst_ni,

2
core/fpu_wrap.sv
View file

@ -14,7 +14,7 @@
module fpu_wrap import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,

2
core/frontend/bht.sv
View file

@ -19,7 +19,7 @@
// branch history table - 2 bit saturation counter
module bht #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned NR_ENTRIES = 1024
)(
input logic clk_i,

2
core/frontend/btb.sv
View file

@ -26,7 +26,7 @@
//
// branch target buffer
module btb #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int NR_ENTRIES = 8
)(
input logic clk_i, // Clock

4
core/frontend/frontend.sv
View file

@ -16,7 +16,7 @@
// change request from the back-end and does branch prediction.
module frontend import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
) (
input logic clk_i, // Clock
@ -112,7 +112,7 @@ module frontend import ariane_pkg::*; #(
logic serving_unaligned;
// Re-align instructions
instr_realign #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) i_instr_realign (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),

2
core/frontend/instr_queue.sv
View file

@ -44,7 +44,7 @@
// can not be pushed at once.
module instr_queue import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,

2
core/frontend/instr_scan.sv
View file

@ -16,7 +16,7 @@
// Instruction Scanner
// ------------------------------
module instr_scan #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic [31:0] instr_i, // expect aligned instruction, compressed or not
output logic rvi_return_o,

2
core/frontend/ras.sv
View file

@ -15,7 +15,7 @@
// return address stack
module ras #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned DEPTH = 2
)(
input logic clk_i,

6
core/id_stage.sv
View file

@ -14,7 +14,7 @@
// issue and read operands.
module id_stage #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,
@ -62,7 +62,7 @@ module id_stage #(
// 1. Check if they are compressed and expand in case they are
// ---------------------------------------------------------
compressed_decoder #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) compressed_decoder_i (
.instr_i ( fetch_entry_i.instruction ),
.instr_o ( instruction ),
@ -78,7 +78,7 @@ module id_stage #(
// 2. Decode and emit instruction to issue stage
// ---------------------------------------------------------
decoder #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) decoder_i (
.debug_req_i,
.irq_ctrl_i,

11
core/include/ariane_pkg.sv
View file

@ -31,12 +31,17 @@ package ariane_pkg;
// This is the new user config interface system. If you need to parameterize something
// within Ariane add a field here and assign a default value to the config. Please make
// sure to add a propper parameter check to the `check_cfg` function.
localparam int unsigned ILEN = 32;
localparam int unsigned NRET = 1;
typedef struct packed {
int unsigned dummy;
int unsigned NrCommitPorts;
int unsigned IsRVFI;
} cva6_cfg_t;
localparam cva6_cfg_t cva6_cfg_empty = {
32'b0
unsigned'(0),
unsigned'(0)
};
localparam NrMaxRules = 16;
@ -141,7 +146,6 @@ package ariane_pkg;
// to uniquely identify the entry in the scoreboard
localparam ASID_WIDTH = (riscv::XLEN == 64) ? 16 : 1;
localparam BITS_SATURATION_COUNTER = 2;
localparam NR_COMMIT_PORTS = cva6_config_pkg::CVA6ConfigNrCommitPorts;
localparam ENABLE_RENAME = cva6_config_pkg::CVA6ConfigRenameEn;
@ -685,7 +689,6 @@ package ariane_pkg;
// ---------------
localparam RVFI = cva6_config_pkg::CVA6ConfigRvfiTrace;
typedef rvfi_pkg::rvfi_instr_t [NR_COMMIT_PORTS-1:0] rvfi_port_t;
typedef struct packed {
logic [riscv::VLEN-1:0] pc; // PC of instruction

9
core/include/cv32a60x_config_pkg.sv
View file

@ -74,13 +74,6 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
localparam CVA6ConfigRvfiTrace = 1;
endpackage

9
core/include/cv32a6_embedded_config_pkg.sv
View file

@ -73,13 +73,6 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 0;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
localparam CVA6ConfigRvfiTrace = 1;
endpackage

9
core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
View file

@ -74,13 +74,6 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`undef RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
localparam CVA6ConfigRvfiTrace = 1;
endpackage

9
core/include/cv32a6_imac_sv0_config_pkg.sv
View file

@ -74,13 +74,6 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
localparam CVA6ConfigRvfiTrace = 1;
endpackage

9
core/include/cv32a6_imac_sv32_config_pkg.sv
View file

@ -74,13 +74,6 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
localparam CVA6ConfigRvfiTrace = 1;
endpackage

9
core/include/cv32a6_imafc_sv32_config_pkg.sv
View file

@ -74,13 +74,6 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
localparam CVA6ConfigRvfiTrace = 1;
endpackage

9
core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file

@ -74,13 +74,6 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
localparam CVA6ConfigRvfiTrace = 1;
endpackage

9
core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
View file

@ -74,13 +74,6 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`undef RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
localparam CVA6ConfigRvfiTrace = 1;
endpackage

9
core/include/cv64a6_imafdcv_sv39_config_pkg.sv
View file

@ -74,13 +74,6 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
localparam CVA6ConfigRvfiTrace = 1;
endpackage

2
core/instr_realign.sv
View file

@ -21,7 +21,7 @@
module instr_realign import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,

37
core/issue_read_operands.sv
View file

@ -15,8 +15,7 @@
module issue_read_operands import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned NR_COMMIT_PORTS = 2
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
)(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
@ -70,10 +69,10 @@ module issue_read_operands import ariane_pkg::*; #(
input logic cvxif_ready_i,
output logic [31:0] cvxif_off_instr_o,
// commit port
input logic [NR_COMMIT_PORTS-1:0][4:0] waddr_i,
input logic [NR_COMMIT_PORTS-1:0][riscv::XLEN-1:0] wdata_i,
input logic [NR_COMMIT_PORTS-1:0] we_gpr_i,
input logic [NR_COMMIT_PORTS-1:0] we_fpr_i,
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i,
output logic stall_issue_o // stall signal, we do not want to fetch any more entries
// committing instruction instruction
@ -370,7 +369,7 @@ module issue_read_operands import ariane_pkg::*; #(
end
// or check that the target destination register will be written in this cycle by the
// commit stage
for (int unsigned i = 0; i < NR_COMMIT_PORTS; i++)
for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++)
if (is_rd_fpr(issue_instr_i.op) ? (we_fpr_i[i] && waddr_i[i] == issue_instr_i.rd[4:0])
: (we_gpr_i[i] && waddr_i[i] == issue_instr_i.rd[4:0])) begin
issue_ack_o = 1'b1;
@ -403,22 +402,21 @@ module issue_read_operands import ariane_pkg::*; #(
logic [NR_RGPR_PORTS-1:0][4:0] raddr_pack;
// pack signals
logic [NR_COMMIT_PORTS-1:0][4:0] waddr_pack;
logic [NR_COMMIT_PORTS-1:0][riscv::XLEN-1:0] wdata_pack;
logic [NR_COMMIT_PORTS-1:0] we_pack;
logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_pack;
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_pack;
logic [CVA6Cfg.NrCommitPorts-1:0] we_pack;
assign raddr_pack = NR_RGPR_PORTS == 3 ? {issue_instr_i.result[4:0], issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]}
: {issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]};
for (genvar i = 0; i < NR_COMMIT_PORTS; i++) begin : gen_write_back_port
for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_write_back_port
assign waddr_pack[i] = waddr_i[i];
assign wdata_pack[i] = wdata_i[i];
assign we_pack[i] = we_gpr_i[i];
end
if (ariane_pkg::FPGA_EN) begin : gen_fpga_regfile
ariane_regfile_fpga #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.DATA_WIDTH ( riscv::XLEN ),
.NR_READ_PORTS ( NR_RGPR_PORTS ),
.NR_WRITE_PORTS ( NR_COMMIT_PORTS ),
.ZERO_REG_ZERO ( 1 )
) i_ariane_regfile_fpga (
.test_en_i ( 1'b0 ),
@ -431,10 +429,9 @@ module issue_read_operands import ariane_pkg::*; #(
);
end else begin : gen_asic_regfile
ariane_regfile #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.DATA_WIDTH ( riscv::XLEN ),
.NR_READ_PORTS ( NR_RGPR_PORTS ),
.NR_WRITE_PORTS ( NR_COMMIT_PORTS ),
.ZERO_REG_ZERO ( 1 )
) i_ariane_regfile (
.test_en_i ( 1'b0 ),
@ -454,20 +451,19 @@ module issue_read_operands import ariane_pkg::*; #(
// pack signals
logic [2:0][4:0] fp_raddr_pack;
logic [NR_COMMIT_PORTS-1:0][riscv::XLEN-1:0] fp_wdata_pack;
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] fp_wdata_pack;
generate
if (FP_PRESENT) begin : float_regfile_gen
assign fp_raddr_pack = {issue_instr_i.result[4:0], issue_instr_i.rs2[4:0], issue_instr_i.rs1[4:0]};
for (genvar i = 0; i < NR_COMMIT_PORTS; i++) begin : gen_fp_wdata_pack
for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_fp_wdata_pack
assign fp_wdata_pack[i] = {wdata_i[i][FLEN-1:0]};
end
if (ariane_pkg::FPGA_EN) begin : gen_fpga_fp_regfile
ariane_regfile_fpga #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.DATA_WIDTH ( FLEN ),
.NR_READ_PORTS ( 3 ),
.NR_WRITE_PORTS ( NR_COMMIT_PORTS ),
.ZERO_REG_ZERO ( 0 )
) i_ariane_fp_regfile_fpga (
.test_en_i ( 1'b0 ),
@ -480,10 +476,9 @@ module issue_read_operands import ariane_pkg::*; #(
);
end else begin : gen_asic_fp_regfile
ariane_regfile #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.DATA_WIDTH ( FLEN ),
.NR_READ_PORTS ( 3 ),
.NR_WRITE_PORTS ( NR_COMMIT_PORTS ),
.ZERO_REG_ZERO ( 0 )
) i_ariane_fp_regfile (
.test_en_i ( 1'b0 ),

27
core/issue_stage.sv
View file

@ -15,10 +15,9 @@
module issue_stage import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned NR_ENTRIES = 8,
parameter int unsigned NR_WB_PORTS = 4,
parameter int unsigned NR_COMMIT_PORTS = 2
parameter int unsigned NR_WB_PORTS = 4
)(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
@ -77,13 +76,13 @@ module issue_stage import ariane_pkg::*; #(
input logic x_we_i,
// commit port
input logic [NR_COMMIT_PORTS-1:0][4:0] waddr_i,
input logic [NR_COMMIT_PORTS-1:0][riscv::XLEN-1:0] wdata_i,
input logic [NR_COMMIT_PORTS-1:0] we_gpr_i,
input logic [NR_COMMIT_PORTS-1:0] we_fpr_i,
input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i,
input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i,
output scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_o,
input logic [NR_COMMIT_PORTS-1:0] commit_ack_i,
output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o,
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
output logic stall_issue_o, // Used in Performance Counters
@ -132,7 +131,7 @@ module issue_stage import ariane_pkg::*; #(
// 1. Re-name
// ---------------------------------------------------------
re_name #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) i_re_name (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
@ -150,10 +149,9 @@ module issue_stage import ariane_pkg::*; #(
// 2. Manage instructions in a scoreboard
// ---------------------------------------------------------
scoreboard #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.NR_ENTRIES (NR_ENTRIES ),
.NR_WB_PORTS(NR_WB_PORTS),
.NR_COMMIT_PORTS(NR_COMMIT_PORTS)
.NR_WB_PORTS(NR_WB_PORTS)
) i_scoreboard (
.sb_full_o ( sb_full_o ),
.unresolved_branch_i ( 1'b0 ),
@ -193,8 +191,7 @@ module issue_stage import ariane_pkg::*; #(
// 3. Issue instruction and read operand, also commit
// ---------------------------------------------------------
issue_read_operands #(
.cva6_cfg ( cva6_cfg ),
.NR_COMMIT_PORTS ( NR_COMMIT_PORTS )
.CVA6Cfg ( CVA6Cfg )
)i_issue_read_operands (
.flush_i ( flush_unissued_instr_i ),
.issue_instr_i ( issue_instr_sb_iro ),

12
core/load_store_unit.sv
View file

@ -14,7 +14,7 @@
module load_store_unit import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned ASID_WIDTH = 1,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
)(
@ -140,7 +140,7 @@ module load_store_unit import ariane_pkg::*; #(
// -------------------
if (MMU_PRESENT && (riscv::XLEN == 64)) begin : gen_mmu_sv39
mmu #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.INSTR_TLB_ENTRIES ( ariane_pkg::INSTR_TLB_ENTRIES ),
.DATA_TLB_ENTRIES ( ariane_pkg::DATA_TLB_ENTRIES ),
.ASID_WIDTH ( ASID_WIDTH ),
@ -170,7 +170,7 @@ module load_store_unit import ariane_pkg::*; #(
);
end else if (MMU_PRESENT && (riscv::XLEN == 32)) begin : gen_mmu_sv32
cva6_mmu_sv32 #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.INSTR_TLB_ENTRIES ( ariane_pkg::INSTR_TLB_ENTRIES ),
.DATA_TLB_ENTRIES ( ariane_pkg::DATA_TLB_ENTRIES ),
.ASID_WIDTH ( ASID_WIDTH ),
@ -246,7 +246,7 @@ module load_store_unit import ariane_pkg::*; #(
// Store Unit
// ------------------
store_unit #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) i_store_unit (
.clk_i,
.rst_ni,
@ -287,7 +287,7 @@ module load_store_unit import ariane_pkg::*; #(
// Load Unit
// ------------------
load_unit #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg )
) i_load_unit (
.valid_i ( ld_valid_i ),
@ -477,7 +477,7 @@ module load_store_unit import ariane_pkg::*; #(
assign lsu_req_i = {lsu_valid_i, vaddr_i, overflow, fu_data_i.operand_b, be_i, fu_data_i.fu, fu_data_i.operation, fu_data_i.trans_id};
lsu_bypass #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) lsu_bypass_i (
.lsu_req_i ( lsu_req_i ),
.lsu_req_valid_i ( lsu_valid_i ),

2
core/load_unit.sv
View file

@ -14,7 +14,7 @@
// Description: Load Unit, takes care of all load requests
module load_unit import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
) (
input logic clk_i, // Clock

2
core/lsu_bypass.sv
View file

@ -24,7 +24,7 @@
// two element FIFO. This is necessary as we only know very late in the cycle whether the load/store will succeed (address check,
// TLB hit mainly). So we better unconditionally allow another request to arrive and store this request in case we need to.
module lsu_bypass import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,

10
core/mmu_sv32/cva6_mmu_sv32.sv
View file

@ -27,7 +27,7 @@
// =========================================================================== //
module cva6_mmu_sv32 import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned INSTR_TLB_ENTRIES = 2,
parameter int unsigned DATA_TLB_ENTRIES = 2,
parameter int unsigned ASID_WIDTH = 1,
@ -112,7 +112,7 @@ module cva6_mmu_sv32 import ariane_pkg::*; #(
cva6_tlb_sv32 #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.TLB_ENTRIES ( INSTR_TLB_ENTRIES ),
.ASID_WIDTH ( ASID_WIDTH )
) i_itlb (
@ -134,7 +134,7 @@ module cva6_mmu_sv32 import ariane_pkg::*; #(
);
cva6_tlb_sv32 #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.TLB_ENTRIES ( DATA_TLB_ENTRIES ),
.ASID_WIDTH ( ASID_WIDTH )
) i_dtlb (
@ -156,7 +156,7 @@ module cva6_mmu_sv32 import ariane_pkg::*; #(
);
cva6_shared_tlb_sv32 #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.SHARED_TLB_DEPTH ( 64 ),
.SHARED_TLB_WAYS ( 2 ),
.ASID_WIDTH ( ASID_WIDTH )
@ -197,7 +197,7 @@ module cva6_mmu_sv32 import ariane_pkg::*; #(
);
cva6_ptw_sv32 #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ASID_WIDTH ( ASID_WIDTH ),
.ArianeCfg ( ArianeCfg )
) i_ptw (

4
core/mmu_sv32/cva6_ptw_sv32.sv
View file

@ -27,7 +27,7 @@
/* verilator lint_off WIDTH */
module cva6_ptw_sv32 import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int ASID_WIDTH = 1,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
) (
@ -144,7 +144,7 @@ module cva6_ptw_sv32 import ariane_pkg::*; #(
assign bad_paddr_o = ptw_access_exception_o ? ptw_pptr_q : 'b0;
pmp #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.PLEN ( riscv::PLEN ),
.PMP_LEN ( riscv::PLEN - 2 ),
.NR_ENTRIES ( ArianeCfg.NrPMPEntries )

2
core/mmu_sv32/cva6_shared_tlb_sv32.sv
View file

@ -18,7 +18,7 @@
/* verilator lint_off WIDTH */
module cva6_shared_tlb_sv32 import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int SHARED_TLB_DEPTH = 64,
parameter int SHARED_TLB_WAYS = 2,
parameter int ASID_WIDTH = 1,

2
core/mmu_sv32/cva6_tlb_sv32.sv
View file

@ -25,7 +25,7 @@
// =========================================================================== //
module cva6_tlb_sv32 import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned TLB_ENTRIES = 4,
parameter int unsigned ASID_WIDTH = 1
)(

12
core/mmu_sv39/mmu.sv
View file

@ -16,7 +16,7 @@
module mmu import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned INSTR_TLB_ENTRIES = 4,
parameter int unsigned DATA_TLB_ENTRIES = 4,
parameter int unsigned ASID_WIDTH = 1,
@ -97,7 +97,7 @@ module mmu import ariane_pkg::*; #(
tlb #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.TLB_ENTRIES ( INSTR_TLB_ENTRIES ),
.ASID_WIDTH ( ASID_WIDTH )
) i_itlb (
@ -120,7 +120,7 @@ module mmu import ariane_pkg::*; #(
);
tlb #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.TLB_ENTRIES ( DATA_TLB_ENTRIES ),
.ASID_WIDTH ( ASID_WIDTH )
) i_dtlb (
@ -144,7 +144,7 @@ module mmu import ariane_pkg::*; #(
ptw #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.ASID_WIDTH ( ASID_WIDTH ),
.ArianeCfg ( ArianeCfg )
) i_ptw (
@ -275,7 +275,7 @@ module mmu import ariane_pkg::*; #(
// Instruction fetch
pmp #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.PLEN ( riscv::PLEN ),
.PMP_LEN ( riscv::PLEN - 2 ),
.NR_ENTRIES ( ArianeCfg.NrPMPEntries )
@ -424,7 +424,7 @@ module mmu import ariane_pkg::*; #(
// Load/store PMP check
pmp #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.PLEN ( riscv::PLEN ),
.PMP_LEN ( riscv::PLEN - 2 ),
.NR_ENTRIES ( ArianeCfg.NrPMPEntries )

4
core/mmu_sv39/ptw.sv
View file

@ -16,7 +16,7 @@
/* verilator lint_off WIDTH */
module ptw import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int ASID_WIDTH = 1,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
) (
@ -139,7 +139,7 @@ module ptw import ariane_pkg::*; #(
assign bad_paddr_o = ptw_access_exception_o ? ptw_pptr_q : 'b0;
pmp #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.PLEN ( riscv::PLEN ),
.PMP_LEN ( riscv::PLEN - 2 ),
.NR_ENTRIES ( ArianeCfg.NrPMPEntries )

2
core/mmu_sv39/tlb.sv
View file

@ -16,7 +16,7 @@
module tlb import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned TLB_ENTRIES = 4,
parameter int unsigned ASID_WIDTH = 1
)(

6
core/mult.sv
View file

@ -1,7 +1,7 @@
module mult import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,
@ -44,7 +44,7 @@ module mult import ariane_pkg::*; #(
// Multiplication
// ---------------------
multiplier #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) i_multiplier (
.clk_i,
.rst_ni,
@ -110,7 +110,7 @@ module mult import ariane_pkg::*; #(
// Serial Divider
// ---------------------
serdiv #(
.cva6_cfg ( cva6_cfg ),
.CVA6Cfg ( CVA6Cfg ),
.WIDTH ( riscv::XLEN )
) i_div (
.clk_i ( clk_i ),

2
core/multiplier.sv
View file

@ -16,7 +16,7 @@
module multiplier import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,

20
core/perf_counters.sv
View file

@ -14,7 +14,7 @@
module perf_counters import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned NumPorts = 3 // number of miss ports
) (
input logic clk_i,
@ -26,8 +26,8 @@ module perf_counters import ariane_pkg::*; #(
input riscv::xlen_t data_i, // data to write
output riscv::xlen_t data_o, // data to read
// from commit stage
input scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_i, // the instruction we want to commit
input logic [NR_COMMIT_PORTS-1:0] commit_ack_i, // acknowledge that we are indeed committing
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // the instruction we want to commit
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // acknowledge that we are indeed committing
// from L1 caches
input logic l1_icache_miss_i,
input logic l1_dcache_miss_i,
@ -74,25 +74,25 @@ module perf_counters import ariane_pkg::*; #(
5'b00010 : events[i] = l1_dcache_miss_i;//L1 D-Cache misses
5'b00011 : events[i] = itlb_miss_i;//ITLB misses
5'b00100 : events[i] = dtlb_miss_i;//DTLB misses
5'b00101 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == LOAD;//Load accesses
5'b00110 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == STORE;//Store accesses
5'b00101 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == LOAD;//Load accesses
5'b00110 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == STORE;//Store accesses
5'b00111 : events[i] = ex_i.valid;//Exceptions
5'b01000 : events[i] = eret_i;//Exception handler returns
5'b01001 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == CTRL_FLOW;//Branch instructions
5'b01001 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == CTRL_FLOW;//Branch instructions
5'b01010 : events[i] = resolved_branch_i.valid && resolved_branch_i.is_mispredict;//Branch mispredicts
5'b01011 : events[i] = branch_exceptions_i.valid;//Branch exceptions
// The standard software calling convention uses register x1 to hold the return address on a call
// the unconditional jump is decoded as ADD op
5'b01100 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == CTRL_FLOW && (commit_instr_i[j].op == ADD || commit_instr_i[j].op == JALR) && (commit_instr_i[j].rd == 'd1 || commit_instr_i[j].rd == 'd5);//Call
5'b01101 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].op == JALR && commit_instr_i[j].rd == 'd0;//Return
5'b01100 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == CTRL_FLOW && (commit_instr_i[j].op == ADD || commit_instr_i[j].op == JALR) && (commit_instr_i[j].rd == 'd1 || commit_instr_i[j].rd == 'd5);//Call
5'b01101 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].op == JALR && commit_instr_i[j].rd == 'd0;//Return
5'b01110 : events[i] = sb_full_i;//MSB Full
5'b01111 : events[i] = if_empty_i;//Instruction fetch Empty
5'b10000 : events[i] = l1_icache_access_i.req;//L1 I-Cache accesses
5'b10001 : events[i] = l1_dcache_access_i[0].data_req || l1_dcache_access_i[1].data_req || l1_dcache_access_i[2].data_req;//L1 D-Cache accesses
5'b10010 : events[i] = (l1_dcache_miss_i && miss_vld_bits_i[0] == 8'hFF) || (l1_dcache_miss_i && miss_vld_bits_i[1] == 8'hFF) || (l1_dcache_miss_i && miss_vld_bits_i[2] == 8'hFF);//eviction
5'b10011 : events[i] = i_tlb_flush_i;//I-TLB flush
5'b10100 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == ALU || commit_instr_i[j].fu == MULT;//Integer instructions
5'b10101 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == FPU || commit_instr_i[j].fu == FPU_VEC;//Floating Point Instructions
5'b10100 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == ALU || commit_instr_i[j].fu == MULT;//Integer instructions
5'b10101 : for (int unsigned j = 0; j < CVA6Cfg.NrCommitPorts; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == FPU || commit_instr_i[j].fu == FPU_VEC;//Floating Point Instructions
5'b10110 : events[i] = stall_issue_i;//Pipeline bubbles
default: events[i] = 0;
endcase

2
core/pmp/src/pmp.sv
View file

@ -13,7 +13,7 @@
// Description: purely combinatorial PMP unit (with extraction for more complex configs such as NAPOT)
module pmp #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned PLEN = 34, // rv64: 56
parameter int unsigned PMP_LEN = 32, // rv64: 54
parameter int unsigned NR_ENTRIES = 4

2
core/pmp/src/pmp_entry.sv
View file

@ -13,7 +13,7 @@
// Description: single PMP entry
module pmp_entry #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned PLEN = 56,
parameter int unsigned PMP_LEN = 54
) (

2
core/re_name.sv
View file

@ -10,7 +10,7 @@
// Description: Re-name registers
module re_name import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

25
core/scoreboard.sv
View file

@ -13,10 +13,9 @@
// Description: Scoreboard - keeps track of all decoded, issued and committed instructions
module scoreboard #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned NR_ENTRIES = 8, // must be a power of 2
parameter int unsigned NR_WB_PORTS = 1,
parameter int unsigned NR_COMMIT_PORTS = 2
parameter int unsigned NR_WB_PORTS = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
@ -42,8 +41,8 @@ module scoreboard #(
output logic rs3_valid_o,
// advertise instruction to commit stage, if commit_ack_i is asserted advance the commit pointer
output ariane_pkg::scoreboard_entry_t [NR_COMMIT_PORTS-1:0] commit_instr_o,
input logic [NR_COMMIT_PORTS-1:0] commit_ack_i,
output ariane_pkg::scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o,
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
// instruction to put on top of scoreboard e.g.: top pointer
// we can always put this instruction to the top unless we signal with asserted full_o
@ -85,8 +84,8 @@ module scoreboard #(
logic issue_full, issue_en;
logic [BITS_ENTRIES:0] issue_cnt_n, issue_cnt_q;
logic [BITS_ENTRIES-1:0] issue_pointer_n, issue_pointer_q;
logic [NR_COMMIT_PORTS-1:0][BITS_ENTRIES-1:0] commit_pointer_n, commit_pointer_q;
logic [$clog2(NR_COMMIT_PORTS):0] num_commit;
logic [CVA6Cfg.NrCommitPorts-1:0][BITS_ENTRIES-1:0] commit_pointer_n, commit_pointer_q;
logic [$clog2(CVA6Cfg.NrCommitPorts):0] num_commit;
// the issue queue is full don't issue any new instructions
// works since aligned to power of 2
@ -97,7 +96,7 @@ module scoreboard #(
ariane_pkg::scoreboard_entry_t decoded_instr;
always_comb begin
decoded_instr = decoded_instr_i;
if (ariane_pkg::RVFI) begin
if (CVA6Cfg.IsRVFI) begin
decoded_instr.rs1_rdata = rs1_forwarding_i;
decoded_instr.rs2_rdata = rs2_forwarding_i;
decoded_instr.lsu_addr = '0;
@ -109,7 +108,7 @@ module scoreboard #(
// output commit instruction directly
always_comb begin : commit_ports
for (int unsigned i = 0; i < NR_COMMIT_PORTS; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
commit_instr_o[i] = mem_q[commit_pointer_q[i]].sbe;
commit_instr_o[i].trans_id = commit_pointer_q[i];
end
@ -156,7 +155,7 @@ module scoreboard #(
// ------------
// Write Back
// ------------
if (ariane_pkg::RVFI) begin
if (CVA6Cfg.IsRVFI) begin
if (lsu_rmask_i != 0) begin
mem_n[lsu_addr_trans_id_i].sbe.lsu_addr = lsu_addr_i;
mem_n[lsu_addr_trans_id_i].sbe.lsu_rmask = lsu_rmask_i;
@ -191,7 +190,7 @@ module scoreboard #(
// Commit Port
// ------------
// we've got an acknowledge from commit
for (logic [NR_COMMIT_PORTS-1:0] i = 0; i < NR_COMMIT_PORTS; i++) begin
for (logic [CVA6Cfg.NrCommitPorts-1:0] i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
if (commit_ack_i[i]) begin
// this instruction is no longer in issue e.g.: it is considered finished
mem_n[commit_pointer_q[i]].issued = 1'b0;
@ -213,14 +212,14 @@ module scoreboard #(
end
// FIFO counter updates
assign num_commit = (NR_COMMIT_PORTS == 2) ? commit_ack_i[1] + commit_ack_i[0] : commit_ack_i[0];
assign num_commit = (CVA6Cfg.NrCommitPorts == 2) ? commit_ack_i[1] + commit_ack_i[0] : commit_ack_i[0];
assign issue_cnt_n = (flush_i) ? '0 : issue_cnt_q - num_commit + issue_en;
assign commit_pointer_n[0] = (flush_i) ? '0 : commit_pointer_q[0] + num_commit;
assign issue_pointer_n = (flush_i) ? '0 : issue_pointer_q + issue_en;
// precompute offsets for commit slots
for (genvar k=1; k < NR_COMMIT_PORTS; k++) begin : gen_cnt_incr
for (genvar k=1; k < CVA6Cfg.NrCommitPorts; k++) begin : gen_cnt_incr
assign commit_pointer_n[k] = (flush_i) ? '0 : commit_pointer_n[0] + unsigned'(k);
end

2
core/serdiv.sv
View file

@ -16,7 +16,7 @@
module serdiv import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter WIDTH = 64,
parameter STABLE_HANDSHAKE = 0 // Guarantee a stable in_rdy_o during the input handshake. Keep it at 0 in CVA6
) (

2
core/store_buffer.sv
View file

@ -15,7 +15,7 @@
module store_buffer import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

6
core/store_unit.sv
View file

@ -14,7 +14,7 @@
module store_unit import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t cva6_cfg = ariane_pkg::cva6_cfg_empty
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
@ -216,7 +216,7 @@ module store_unit import ariane_pkg::*; #(
// Store Queue
// ---------------
store_buffer #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) store_buffer_i (
.clk_i,
.rst_ni,
@ -245,7 +245,7 @@ module store_unit import ariane_pkg::*; #(
);
amo_buffer #(
.cva6_cfg ( cva6_cfg )
.CVA6Cfg ( CVA6Cfg )
) i_amo_buffer (
.clk_i,
.rst_ni,

13
corev_apu/fpga/src/ariane_xilinx.sv
View file

@ -12,6 +12,7 @@
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
module ariane_xilinx (
// WARNING: Do not define input parameters. This causes the FPGA build to fail.
`ifdef GENESYSII
input logic sys_clk_p ,
input logic sys_clk_n ,
@ -152,6 +153,15 @@ module ariane_xilinx (
input logic rx ,
output logic tx
);
// cva6 configuration
// Pipeline
localparam int unsigned NrCommitPorts = cva6_config_pkg::CVA6ConfigNrCommitPorts;
// RVFI
localparam int unsigned IsRVFI = 0;
localparam type rvfi_instr_t = logic;
// 24 MByte in 8 byte words
localparam NumWords = (24 * 1024 * 1024) / 8;
localparam NBSlave = 2; // debug, ariane
@ -697,6 +707,9 @@ ariane_axi::req_t axi_ariane_req;
ariane_axi::resp_t axi_ariane_resp;
ariane #(
.NrCommitPorts ( NrCommitPorts ),
.IsRVFI ( IsRVFI ),
.rvfi_instr_t ( rvfi_instr_t ),
.ArianeCfg ( ariane_soc::ArianeSocCfg )
) i_ariane (
.clk_i ( clk ),

24
corev_apu/include/traced_instr_pkg.sv
View file

@ -1,24 +0,0 @@
// See LICENSE.Berkeley for license details.
// Author: Abraham Gonzalez, UC Berkeley
// Date: 24.02.2020
// Description: Traced Instruction and Port (using in Rocket Chip based systems)
package traced_instr_pkg;
typedef struct packed {
logic clock;
logic reset;
logic valid;
logic [63:0] iaddr;
logic [31:0] insn;
logic [1:0] priv;
logic exception;
logic interrupt;
logic [63:0] cause;
logic [63:0] tval;
} traced_instr_t;
typedef traced_instr_t [ariane_pkg::NR_COMMIT_PORTS-1:0] trace_port_t;
endpackage

18
corev_apu/src/ariane.sv
View file

@ -14,6 +14,12 @@
module ariane import ariane_pkg::*; #(
// Pipeline
parameter int unsigned NrCommitPorts = 0,
// RVFI
parameter int unsigned IsRVFI = 0,
parameter type rvfi_instr_t = logic,
//
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig,
parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth,
parameter int unsigned AxiDataWidth = ariane_axi::DataWidth,
@ -36,11 +42,9 @@ module ariane import ariane_pkg::*; #(
// Timer facilities
input logic time_irq_i, // timer interrupt in (async)
input logic debug_req_i, // debug request (async)
`ifdef RVFI_PORT
// RISC-V formal interface port (`rvfi`):
// Can be left open when formal tracing is not needed.
output rvfi_port_t rvfi_o,
`endif
output rvfi_instr_t [NrCommitPorts-1:0] rvfi_o,
`ifdef PITON_ARIANE
// L15 (memory side)
output wt_cache_pkg::l15_req_t l15_req_o,
@ -56,6 +60,10 @@ module ariane import ariane_pkg::*; #(
cvxif_pkg::cvxif_resp_t cvxif_resp;
cva6 #(
.NrCommitPorts ( NrCommitPorts ),
.IsRVFI ( IsRVFI ),
.rvfi_instr_t ( rvfi_instr_t ),
//
.ArianeCfg ( ArianeCfg ),
.AxiAddrWidth ( AxiAddrWidth ),
.AxiDataWidth ( AxiDataWidth ),
@ -74,11 +82,7 @@ module ariane import ariane_pkg::*; #(
.ipi_i ( ipi_i ),
.time_irq_i ( time_irq_i ),
.debug_req_i ( debug_req_i ),
`ifdef RVFI_PORT
.rvfi_o ( rvfi_o ),
`else
.rvfi_o ( ),
`endif
.cvxif_req_o ( cvxif_req ),
.cvxif_resp_i ( cvxif_resp ),
`ifdef PITON_ARIANE

42
corev_apu/tb/ariane_testharness.sv
View file

@ -16,6 +16,36 @@
`include "axi/assign.svh"
module ariane_testharness #(
// Pipeline
parameter int unsigned NrCommitPorts = cva6_config_pkg::CVA6ConfigNrCommitPorts,
// RVFI
parameter int unsigned IsRVFI = cva6_config_pkg::CVA6ConfigRvfiTrace,
parameter type rvfi_instr_t = struct packed {
logic [ariane_pkg::NRET-1:0] valid;
logic [ariane_pkg::NRET*64-1:0] order;
logic [ariane_pkg::NRET*ariane_pkg::ILEN-1:0] insn;
logic [ariane_pkg::NRET-1:0] trap;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] cause;
logic [ariane_pkg::NRET-1:0] halt;
logic [ariane_pkg::NRET-1:0] intr;
logic [ariane_pkg::NRET*2-1:0] mode;
logic [ariane_pkg::NRET*2-1:0] ixl;
logic [ariane_pkg::NRET*5-1:0] rs1_addr;
logic [ariane_pkg::NRET*5-1:0] rs2_addr;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs1_rdata;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs2_rdata;
logic [ariane_pkg::NRET*5-1:0] rd_addr;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] rd_wdata;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_rdata;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_wdata;
logic [ariane_pkg::NRET*riscv::VLEN-1:0] mem_addr;
logic [ariane_pkg::NRET*riscv::PLEN-1:0] mem_paddr;
logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask;
logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_rdata;
logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_wdata;
},
//
parameter int unsigned AXI_USER_WIDTH = ariane_pkg::AXI_USER_WIDTH,
parameter int unsigned AXI_USER_EN = ariane_pkg::AXI_USER_EN,
parameter int unsigned AXI_ADDRESS_WIDTH = 64,
@ -604,10 +634,13 @@ module ariane_testharness #(
// ---------------
ariane_axi::req_t axi_ariane_req;
ariane_axi::resp_t axi_ariane_resp;
ariane_pkg::rvfi_port_t rvfi;
rvfi_instr_t [NrCommitPorts-1:0] rvfi;
ariane #(
.ArianeCfg ( ariane_soc::ArianeSocCfg )
.NrCommitPorts ( NrCommitPorts ),
.IsRVFI ( IsRVFI ),
.rvfi_instr_t ( rvfi_instr_t ),
.ArianeCfg ( ariane_soc::ArianeSocCfg )
) i_ariane (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
@ -616,9 +649,7 @@ module ariane_testharness #(
.irq_i ( irqs ),
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),
`ifdef RVFI_PORT
.rvfi_o ( rvfi ),
`endif
// Disable Debug when simulating with Spike
`ifdef SPIKE_TANDEM
.debug_req_i ( 1'b0 ),
@ -650,6 +681,9 @@ module ariane_testharness #(
end
rvfi_tracer #(
.NrCommitPorts(NrCommitPorts),
.rvfi_instr_t(rvfi_instr_t),
//
.HART_ID(hart_id),
.DEBUG_START(0),
.DEBUG_STOP(0)

10
corev_apu/tb/rvfi_tracer.sv
View file

@ -8,14 +8,18 @@
// Original Author: Jean-Roch COULON - Thales
module rvfi_tracer #(
// Pipeline
parameter int unsigned NrCommitPorts = 0,
// RVFI
parameter type rvfi_instr_t = logic,
//
parameter logic [7:0] HART_ID = '0,
parameter int unsigned DEBUG_START = 0,
parameter int unsigned NR_COMMIT_PORTS = 2,
parameter int unsigned DEBUG_STOP = 0
)(
input logic clk_i,
input logic rst_ni,
input rvfi_pkg::rvfi_instr_t[NR_COMMIT_PORTS-1:0] rvfi_i,
input rvfi_instr_t[NrCommitPorts-1:0] rvfi_i,
output logic[31:0] end_of_test_o
);
@ -44,7 +48,7 @@ module rvfi_tracer #(
assign end_of_test_o = end_of_test_d;
always_ff @(posedge clk_i) begin
end_of_test_q = (rst_ni && (end_of_test_d[0] == 1'b1)) ? end_of_test_d : 0;
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
for (int i = 0; i < NrCommitPorts; i++) begin
pc64 = {{riscv::XLEN-riscv::VLEN{rvfi_i[i].pc_rdata[riscv::VLEN-1]}}, rvfi_i[i].pc_rdata};
// print the instruction information if the instruction is valid or a trap is taken
if (rvfi_i[i].valid) begin