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Preliminary instantiation to get run synthesis

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Florian Zaruba 2017-04-13 15:28:09 +02:00
parent fe992dbbb9
commit 28c86ce521
8 changed files with 299 additions and 35 deletions
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64
ariane.sv
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@ -46,6 +46,70 @@ module ariane
);
logic rst_ni;
logic flush_i;
logic [31:0] instruction_i;
logic instruction_valid_i;
logic ready_o;
alu_op operator_o;
logic [63:0] operand_a_o;
logic [63:0] operand_b_o;
logic alu_ready_i;
logic alu_valid_o;
logic lsu_ready_i;
logic lsu_valid_o;
logic mult_ready_i;
logic mult_valid_o;
logic [4:0] waddr_a_i;
logic [63:0] wdata_a_i;
logic we_a_i;
id_stage id_stage_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.test_en_i ( test_en_i ),
.flush_i ( flush_i ),
.instruction_i ( instruction_i ),
.instruction_valid_i ( instruction_valid_i ),
.ready_o ( ready_o ),
.operator_o ( operator_o ),
.operand_a_o ( operand_a_o ),
.operand_b_o ( operand_b_o ),
.alu_ready_i ( alu_ready_i ),
.alu_valid_o ( alu_valid_o ),
.lsu_ready_i ( lsu_ready_i ),
.lsu_valid_o ( lsu_valid_o ),
.mult_ready_i ( mult_ready_i ),
.mult_valid_o ( mult_valid_o ),
.waddr_a_i ( waddr_a_i ),
.wdata_a_i ( wdata_a_i ),
.we_a_i ( we_a_i )
);
logic [63:0] alu_result;
logic comparison_result_o;
logic lsu_ready_o;
logic lsu_valid_i;
logic mult_ready_o;
logic mult_valid_i;
ex_stage ex_stage_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.operator_i ( operator_o ),
.operand_a_i ( operand_a_o ),
.operand_b_i ( operand_b_o ),
.alu_result_o ( alu_result ),
.comparison_result_o ( comparison_result_o ),
.alu_ready_o ( alu_ready_i ),
.alu_valid_i ( alu_valid_o ),
.lsu_ready_o ( lsu_ready_o ),
.lsu_valid_i ( lsu_valid_i ),
.mult_ready_o ( mult_ready_o ),
.mult_valid_i ( mult_valid_i )
);
endmodule // ariane

47
ex_stage.sv Normal file
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@ -0,0 +1,47 @@
import ariane_pkg::*;
module ex_stage (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input alu_op operator_i,
input logic [63:0] operand_a_i,
input logic [63:0] operand_b_i,
output logic [63:0] alu_result_o,
output logic comparison_result_o,
// ALU 1
output logic alu_ready_o, // FU is ready
input logic alu_valid_i, // Output is valid
// LSU
output logic lsu_ready_o, // FU is ready
input logic lsu_valid_i, // Output is valid
// MULT
output logic mult_ready_o, // FU is ready
input logic mult_valid_i // Output is valid
);
alu alu_i (
.operator_i ( operator_i ),
.operand_a_i ( operand_a_i ),
.operand_b_i ( operand_b_i ),
.multdiv_operand_a_i ( ),
.multdiv_operand_b_i ( ),
.multdiv_en_i ( ),
.adder_result_o ( ),
.adder_result_ext_o ( ),
.result_o ( alu_result_o ),
.comparison_result_o ( comparison_result_o ),
.is_equal_result_o ( )
);
assign alu_ready_o = 1'b1;
// Multiplication
// Load-Store Unit
// pass through
endmodule

108
id_stage.sv Normal file
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@ -0,0 +1,108 @@
import ariane_pkg::*;
module id_stage (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_en_i, // Test Enable
input logic flush_i,
// to IF
input logic [31:0] instruction_i,
input logic instruction_valid_i,
output logic ready_o, // id is ready
output alu_op operator_o,
output logic [63:0] operand_a_o,
output logic [63:0] operand_b_o,
input logic alu_ready_i,
output logic alu_valid_o,
input logic lsu_ready_i,
output logic lsu_valid_o,
input logic mult_ready_i,
output logic mult_valid_o,
// write back port
input logic [4:0] waddr_a_i,
input logic [63:0] wdata_a_i,
input logic we_a_i
);
logic full_o;
logic [31:0][$bits(fu_t)-1:0] rd_clobber_o;
logic [4:0] rs1_i;
logic [63:0] rs1_o;
logic rs1_valid_o;
logic [4:0] rs2_i;
logic [63:0] rs2_o;
logic rs2_valid_o;
scoreboard_entry commit_instr_o;
logic commit_ack_i;
scoreboard_entry decoded_instr_i;
logic decoded_instr_valid_i;
scoreboard_entry issue_instr_o;
logic issue_instr_valid_o;
logic issue_ack_i;
logic [63:0] pc_i;
logic [63:0] wdata_i;
logic wb_valid_i;
// ToDo: Branching logic
assign ready_o = ~full_o;
scoreboard scoreboard_i (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.full_o (full_o ),
.flush_i (flush_i ),
.rd_clobber_o (rd_clobber_o ),
.rs1_i (rs1_i ),
.rs1_o (rs1_o ),
.rs1_valid_o (rs1_valid_o ),
.rs2_i (rs2_i ),
.rs2_o (rs2_o ),
.rs2_valid_o (rs2_valid_o ),
.commit_instr_o (commit_instr_o ),
.commit_ack_i (commit_ack_i ),
.decoded_instr_i (decoded_instr_i ),
.decoded_instr_valid_i(decoded_instr_valid_i),
.issue_instr_o (issue_instr_o ),
.issue_instr_valid_o (issue_instr_valid_o ),
.issue_ack_i (issue_ack_i ),
.pc_i (pc_i ),
.wdata_i (wdata_i ),
.wb_valid_i (wb_valid_i )
);
issue_read_operands issue_read_operands_i (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.test_en_i (test_en_i ),
.issue_instr_i (issue_instr_o ),
.issue_instr_valid_i(issue_instr_valid_o),
.issue_ack_o (issue_ack_i ),
.rs1_o (rs1_i ),
.rs1_i (rs1_o ),
.rs1_valid_i (rs1_valid_o ),
.rs2_o (rs2_i ),
.rs2_i (rs2_o ),
.rs2_valid_i (rs2_valid_o ),
.rd_clobber_i (rd_clobber_o ),
.operator_o (operator_o ),
.operand_a_o (operand_a_o ),
.operand_b_o (operand_b_o ),
.alu_ready_i (alu_ready_i ),
.alu_valid_o (alu_valid_o ),
.lsu_ready_i (lsu_ready_i ),
.lsu_valid_o (lsu_valid_o ),
.mult_ready_i (mult_ready_i ),
.mult_valid_o (mult_valid_o ),
.waddr_a_i (waddr_a_i ),
.wdata_a_i (wdata_a_i ),
.we_a_i (we_a_i )
);
endmodule

9
include/debug_if.svh
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@ -2,6 +2,12 @@
// Date: 3/18/2017
// Description: Debug interface for memory mapped debug
// The interface can be used in Master or Slave mode.
//
// Copyright (C) 2017 ETH Zurich, University of Bologna
// All rights reserved.
`ifndef DEBUG_IF__SV
`define DEBUG_IF__SV
interface debug_if
#(
parameter ADDR_WIDTH = 15
@ -27,4 +33,5 @@ interface debug_if
input req, addr, we, wdata,
output gnt, rvalid, rdata
);
endinterface
endinterface
`endif

50
include/mem_if.svh
View file

@ -2,31 +2,37 @@
// Date: 3/18/2017
// Description: Generic memory interface used by the core.
// The interface can be used in Master or Slave mode.
// Guard statement proposed by "Easier UVM" (doulos)
//
// Copyright (C) 2017 ETH Zurich, University of Bologna
// All rights reserved.
// Guard statement proposed by "Easier UVM" (doulos)
`ifndef MEM_IF__SV
`define MEM_IF__SV
interface mem_if #(parameter int ADDRESS_SIZE = 64);
logic [ADDRESS_SIZE-1:0] address; // Address for read/write request
logic [31:0] data_wdata; // Data to be written
logic data_req; // Requests read data
logic data_gnt; // Request has been granted, signals can be changed as
// soon as request has been granted
logic data_rvalid; // Read data is valid
logic [31:0] data_rdata; // Read data
logic data_we; // Write enable
logic [3:0] data_be; // Byte enable
// Memory interface configured as master
modport Master
(
input address, data_wdata, data_req, data_we, data_be;
output data_gnt, data_rvalid, data_rdata;
);
// Memory interface configured as slave
modport Slave
(
input address, data_wdata, data_req, data_we, data_be;
output data_gnt, data_rvalid, data_rdata;
interface mem_if
#(
parameter int ADDRESS_SIZE = 64
);
logic [ADDRESS_SIZE-1:0] address; // Address for read/write request
logic [31:0] data_wdata; // Data to be written
logic data_req; // Requests read data
logic data_gnt; // Request has been granted, signals can be changed as
// soon as request has been granted
logic data_rvalid; // Read data is valid
logic [31:0] data_rdata; // Read data
logic data_we; // Write enable
logic [3:0] data_be; // Byte enable
// Memory interface configured as master
modport Master
(
input address, data_wdata, data_req, data_we, data_be,
output data_gnt, data_rvalid, data_rdata
);
// Memory interface configured as slave
modport Slave
(
input address, data_wdata, data_req, data_we, data_be,
output data_gnt, data_rvalid, data_rdata
);
endinterface
`endif

7
issue_read_operands.sv
View file

@ -12,7 +12,7 @@ import ariane_pkg::*;
module issue_read_operands (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic rst_ni, // Asynchronous reset active low
input logic test_en_i,
// coming from scoreboard
input scoreboard_entry issue_instr_i,
@ -86,6 +86,8 @@ module issue_read_operands (
fu_busy = ~lsu_ready_i;
CSR:
fu_busy = 1'b0;
default:
fu_busy = 1'b0;
endcase
end
@ -158,6 +160,9 @@ module issue_read_operands (
mult_valid_o = 1'b1;
LSU:
lsu_valid_o = 1'b1;
default: begin
end
endcase
end
end

17
regfile.sv
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@ -27,7 +27,7 @@
// //
////////////////////////////////////////////////////////////////////////////////
module zeroriscy_register_file
module regfile
#(
parameter DATA_WIDTH = 32
)
@ -76,12 +76,6 @@ module zeroriscy_register_file
logic clk_int;
int unsigned i;
int unsigned j;
int unsigned k;
genvar x;
//-----------------------------------------------------------------------------
//-- READ : Read address decoder RAD
//-----------------------------------------------------------------------------
@ -116,9 +110,9 @@ module zeroriscy_register_file
//-----------------------------------------------------------------------------
always_comb
begin : p_WADa
for(i = 1; i < NUM_WORDS; i++)
for (int unsigned i = 1; i < NUM_WORDS; i++)
begin : p_WordItera
if ( (we_a_i == 1'b1 ) && (waddr_a_int == i) )
if ( (we_a_i == 1'b1 ) && (waddr_a_int == i[4:0]) )
waddr_onehot_a[i] = 1'b1;
else
waddr_onehot_a[i] = 1'b0;
@ -129,8 +123,9 @@ module zeroriscy_register_file
//-----------------------------------------------------------------------------
//-- WRITE : Clock gating (if integrated clock-gating cells are available)
//-----------------------------------------------------------------------------
genvar x;
generate
for(x = 1; x < NUM_WORDS; x++)
for (x = 1; x < NUM_WORDS; x++)
begin : CG_CELL_WORD_ITER
cluster_clock_gating CG_Inst
(
@ -156,7 +151,7 @@ module zeroriscy_register_file
// Note: The assignment has to be done inside this process or Modelsim complains about it
mem[0] = '0;
for(k = 1; k < NUM_WORDS; k++)
for(int unsigned k = 1; k < NUM_WORDS; k++)
begin : w_WordIter
if(mem_clocks[k] == 1'b1)
mem[k] = wdata_a_q;

32
util/cluster_clock_gating.sv Executable file
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@ -0,0 +1,32 @@
/* Behavioural GLock Gating
* File: cluster_clock_gating.sv
* Author: ?
* Date: ?
*
* Copyright (C) 2017 ETH Zurich, University of Bologna
* All rights reserved.
*/
module cluster_clock_gating
(
input logic clk_i,
input logic en_i,
input logic test_en_i,
output logic clk_o
);
`ifdef PULP_FPGA_EMUL
// no clock gates in FPGA flow
assign clk_o = clk_i;
`else
logic clk_en;
always_latch
begin
if (clk_i == 1'b0)
clk_en <= en_i | test_en_i;
end
assign clk_o = clk_i & clk_en;
`endif
endmodule