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Correct style issues and changes to pass Travis

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This commit is contained in:
Dr Jonathan Kimmitt 2019-01-25 09:34:39 +00:00
parent 1311a8da0b
commit 29ffdf1b55
4 changed files with 31 additions and 30 deletions
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26
fpga/src/dualmem_widen.sv
View file

@ -1,17 +1,17 @@
module dualmem_widen(clka, clkb, dina, dinb, addra, addrb, wea, web, douta, doutb, ena, enb);
input wire clka, clkb;
input [15:0] dina;
input [63:0] dinb;
input [10:0] addra;
input [8:0] addrb;
input [1:0] wea;
input [1:0] web;
input [0:0] ena, enb;
output [15:0] douta;
output [63:0] doutb;
module dualmem_widen(
input wire clka, clkb,
input [15:0] dina,
input [63:0] dinb,
input [10:0] addra,
input [8:0] addrb,
input [1:0] wea,
input [1:0] web,
output [15:0] douta,
output [63:0] doutb,
input [0:0] ena, enb
);
genvar r;
wire [47:0] dout;

23
fpga/src/dualmem_widen8.sv
View file

@ -1,16 +1,15 @@
module dualmem_widen8(clka, clkb, dina, dinb, addra, addrb, wea, web, douta, doutb, ena, enb);
input wire clka, clkb;
input [15:0] dina;
input [63:0] dinb;
input [12:0] addra;
input [10:0] addrb;
input [1:0] wea;
input [1:0] web;
input [0:0] ena, enb;
output [15:0] douta;
output [63:0] doutb;
module dualmem_widen8(
input wire clka, clkb,
input [15:0] dina,
input [63:0] dinb,
input [12:0] addra,
input [10:0] addrb,
input [1:0] wea,
input [1:0] web,
output [15:0] douta,
output [63:0] doutb,
input [0:0] ena, enb);
genvar r;
wire [63:0] dout0;

6
fpga/src/eth_mac_1g.sv
View file

@ -29,12 +29,10 @@ THE SOFTWARE.
/*
* 1G Ethernet MAC
*/
module eth_mac_1g #
(
module eth_mac_1g #(
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
) (
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,

6
tb/ariane_peripherals.sv
View file

@ -480,7 +480,11 @@ module ariane_peripherals #(
// ---------------
// 4. Ethernet
// ---------------
begin
if (0)
begin
end
else
begin
assign irq_sources [2] = 1'b0;
assign ethernet.aw_ready = 1'b1;
assign ethernet.ar_ready = 1'b1;