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🐛 Fix bitmask in medeleg

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This commit is contained in:
Florian Zaruba 2017-06-08 16:07:53 +02:00
parent f6b226ad4c
commit 2ab598e8a5
2 changed files with 7 additions and 6 deletions
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5
Makefile
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@ -40,8 +40,9 @@ riscv-tests = rv64ui-p-add rv64ui-p-addi rv64ui-p-slli rv64ui-p-addiw rv64ui-p-a
rv64ui-p-sraiw rv64ui-p-sraw rv64ui-p-srl rv64ui-p-srli rv64ui-p-srliw rv64ui-p-srlw \
rv64ui-p-lb rv64ui-p-lbu rv64ui-p-ld rv64ui-p-lh rv64ui-p-lhu rv64ui-p-lui \
rv64ui-p-lw rv64ui-p-lwu \
rv64mi-p-csr rv64mi-p-mcsr rv64mi-p-illegal rv64mi-p-ma_addr rv64mi-p-ma_fetch \
rv64mi-p-sbreak rv64mi-p-scall
rv64mi-p-csr rv64mi-p-mcsr rv64mi-p-illegal rv64mi-p-ma_addr rv64mi-p-ma_fetch rv64mi-p-sbreak rv64mi-p-scall \
rv64si-p-csr
riscv-test = rv64ui-p-add
# Search here for include files (e.g.: non-standalone components)

8
src/csr_regfile.sv
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@ -259,7 +259,7 @@ module csr_regfile #(
end
// machine exception delegation register
// 0 - 12 exceptions supported
CSR_MEDELEG: medeleg_n = csr_wdata & 64'hBFF;
CSR_MEDELEG: medeleg_n = csr_wdata & 64'hF7FF;
// machine interrupt delegation register
// we do not support user interrupt delegation
CSR_MIDELEG: mideleg_n = csr_wdata & 64'hBBB;
@ -315,11 +315,11 @@ module csr_regfile #(
// this can either be user or supervisor mode
mstatus_n.spp = logic'(priv_lvl_q);
// set cause
scause_n = ex_i.cause;
scause_n = ex_i.cause;
// set epc
sepc_n = pc_i;
sepc_n = pc_i;
// set mtval or stval
stval_n = ex_i.tval;
stval_n = ex_i.tval;
// trap to machine mode
end else begin
// update mstatus