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Add Zicond Extension support in CVA6 (#1405)

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Fatima Saleem 2023-09-15 11:19:50 +05:00 • committed by GitHub
parent 5c3e3d4545
commit 2ac676d931
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15 changed files with 52 additions and 5 deletions
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7
core/alu.sv
View file

@ -302,6 +302,13 @@ module alu import ariane_pkg::*; #(
default: ; // default case to suppress unique warning
endcase
end
if (CVA6Cfg.RCONDEXT) begin
unique case (fu_data_i.operation)
CZERO_EQZ : result_o = (|fu_data_i.operand_b) ? fu_data_i.operand_a : '0; // move zero to rd if rs2 is equal to zero else rs1
CZERO_NEZ : result_o = (|fu_data_i.operand_b) ? '0 : fu_data_i.operand_a; // move zero to rd if rs2 is nonzero else rs1
default: ; // default case to suppress unique warning
endcase
end
//VCS coverage on
end
endmodule

1
core/cva6.sv
View file

@ -178,6 +178,7 @@ module cva6 import ariane_pkg::*; #(
CVA6Cfg.RVC,
CVA6Cfg.XFVec,
CVA6Cfg.CvxifEn,
CVA6Cfg.RCONDEXT,
// Extended
bit'(RVF),
bit'(RVD),

23
core/decoder.sv
View file

@ -46,6 +46,7 @@ module decoder import ariane_pkg::*; #(
);
logic illegal_instr;
logic illegal_instr_bm;
logic illegal_instr_zic;
logic illegal_instr_non_bm;
// this instruction is an environment call (ecall), it is handled like an exception
logic ecall;
@ -104,6 +105,7 @@ module decoder import ariane_pkg::*; #(
illegal_instr = 1'b0;
illegal_instr_non_bm = 1'b0;
illegal_instr_bm = 1'b0;
illegal_instr_zic = 1'b0;
instruction_o.pc = pc_i;
instruction_o.trans_id = '0;
instruction_o.fu = NONE;
@ -577,11 +579,24 @@ module decoder import ariane_pkg::*; #(
illegal_instr_bm = 1'b1;
end
endcase
illegal_instr = illegal_instr_non_bm & illegal_instr_bm;
//VCS coverage on
end else begin
illegal_instr = illegal_instr_non_bm;
end
if (CVA6Cfg.RCONDEXT) begin
unique case ({instr.rtype.funct7, instr.rtype.funct3})
//Conditional move
{7'b000_0111, 3'b101}: instruction_o.op = ariane_pkg::CZERO_EQZ; // czero.eqz
{7'b000_0111, 3'b111}: instruction_o.op = ariane_pkg::CZERO_NEZ; // czero.nez
default: begin
illegal_instr_zic = 1'b1;
end
endcase
end
//VCS coverage on
unique case ({ariane_pkg::BITMANIP, CVA6Cfg.RCONDEXT})
2'b00 : illegal_instr = illegal_instr_non_bm;
2'b01 : illegal_instr = illegal_instr_non_bm & illegal_instr_zic;
2'b10 : illegal_instr = illegal_instr_non_bm & illegal_instr_bm;
2'b11 : illegal_instr = illegal_instr_non_bm & illegal_instr_bm & illegal_instr_zic;
endcase
end
end

4
core/include/ariane_pkg.sv
View file

@ -503,7 +503,9 @@ package ariane_pkg;
// Bitmanip Logical with negate op (Bitmanip)
ANDN, ORN, XNOR,
// Accelerator operations
ACCEL_OP, ACCEL_OP_FS1, ACCEL_OP_FD, ACCEL_OP_LOAD, ACCEL_OP_STORE
ACCEL_OP, ACCEL_OP_FS1, ACCEL_OP_FD, ACCEL_OP_LOAD, ACCEL_OP_STORE,
// Zicond instruction
CZERO_EQZ, CZERO_NEZ
} fu_op;
typedef struct packed {

3
core/include/config_pkg.sv
View file

@ -31,6 +31,7 @@ package config_pkg;
bit RVC;
bit XFVec;
bit CvxifEn;
bit RCONDEXT;
// Calculated
bit RVF;
bit RVD;
@ -66,6 +67,7 @@ package config_pkg;
bit'(1), // RVC
bit'(0), // XFVec
bit'(1), // CvxifEn
bit'(0), // EnableZiCond
// Extended
bit'(0), // RVF
bit'(0), // RVD
@ -99,6 +101,7 @@ package config_pkg;
bit'(0), // RVC
bit'(0), // XFVec
bit'(0), // CvxifEn
bit'(0), // EnableZiCond
// Extended
bit'(0), // RVF
bit'(0), // RVD

2
core/include/cv32a60x_config_pkg.sv
View file

@ -28,6 +28,7 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigZiCondExtEn = 1;
localparam CVA6ConfigAxiIdWidth = 4;
localparam CVA6ConfigAxiAddrWidth = 64;
@ -91,6 +92,7 @@ package cva6_config_pkg;
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
bit'(CVA6ConfigZiCondExtEn), // ZiCondExtEn
// Extended
bit'(0), // RVF
bit'(0), // RVD

3
core/include/cv32a6_embedded_config_pkg.sv
View file

@ -27,6 +27,7 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 0;
localparam CVA6ConfigBExtEn = 1;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigZiCondExtEn = 1;
localparam CVA6ConfigAxiIdWidth = 4;
localparam CVA6ConfigAxiAddrWidth = 64;
@ -90,6 +91,8 @@ package cva6_config_pkg;
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
bit'(CVA6ConfigZiCondExtEn), // ZiCondExtEn
// Extended
bit'(0), // RVF
bit'(0), // RVD

2
core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
View file

@ -28,6 +28,7 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigZiCondExtEn = 0;
localparam CVA6ConfigAxiIdWidth = 4;
localparam CVA6ConfigAxiAddrWidth = 64;
@ -91,6 +92,7 @@ package cva6_config_pkg;
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
bit'(CVA6ConfigZiCondExtEn), // ZiCondExtEn
// Extended
bit'(0), // RVF
bit'(0), // RVD

2
core/include/cv32a6_imac_sv0_config_pkg.sv
View file

@ -28,6 +28,7 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigZiCondExtEn = 0;
localparam CVA6ConfigAxiIdWidth = 4;
localparam CVA6ConfigAxiAddrWidth = 64;
@ -91,6 +92,7 @@ package cva6_config_pkg;
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
bit'(CVA6ConfigZiCondExtEn), // ZiCondExtEn
// Extended
bit'(0), // RVF
bit'(0), // RVD

2
core/include/cv32a6_imac_sv32_config_pkg.sv
View file

@ -28,6 +28,7 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigZiCondExtEn = 0;
localparam CVA6ConfigAxiIdWidth = 4;
localparam CVA6ConfigAxiAddrWidth = 64;
@ -91,6 +92,7 @@ package cva6_config_pkg;
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
bit'(CVA6ConfigZiCondExtEn), // ZiCondExtEn
// Extended
bit'(0), // RVF
bit'(0), // RVD

2
core/include/cv32a6_imafc_sv32_config_pkg.sv
View file

@ -28,6 +28,7 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigZiCondExtEn = 0;
localparam CVA6ConfigAxiIdWidth = 4;
localparam CVA6ConfigAxiAddrWidth = 64;
@ -91,6 +92,7 @@ package cva6_config_pkg;
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
bit'(CVA6ConfigZiCondExtEn), // ZiCondExtEn
// Extended
bit'(0), // RVF
bit'(0), // RVD

1
core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
View file

@ -91,6 +91,7 @@ package cva6_config_pkg;
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
bit'(CVA6ConfigZiCondExtEn), // ZiCondExtEn
// Extended
bit'(0), // RVF
bit'(0), // RVD

2
core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file

@ -28,6 +28,7 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 1;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigZiCondExtEn = 1;
localparam CVA6ConfigAxiIdWidth = 4;
localparam CVA6ConfigAxiAddrWidth = 64;
@ -91,6 +92,7 @@ package cva6_config_pkg;
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
bit'(CVA6ConfigZiCondExtEn), // RCONDEXT
// Extended
bit'(0), // RVF
bit'(0), // RVD

2
core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
View file

@ -28,6 +28,7 @@ package cva6_config_pkg;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigVExtEn = 0;
localparam CVA6ConfigZiCondExtEn = 0;
localparam CVA6ConfigAxiIdWidth = 4;
localparam CVA6ConfigAxiAddrWidth = 64;
@ -91,6 +92,7 @@ package cva6_config_pkg;
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
bit'(CVA6ConfigZiCondExtEn), // ZiCondExtEn
// Extended
bit'(0), // RVF
bit'(0), // RVD

1
core/include/cv64a6_imafdcv_sv39_config_pkg.sv
View file

@ -91,6 +91,7 @@ package cva6_config_pkg;
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
bit'(CVA6ConfigZiCondExtEn), // ZiCondExtEn
// Extended
bit'(0), // RVF
bit'(0), // RVD