Switch to UVM reporting and set verbosity for display

Makefile

@@ -115,15 +115,15 @@ $(library):
 
 sim: build
 	vsim${questa_version} -lib ${library} ${top_level}_optimized +UVM_TESTNAME=${test_case} +BASEDIR=$(riscv-test-dir) \
-	+ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
+	+ASMTEST=$(riscv-test)  +UVM_VERBOSITY=HIGH -coverage -classdebug -do "do tb/wave/wave_core.do"
 
 simc: build
 	vsim${questa_version} -c -lib ${library} ${top_level}_optimized +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
-	 +BASEDIR=$(riscv-test-dir) +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
+	 +BASEDIR=$(riscv-test-dir) +UVM_VERBOSITY=HIGH  +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
 
 run-asm-tests: build
 	$(foreach test, $(riscv-tests), vsim$(questa_version) +BASEDIR=$(riscv-test-dir) +max-cycles=$(max_cycles) \
-		+UVM_TESTNAME=$(test_case) +ASMTEST=$(test) +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c \
+		+UVM_TESTNAME=$(test_case) +UVM_VERBOSITY=LOW +ASMTEST=$(test) +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c +UVM_VERBOSITY=LOW\
 		-coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"  \
 		$(library).$(test_top_level)_optimized;)
 

ariane-run-torture

@@ -3,5 +3,5 @@
 cd output && make
 cd ../..
 # start the simulation
-vsim-10.6 -c -lib work core_tb_optimized +UVM_TESTNAME=core_test $2 +BASEDIR=riscv-torture $1 +ASMTEST=$3 -coverage -classdebug -do "run -a"
+vsim-10.6 -c -lib work core_tb_optimized +UVM_TESTNAME=core_test $2 +BASEDIR=riscv-torture $1 +ASMTEST=$3  +UVM_VERBOSITY=LOW -coverage -classdebug -do "run -a"
 

src/ariane.sv

@@ -550,7 +550,7 @@ module ariane
     assign tracer_if.exception         = commit_stage_i.exception_o;
 
     program instr_tracer (instruction_tracer_if tracer_if);
-        instruction_tracer it = new (tracer_if);
+        instruction_tracer it = new (tracer_if, 1'b0);
 
         initial begin
             #15ns;

src/util/instruction_tracer.svh

@@ -18,7 +18,6 @@
 //
 
 class instruction_tracer;
-
     // interface to the core
     virtual instruction_tracer_if tracer_if;
     // keep the decoded instructions in a queue
@@ -36,11 +35,18 @@ class instruction_tracer;
     int f;
     // address mapping
     // contains mappings of the form vaddr <-> paddr
+    // should it print the instructions to the console
+    logic display_instructions;
     logic [63:0] store_mapping[$], load_mapping[$], address_mapping;
 
-    function new(virtual instruction_tracer_if tracer_if);
+    static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
+
+
+    function new(virtual instruction_tracer_if tracer_if, logic display_instructions);
 
         this.tracer_if = tracer_if;
+        this.display_instructions = display_instructions;
+
     endfunction : new
 
     function void create_file(logic [5:0] cluster_id, logic [3:0] core_id);
@@ -166,7 +172,7 @@ class instruction_tracer;
         instruction_trace_item iti = new ($time, clk_ticks, sbe, instr, this.reg_file, result, paddr);
         // print instruction to console
         string print_instr = iti.printInstr();
-        $display(print_instr);
+        `uvm_info( "Tracer",  print_instr, UVM_HIGH)
         $fwrite(this.f, {print_instr, "\n"});
     endfunction;
 

src/util/instruction_tracer_pkg.sv

@@ -18,7 +18,8 @@
 //
 package instruction_tracer_pkg;
     import ariane_pkg::*;
-
+    import uvm_pkg::*;
+    `include "uvm_macros.svh"
     `include "instruction_tracer_defines.svh"
     `include "instruction_trace_item.svh"
     `include "exception_trace_item.svh"

tb/core_tb.sv

@@ -37,6 +37,8 @@ module core_tb;
     logic rst_ni;
     logic rtc_i;
 
+    logic display_instr;
+
     longint unsigned cycles;
     longint unsigned max_cycles;