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Several small fixes for FPGA synthesis.

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This commit is contained in:
Michael Schaffner 2018-10-31 16:04:25 +01:00
parent cb0b0bec03
commit 2cce24643a
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GPG key ID: 7AA09AE049819C2C
5 changed files with 13 additions and 13 deletions
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14
src/cache_subsystem/serpent_dcache_mem.sv
View file

@ -255,8 +255,8 @@ module serpent_dcache_mem #(
for (genvar k = 0; k < DCACHE_NUM_BANKS; k++) begin : g_data_banks
// Data RAM
sram #(
.DATA_WIDTH ( 64*DCACHE_SET_ASSOC ),
.NUM_WORDS ( DCACHE_NUM_WORDS )
.DATA_WIDTH ( ariane_pkg::DCACHE_SET_ASSOC * 64 ),
.NUM_WORDS ( serpent_cache_pkg::DCACHE_NUM_WORDS )
) i_data_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
@ -277,8 +277,8 @@ module serpent_dcache_mem #(
// Tag RAM
sram #(
// tag + valid bit
.DATA_WIDTH ( DCACHE_TAG_WIDTH+1 ),
.NUM_WORDS ( DCACHE_NUM_WORDS )
.DATA_WIDTH ( ariane_pkg::DCACHE_TAG_WIDTH + 1 ),
.NUM_WORDS ( serpent_cache_pkg::DCACHE_NUM_WORDS )
) i_tag_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
@ -329,9 +329,9 @@ module serpent_dcache_mem #(
else $fatal(1,"[l1 dcache] wbuffer_hit_oh signal must be hot1");
// this is only used for verification!
logic vld_mirror[DCACHE_NUM_WORDS-1:0][DCACHE_SET_ASSOC-1:0];
logic [DCACHE_TAG_WIDTH-1:0] tag_mirror[DCACHE_NUM_WORDS-1:0][DCACHE_SET_ASSOC-1:0];
logic [DCACHE_SET_ASSOC-1:0] tag_write_duplicate_test;
logic vld_mirror[serpent_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0];
logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag_mirror[serpent_cache_pkg::DCACHE_NUM_WORDS-1:0][ariane_pkg::DCACHE_SET_ASSOC-1:0];
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] tag_write_duplicate_test;
always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror
if(~rst_ni) begin

6
src/cache_subsystem/serpent_dcache_missunit.sv
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@ -114,7 +114,7 @@ module serpent_dcache_missunit #(
assign cache_en_o = enable_q;
assign cnt_d = (flush_en) ? cnt_q + 1 : '0;
assign flush_done = (cnt_q == DCACHE_NUM_WORDS-1);
assign flush_done = (cnt_q == serpent_cache_pkg::DCACHE_NUM_WORDS-1);
assign miss_req_masked_d = ( lock_reqs ) ? miss_req_masked_q :
( mask_reads ) ? miss_we_i & miss_req_i : miss_req_i;
@ -140,7 +140,7 @@ module serpent_dcache_missunit #(
// find invalid cache line
lzc #(
.WIDTH ( DCACHE_SET_ASSOC )
.WIDTH ( ariane_pkg::DCACHE_SET_ASSOC )
) i_lzc_inv (
.in_i ( ~miss_vld_bits_i[miss_port_idx] ),
.cnt_o ( inv_way ),
@ -149,7 +149,7 @@ module serpent_dcache_missunit #(
// generate random cacheline index
lfsr_8bit #(
.WIDTH ( DCACHE_SET_ASSOC )
.WIDTH ( ariane_pkg::DCACHE_SET_ASSOC )
) i_lfsr_inv (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),

2
src/ex_stage.sv
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@ -215,7 +215,7 @@ module ex_stage (
generate
if (FP_PRESENT) begin : fpu_gen
fu_data_t fpu_data;
assign fpu_data.operator = fpu_valid_i ? fu_data_i : '0;
assign fpu_data = fpu_valid_i ? fu_data_i : '0;
fpu_wrap fpu_i (
.clk_i,

2
src/mult.sv
View file

@ -40,7 +40,7 @@ module mult (
// ---------------------
// Multiplication
// ---------------------
mul i_mul (
multiplier i_multiplier (
.clk_i,
.rst_ni,
.trans_id_i ( fu_data_i.trans_id ),

2
src/multiplier.sv
View file

@ -16,7 +16,7 @@
import ariane_pkg::*;
module mul (
module multiplier (
input logic clk_i,
input logic rst_ni,
input logic [TRANS_ID_BITS-1:0] trans_id_i,