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instr_tracer.sv: Fix double sampling (#2782)
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Currently, the instruction trace update logic is triggered on both clock
edges, leading to double entries in the instruction trace and a wrong
cycle count. Fix this by updating the trace only on positive clock edges.

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
This commit is contained in:
Nils Wistoff 2025-02-20 17:18:59 +11:00 • committed by GitHub
parent a55db35bd1
commit 2d411b2dc8
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common/local/util/instr_tracer.sv
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@ -94,7 +94,7 @@ module instr_tracer #(
forever begin forever begin
automatic bp_resolve_t bp_instruction = '0; automatic bp_resolve_t bp_instruction = '0;
// new cycle, we are only interested if reset is de-asserted // new cycle, we are only interested if reset is de-asserted
@(pck) if (rstn !== 1'b1) begin @(posedge pck) if (rstn !== 1'b1) begin
flush(); flush();
continue; continue;
end end