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Correct small mismatch in icache TB (piton-specific data replication in reads)
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commit
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1 changed files with 15 additions and 16 deletions
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@ -72,8 +72,8 @@ module mem_emul #(
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always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlb_rand
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automatic bit ok = 0;
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automatic int rnd = 0;
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automatic logic [31:0] val;
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automatic logic [63:0] lval;
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automatic logic [31:0] val;
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automatic logic [63:0] lval;
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if(~rst_ni) begin
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mem_ready_q <= '0;
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@ -81,7 +81,7 @@ module mem_emul #(
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rand_addr_q <= '0;
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initialized_q <= '0;
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end else begin
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// fill the memory once with random data
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if (~initialized_q) begin
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for (int k=0; k<MemWords; k++) begin
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@ -90,15 +90,15 @@ module mem_emul #(
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mem_array_shadow[k] <= val;
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end
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initialized_q <= 1;
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end
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end
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// re-randomize noncacheable I/O space if requested
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if (io_rand_en_i) begin
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for (int k=0; k<CachedAddrBeg; k++) begin
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ok = randomize(val);
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mem_array[k] <= val;
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end
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end
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end
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// generate random contentions
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if (mem_rand_en_i) begin
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@ -112,7 +112,7 @@ module mem_emul #(
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end
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// generate random invalidations
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if (inv_rand_en_i) begin
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if (infifo_push) begin
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// update coherent memory view for expected responses
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@ -120,7 +120,7 @@ module mem_emul #(
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lval = inval_addr_queue.pop_back();
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val = inval_data_queue.pop_back();
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mem_array_shadow[lval] <= val;
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end
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end
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end
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ok = randomize(rnd) with {rnd > 0; rnd <= 100;};
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@ -150,7 +150,7 @@ module mem_emul #(
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infifo_data = '0;
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outfifo_pop = 0;
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infifo_data.rtype = ICACHE_IFILL_ACK;
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// generate random invalidation
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if (mem_inv_q) begin
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@ -173,11 +173,10 @@ module mem_emul #(
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infifo_data.nc = 1'b1;
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infifo_data.f4b = 1'b1;
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// replicate words (this is done in openpiton, too)
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// note: openpiton replicates the words here. we do not do this currently,
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// but this could save us another mux in the critical path in the icache.
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// for (int k=0; k<ICACHE_LINE_WIDTH/32; k++) begin
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// infifo_data.data[k*32 +:32] = mem_array[outfifo_data.paddr>>2];
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// end
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// note: openpiton replicates the words here.
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for (int k=0; k<ICACHE_LINE_WIDTH/32; k++) begin
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infifo_data.data[k*32 +:32] = mem_array[outfifo_data.paddr>>2];
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end
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infifo_data.data[0 +:32] = mem_array[outfifo_data.paddr>>2];
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end else begin
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infifo_data.nc = outfifo_data.nc;
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@ -257,11 +256,11 @@ module mem_emul #(
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assign exp_vaddr_o = stim_addr;
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align0: assert property (
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@(posedge clk_i) disable iff (~rst_ni) ~exp_empty |-> stim_addr[1:0] == 0)
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@(posedge clk_i) disable iff (~rst_ni) ~exp_empty |-> stim_addr[1:0] == 0)
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else $fatal(1,"stim_addr is not 32bit word aligned");
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align1: assert property (
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@(posedge clk_i) disable iff (~rst_ni) ~outfifo_empty |-> outfifo_data.paddr[1:0] == 0)
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@(posedge clk_i) disable iff (~rst_ni) ~outfifo_empty |-> outfifo_data.paddr[1:0] == 0)
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else $fatal(1,"paddr is not 32bit word aligned");
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