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This fixes an issue in the wt_axi_adapter that only appeared when using dcache lines that are wider than icache lines.

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Michael Schaffner 2019-03-26 13:23:43 +01:00 • committed by Florian Zaruba
parent 20e887cd2b
commit 2f75662957
2 changed files with 28 additions and 21 deletions
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5
CHANGELOG.md
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@ -6,6 +6,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
## [Unreleased]
### Changed
- Fix bug in wt_axi_adapter (only appeared when dcache lines were wider than icache lines)
### 4.1.2
- Update FPU headers (license)

44
src/cache_subsystem/wt_axi_adapter.sv
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@ -21,32 +21,34 @@ module wt_axi_adapter #(
parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX,
parameter int unsigned AxiIdWidth = 4
) (
input logic clk_i,
input logic rst_ni,
input logic clk_i,
input logic rst_ni,
// icache
input logic icache_data_req_i,
output logic icache_data_ack_o,
input icache_req_t icache_data_i,
// returning packets must be consumed immediately
output logic icache_rtrn_vld_o,
output icache_rtrn_t icache_rtrn_o,
// icache
input logic icache_data_req_i,
output logic icache_data_ack_o,
input icache_req_t icache_data_i,
// returning packets must be consumed immediately
output logic icache_rtrn_vld_o,
output icache_rtrn_t icache_rtrn_o,
// dcache
input logic dcache_data_req_i,
output logic dcache_data_ack_o,
input dcache_req_t dcache_data_i,
// returning packets must be consumed immediately
output logic dcache_rtrn_vld_o,
output dcache_rtrn_t dcache_rtrn_o,
// dcache
input logic dcache_data_req_i,
output logic dcache_data_ack_o,
input dcache_req_t dcache_data_i,
// returning packets must be consumed immediately
output logic dcache_rtrn_vld_o,
output dcache_rtrn_t dcache_rtrn_o,
// AXI port
output ariane_axi::req_t axi_req_o,
input ariane_axi::resp_t axi_resp_i
// AXI port
output ariane_axi::req_t axi_req_o,
input ariane_axi::resp_t axi_resp_i
);
// support up to 512bit cache lines
localparam AxiNumWords = ariane_pkg::ICACHE_LINE_WIDTH/64;
localparam AxiNumWords = (ariane_pkg::ICACHE_LINE_WIDTH/64) * (ariane_pkg::ICACHE_LINE_WIDTH > ariane_pkg::DCACHE_LINE_WIDTH) +
(ariane_pkg::DCACHE_LINE_WIDTH/64) * (ariane_pkg::ICACHE_LINE_WIDTH <= ariane_pkg::DCACHE_LINE_WIDTH) ;
///////////////////////////////////////////////////////
// request path
@ -389,7 +391,7 @@ always_comb begin : p_axi_rtrn_shift
if (dcache_rtrn_rd_en) begin
dcache_first_d = axi_rd_last;
dcache_rd_shift_d = {axi_rd_data, dcache_rd_shift_q[ICACHE_LINE_WIDTH/64-1:1]};
dcache_rd_shift_d = {axi_rd_data, dcache_rd_shift_q[DCACHE_LINE_WIDTH/64-1:1]};
// if this is a single word transaction, we need to make sure that word is placed at offset 0
if (dcache_first_q) begin
dcache_rd_shift_d[0] = axi_rd_data;