✅ Add LSU testbench stub

Makefile

@@ -8,7 +8,7 @@ library = work
 top_level = core_tb
 test_top_level = core_tb
 # test targets
-tests = alu scoreboard fifo mem_arbiter store_queue
+tests = alu scoreboard fifo mem_arbiter store_queue lsu
 # UVM agents
 agents = include/ariane_pkg.svh $(wildcard tb/agents/*/*.sv)
 # path to interfaces
@@ -18,12 +18,12 @@ envs = $(wildcard tb/env/*/*.sv)
 # UVM Sequences
 sequences =  $(wildcard tb/sequences/*/*.sv)
 # Test packages
-test_pkg =tb/test/mem_arbiter/mem_arbiter_sequence_pkg.sv  $(wildcard tb/test/*/*.sv)
+test_pkg = $(wildcard tb/test/*/*sequence_pkg.sv) $(wildcard tb/test/*/*lib_pkg.sv)
 
 # this list contains the standalone components
 src = $(wildcard src/util/*.sv) $(wildcard src/*.sv)
-
-tbs =  tb/alu_tb.sv tb/mem_arbiter_tb.sv tb/core_tb.sv tb/scoreboard_tb.sv tb/store_queue_tb.sv tb/fifo_tb.sv
+# look for testbenches
+tbs =  $(wildcard tb/*_tb.sv)
 
 # Search here for include files (e.g.: non-standalone components)
 incdir = ./includes

src/lsu.sv

@@ -53,8 +53,8 @@ module lsu #(
     input  logic [ASID_WIDTH-1:0]    asid_i,                   // From CSR register file
     input  logic                     flush_tlb_i,
 
-    mem_if.Slave                     instr_if,                 // Instruction memory/cache
-    mem_if.Slave                     data_if,                  // Data memory/cache
+    mem_if.slave                     instr_if,                 // Instruction memory/cache
+    mem_if.slave                     data_if,                  // Data memory/cache
 
     output exception                 lsu_exception_o   // to WB, signal exception status LD/ST exception
 

src/mmu.sv

@@ -55,9 +55,9 @@ module mmu #(
         input logic                             flush_tlb_i,
         // Memory interfaces
         // Instruction memory interface
-        mem_if.Slave                            instr_if,
+        mem_if.slave                            instr_if,
         // Data memory interface
-        mem_if.Slave                            data_if
+        mem_if.slave                            data_if
 );
     // assignments necessary to use interfaces here
     // only done for the few signals of the instruction interface

tb/env/lsu/lsu_env.svh

@@ -0,0 +1,56 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 02.05.2017
+// Description: Environment which instantiates the agent and all environment
+//              related components such as a scoreboard etc.
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+
+class lsu_env extends uvm_env;
+
+    // UVM Factory Registration Macro
+    `uvm_component_utils(lsu_env)
+
+    //------------------------------------------
+    // Data Members
+    //------------------------------------------
+    mem_if_agent m_mem_if_agent;
+    mem_if_sequencer m_mem_if_sequencer;
+    lsu_env_config m_cfg;
+    //------------------------------------------
+    // Methods
+    //------------------------------------------
+
+    // Standard UVM Methods:
+    function new(string name = "lsu_env", uvm_component parent = null);
+      super.new(name, parent);
+    endfunction
+
+    function void build_phase(uvm_phase phase);
+        if (!uvm_config_db #(lsu_env_config)::get(this, "", "lsu_env_config", m_cfg))
+            `uvm_fatal("CONFIG_LOAD", "Cannot get() configuration lsu_env_config from uvm_config_db. Have you set() it?")
+        // Conditional instantiation goes here
+
+        // Create agent configuration
+        uvm_config_db #(mem_if_agent_config)::set(this, "m_mem_if_agent*",
+                                               "mem_if_agent_config",
+                                               m_cfg.m_mem_if_agent_config);
+        m_mem_if_agent = mem_if_agent::type_id::create("m_mem_if_agent", this);
+
+        // Get sequencer
+        m_mem_if_sequencer = mem_if_sequencer::type_id::create("m_mem_if_sequencer", this);
+
+    endfunction:build_phase
+
+    function void connect_phase(uvm_phase phase);
+       m_mem_if_sequencer = m_mem_if_agent.m_sequencer;
+    endfunction: connect_phase
+endclass : lsu_env

tb/env/lsu/lsu_env_config.svh

@@ -0,0 +1,29 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 02.05.2017
+// Description: lsu configuration object
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+
+class lsu_env_config extends uvm_object;
+
+    // UVM Factory Registration Macro
+    `uvm_object_utils(lsu_env_config)
+
+    // a functional unit master interface
+    virtual mem_if m_mem_if;
+
+    // an agent config
+
+    mem_if_agent_config m_mem_if_agent_config;
+
+endclass : lsu_env_config

tb/env/lsu/lsu_env_pkg.sv

@@ -0,0 +1,26 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 02.05.2017
+// Description: lsu package
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+
+package lsu_env_pkg;
+    // Standard UVM import & include:
+    import uvm_pkg::*;
+    `include "uvm_macros.svh"
+    // Testbench related imports
+    import mem_if_agent_pkg::*;
+    // Includes for the config for the environment
+    `include "lsu_env_config.svh"
+    // Includes the environment
+    `include "lsu_env.svh"
+endpackage

tb/lsu_tb.sv

@@ -0,0 +1,90 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 02.05.2017
+// Description: LSU Testbench
+//
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+//
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+//
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+//
+
+module lsu_tb;
+
+    import uvm_pkg::*;
+    // import the main test class
+    import lsu_lib_pkg::*;
+    import ariane_pkg::*;
+
+    logic rst_ni, clk;
+
+    mem_if slave(clk);
+    mem_if instr_if(clk);
+
+    lsu dut (
+        .clk_i                  ( clk         ),
+        .rst_ni                 ( rst_ni      ),
+        .flush_i                ( 1'b0        ),
+        .operator_i             (             ),
+        .operand_a_i            (             ),
+        .operand_b_i            (             ),
+        .imm_i                  (             ),
+        .lsu_ready_o            (             ),
+        .lsu_valid_i            (             ),
+        .lsu_trans_id_i         (             ),
+        .lsu_trans_id_o         (             ),
+        .lsu_result_o           (             ),
+        .lsu_valid_o            (             ),
+        .commit_i               (             ),
+        .enable_translation_i   ( 1'b0        ),
+        .fetch_req_i            (             ),
+        .fetch_gnt_o            (             ),
+        .fetch_valid_o          (             ),
+        .fetch_err_o            (             ),
+        .fetch_vaddr_i          (             ),
+        .fetch_rdata_o          (             ),
+        .priv_lvl_i             (             ),
+        .flag_pum_i             (             ),
+        .flag_mxr_i             (             ),
+        .pd_ppn_i               (             ),
+        .asid_i                 (             ),
+        .flush_tlb_i            (             ),
+        .instr_if               ( instr_if    ),
+        .data_if                ( slave       ),
+        .lsu_exception_o        (             )
+    );
+
+    initial begin
+        clk = 1'b0;
+        rst_ni = 1'b0;
+        repeat(8)
+            #10ns clk = ~clk;
+
+        rst_ni = 1'b1;
+        forever
+            #10ns clk = ~clk;
+    end
+
+    program testbench (mem_if slave);
+        initial begin
+            // register the memory interface
+            uvm_config_db #(virtual mem_if)::set(null, "uvm_test_top", "mem_if", slave);
+
+            // print the topology
+            uvm_top.enable_print_topology = 1;
+            // Start UVM test
+            run_test();
+        end
+    endprogram
+
+    testbench tb (slave);
+endmodule

tb/test/lsu/lsu_lib_pkg.sv

@@ -0,0 +1,41 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 02.05.2017
+// Description: Main test package contains all necessary packages
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+
+package lsu_lib_pkg;
+    // Standard UVM import & include:
+    import uvm_pkg::*;
+    `include "uvm_macros.svh"
+    // Import the memory interface agent
+    import mem_if_agent_pkg::*;
+    // ------------------------------------------------
+    // Environment which will be instantiated
+    // ------------------------------------------------
+    import lsu_env_pkg::*;
+    // ----------------
+    // Sequence Package
+    // ----------------
+    import lsu_sequence_pkg::*;
+    // Test based includes like base test class and specializations of it
+    // ----------------
+    // Base test class
+    // ----------------
+    `include "lsu_test_base.svh"
+    // -------------------
+    // Child test classes
+    // -------------------
+    `include "lsu_test.svh"
+
+endpackage

tb/test/lsu/lsu_sequence_pkg.sv

@@ -0,0 +1,26 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 02.05.2017
+// Description: lsu sequence package
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+
+package lsu_sequence_pkg;
+
+
+import mem_if_agent_pkg::*;
+import uvm_pkg::*;
+
+`include "uvm_macros.svh"
+// Include your sequences here e.g.:
+// `include "fibonacci_sequence.svh"
+endpackage

tb/test/lsu/lsu_test.svh

@@ -0,0 +1,50 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 02.05.2017
+// Description: lsu main test class
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+
+class lsu_test extends lsu_test_base;
+    // UVM Factory Registration Macro
+    `uvm_component_utils(lsu_test)
+    // TODO: declare sequence here
+    // lsu_sequence lsu;
+    //------------------------------------------
+    // Methods
+    //------------------------------------------
+
+    // Standard UVM Methods:
+    function new(string name = "lsu_test", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+
+    function void build_phase(uvm_phase phase);
+        super.build_phase(phase);
+    endfunction
+
+    task run_phase(uvm_phase phase);
+        phase.raise_objection(this, "lsu_test");
+        //fibonacci_sequence fibonacci;
+        super.run_phase(phase);
+
+        // lsu = new("lsu");
+        // TODO: Start sequence here
+        // lsu.start(sequencer_h);
+        // Testlogic goes here
+        #100ns;
+
+        phase.drop_objection(this, "lsu_test");
+    endtask
+
+
+endclass : lsu_test

tb/test/lsu/lsu_test_base.svh

@@ -0,0 +1,82 @@
+// Author: Florian Zaruba, ETH Zurich
+// Date: 02.05.2017
+// Description: lsu base test class
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+
+class lsu_test_base extends uvm_test;
+
+    // UVM Factory Registration Macro
+    `uvm_component_utils(lsu_test_base)
+
+    //------------------------------------------
+    // Data Members
+    //------------------------------------------
+
+    //------------------------------------------
+    // Component Members
+    //------------------------------------------
+    // environment configuration
+    lsu_env_config m_env_cfg;
+    // environment
+    lsu_env m_env;
+    mem_if_sequencer sequencer_h;
+
+    // reset_sequence reset;
+    // ---------------------
+    // Agent configuration
+    // ---------------------
+    // functional unit interface
+    mem_if_agent_config m_cfg;
+
+    //------------------------------------------
+    // Methods
+    //------------------------------------------
+    // Standard UVM Methods:
+    function new(string name = "lsu_test_base", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+
+    // Build the environment, get all configurations
+    // Use the factory pattern in order to facilitate UVM functionality
+    function void build_phase(uvm_phase phase);
+        // create environment
+        m_env_cfg = lsu_env_config::type_id::create("m_env_cfg");
+
+        // create agent configurations and assign interfaces
+        // create agent memory master configuration
+        m_cfg = mem_if_agent_config::type_id::create("m_cfg");
+        m_env_cfg.m_mem_if_agent_config = m_cfg;
+        // Get Virtual Interfaces
+        // get master interface DB
+        if (!uvm_config_db #(virtual mem_if)::get(this, "", "mem_if", m_cfg.fu))
+            `uvm_fatal("VIF CONFIG", "Cannot get() interface mem_if from uvm_config_db. Have you set() it?")
+        m_env_cfg.m_mem_if = m_cfg.fu;
+
+
+        // create environment
+        uvm_config_db #(lsu_env_config)::set(this, "*", "lsu_env_config", m_env_cfg);
+        m_env = lsu_env::type_id::create("m_env", this);
+
+    endfunction
+
+    function void end_of_elaboration_phase(uvm_phase phase);
+        sequencer_h = m_env.m_mem_if_sequencer;
+    endfunction
+
+    task run_phase(uvm_phase phase);
+        // reset = new("reset");
+        // reset.start(sequencer_h);
+    endtask
+
+endclass : lsu_test_base

uvm-scaffold

@@ -1 +1 @@
-Subproject commit 2e9af3001a3f5aed052f4d497a9572a0d6be5b5f
+Subproject commit 4c934eda2fc5a8471717608bcc99d51701bd24a7