update riscv-isa-manual to riscv-isa-release-5ddbdd678-2024-08-01 (#2434)

since last riscv-isa-manual update (CVA6 commit 0bd8b8693)

docs/riscv-isa/riscv-isa-manual

@@ -1 +1 @@
-Subproject commit ebf2e3a0b402cd56fd4b571b705b31f3be62c2cc
+Subproject commit 5ddbdd678a03dc1d7801d4ef5bb143375cae5a43

docs/riscv-isa/src/colophon.adoc

@@ -7,7 +7,7 @@
 This document describes the RISC-V unprivileged architecture tailored for
 OpenHW Group {ohg-config}.
 
-[.big]*_Preface to Document Version 20240703_*
+[.big]*_Preface to Document Version 20240801_*
 
 This document describes the RISC-V unprivileged architecture.
 
@@ -40,8 +40,8 @@ h|Extension h|Version h|Status
 |*Zmmul* |*1.0* |*Ratified*
 |*A* |*2.1* |*Ratified*
 |*Zawrs* |*1.01* |*Ratified*
-|*Zacas* |*1.0* |*Ratifed*
-|*Zabha* |*1.0* |*Ratifed*
+|*Zacas* |*1.0* |*Ratified*
+|*Zabha* |*1.0* |*Ratified*
 |*RVWMO* |*2.0* |*Ratified*
 |*Ztso* |*1.0* |*Ratified*
 |*CMO* |*1.0* |*Ratified*

docs/riscv-isa/src/counters.adoc

@@ -14,7 +14,7 @@ counters (CYCLE, TIME, and INSTRET), which have dedicated functions
 (cycle count, real-time clock, and instructions retired, respectively).
 The Zicntr extension depends on the Zicsr extension.
 
-[TIP]
+[NOTE]
 ====
 We recommend provision of these basic counters in implementations as
 they are essential for basic performance analysis, adaptive and dynamic
@@ -35,7 +35,7 @@ the full 64-bit CSRs directly. In particular, the RDCYCLE, RDTIME, and
 RDINSTRET pseudoinstructions read the full 64 bits of the `cycle`,
 `time`, and `instret` counters.
 
-[TIP]
+[NOTE]
 ====
 The counter pseudoinstructions are mapped to the read-only
 `csrrs rd, counter, x0` canonical form, but the other read-only CSR
@@ -47,7 +47,7 @@ For base ISAs with XLEN=32, the Zicntr extension enables the three
 RDTIME, and RDINSTRET pseudoinstructions provide the lower 32 bits, and
 the RDCYCLEH, RDTIMEH, and RDINSTRETH pseudoinstructions provide the
 upper 32 bits of the respective counters.
-[TIP]
+[NOTE]
 ====
 We required the counters be 64 bits wide, even when XLEN=32, as
 otherwise it is very difficult for software to determine if values have
@@ -67,7 +67,7 @@ overflow in practice. The rate at which the cycle counter advances will
 depend on the implementation and operating environment. The execution
 environment should provide a means to determine the current rate
 (cycles/second) at which the cycle counter is incrementing.
-[TIP]
+[NOTE]
 ====
 RDCYCLE is intended to return the number of cycles executed by the
 processor core, not the hart. Precisely defining what is a "core" is
@@ -128,7 +128,7 @@ should be constant within a small error bound. The environment should
 provide a means to determine the accuracy of the clock (i.e., the
 maximum relative error between the nominal and actual real-time clock
 periods).
-[TIP]
+[NOTE]
 ====
 On some simple platforms, cycle count might represent a valid
 implementation of RDTIME, in which case RDTIME and RDCYCLE may return
@@ -141,7 +141,7 @@ bound should be set based on the requirements of the platform.
 
 The real-time clocks of all harts must be synchronized to within one
 tick of the real-time clock.
-[TIP]
+[NOTE]
 ====
 As with other architectural mandates, it suffices to appear "as if"
 harts are synchronized to within one tick of the real-time clock, i.e.,
@@ -154,7 +154,7 @@ hart from some arbitrary start point in the past. RDINSTRETH is only
 present when XLEN=32 and reads bits 63-32 of the same instruction
 counter. The underlying 64-bit counter should never overflow in
 practice.
-[TIP]
+[NOTE]
 ====
 Instructions that cause synchronous exceptions, including ECALL and
 EBREAK, are not considered to retire and hence do not increment the
@@ -181,7 +181,7 @@ hardware performance counters, `hpmcounter3-hpmcounter31`. When
 XLEN=32, the upper 32 bits of these performance counters are accessible
 via additional CSRs `hpmcounter3h- hpmcounter31h`. The Zihpm extension
 depends on the Zicsr extension.
-[TIP]
+[NOTE]
 ====
 In some applications, it is important to be able to read multiple
 counters at the same instant in time. When run under a multitasking
@@ -203,7 +203,7 @@ exception or may return a constant value.
 The execution environment should provide a means to determine the number
 and width of the implemented counters, and an interface to configure the
 events to be counted by each counter.
-[TIP]
+[NOTE]
 ====
 For execution environments implemented on RISC-V privileged platforms,
 the privileged architecture manual describes privileged CSRs controlling

docs/riscv-isa/src/machine.adoc

@@ -676,9 +676,11 @@ by the same write (For RV32, the `MDT` bit is in `mstatush` and the `MIE` bit in
 
 When a trap is to be taken into M-mode, if the `MDT` bit is currently 0, it is
 then set to 1, and the trap is delivered as expected. However, if `MDT` is
-already set to 1, then this is an _unexpected trap_. Additionally, when the
-Smrnmi extension is implemented, a trap that occurs when executing in M-mode
-with the `mnstatus.NMIE` set to 0 is an _unexpected trap_.
+already set to 1, then this is an _unexpected trap_. When the Smrnmi extension
+is implemented, a trap caused by an RNMI is not considered an _unexpected trap_
+irrespective of the state of the `MDT` bit. A trap caused by an RNMI does not
+set the `MDT` bit. However, a trap that occurs when executing in M-mode with
+`mnstatus.NMIE` set to 0 is an _unexpected trap_.
 
 In the event of a _unexpected trap_, the handling is as follows:
 
@@ -723,6 +725,9 @@ The `MRET` and `SRET` instructions, when executed in M-mode, set the `MDT` bit
 to 0. If the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set
 to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.
 
+The `MNRET` instruction, provided by the Smrnmi extension, sets the `MDT` bit to
+0 if the new privilege mode is not M. If it is U, VS, or VU, then `sstatus.SDT` is
+also set to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.
 endif::[]
 
 ifndef::archi-default,RVZsmdbltrp-true[]
@@ -2249,9 +2254,9 @@ ifdef::archi-default[]
 The `cycle`, `instret`, and `hpmcountern` CSRs are read-only shadows of
 `mcycle`, `minstret`, and `mhpmcounter n`, respectively. The `time` CSR
 is a read-only shadow of the memory-mapped `mtime` register.
-Analogously, on RV32I the `cycleh`, `instreth` and `hpmcounternh` CSRs
+Analogously, when XLEN=32, the `cycleh`, `instreth` and `hpmcounternh` CSRs
 are read-only shadows of `mcycleh`, `minstreth` and `mhpmcounternh`,
-respectively. On RV32I the `timeh` CSR is a read-only shadow of the
+respectively. When XLEN=32, the `timeh` CSR is a read-only shadow of the
 upper 32 bits of the memory-mapped `mtime` register, while `time`
 shadows only the lower 32 bits of `mtime`.
 endif::[]
@@ -3029,9 +3034,11 @@ the following rules apply to privilege modes that are less than M:
 * 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop.
 * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop.
 * The `pte.xwr=010b` encoding in VS/S-stage page tables becomes reserved.
-* The `henvcfg.SSE` and `senvcfg.SSE` fields will read as zero and are read-only.
 * `SSAMOSWAP.W/D` raises an illegal-instruction exception.
 
+When `menvcfg.SSE` is 0, the `henvcfg.SSE` and `senvcfg.SSE` fields are
+read-only zero.
+
 The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `menvcfg`.
 When `menvcfg.DTE` is zero, the implementation behaves as though Ssdbltrp is not
 implemented. When Ssdbltrp is not implemented `sstatus.SDT`, `vsstatus.SDT`, and
@@ -3207,6 +3214,14 @@ ifdef::archi-default,XLEN-32[]
 endif::[]
 
 
+ifdef::archi-default,RVU-true[]
+The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.
+When XLEN=32, the `timeh` CSR is a read-only shadow of the upper 32 bits of the
+memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of
+`mtime`.
+When `mtime` changes, it is guaranteed to be reflected in `time` and `timeh`
+eventually, but not necessarily immediately.
+endif::[]
 
 
 === Machine-Mode Privileged Instructions

docs/riscv-isa/src/priv-preface.adoc

@@ -6,10 +6,10 @@
 This document describes the RISC-V privileged architecture tailored for
 OpenHW Group {ohg-config}.
 
-[.big]*_Preface to Version 20240703_*
+[.big]*_Preface to Version 20240801_*
 
 This document describes the RISC-V privileged architecture. This
-release, version 20240703, contains the following versions of the RISC-V ISA
+release, version 20240801, contains the following versions of the RISC-V ISA
 modules:
 
 [%autowidth,float="center",align="center",cols="^,<,^",options="header",]
@@ -100,10 +100,10 @@ implemented.
 * Defined hardware error and software check exception codes.
 * Specified synchronization requirements when changing the PBMTE fields
 in `menvcfg` and `henvcfg`.
-* Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension.
+* Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension.
 * Relaxed behavior of some HINTs when MXLEN > XLEN.
 
-Finally, the following clarifications and document improvments have been made
+Finally, the following clarifications and document improvements have been made
 since the last document release:
 
 * Transliterated the document from LaTeX into AsciiDoc.
@@ -123,6 +123,7 @@ be set to a nonzero value but sometimes not.
 * Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.
 * Clarified that timer and count-overflow interrupts' arrival in
   interrupt-pending registers is not immediate.
+* Clarified that MXR affects only explicit memory accesses.
 
 [.big]*_Preface to Version 20211203_*
 

docs/riscv-isa/src/riscv-privileged.adoc

@@ -4,7 +4,7 @@ include::config.adoc[]
 = The RISC-V Instruction Set Manual for {ohg-config}: Volume II: Privileged Architecture
 include::../docs-resources/global-config.adoc[]
 :description: Volume II - Privileged Architecture
-:revnumber: 20240703
+:revnumber: 20240801
 //:revremark: Pre-release version
 //development: assume everything can change
 //stable: assume everything could change

docs/riscv-isa/src/riscv-unprivileged.adoc

@@ -4,7 +4,7 @@ include::config.adoc[]
 = The RISC-V Instruction Set Manual for {ohg-config}: Volume I - Unprivileged Architecture
 include::../docs-resources/global-config.adoc[]
 :description: Unprivileged Architecture
-:revnumber: 20240703
+:revnumber: 20240801
 //:revremark: Pre-release version
 :colophon:
 :preface-title: Preamble

docs/riscv-isa/src/rnmi.adoc

@@ -1,5 +1,5 @@
 [[rnmi]]
-== "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 0.5
+== "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0
 
 ifeval::[{RVZsmrnmi} == false]
 {ohg-config}: This extension is not supported.

docs/riscv-isa/src/supervisor.adoc

@@ -794,7 +794,7 @@ ifndef::archi-default,MTvalEn-true[]
 [{ohg-config}] The `stval` register is an MXLEN-bit read-only 0 register.
 endif::[]
 
-
+[[sec:senvcfg]]
 ==== Supervisor Environment Configuration (`senvcfg`) Register 
 
 The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as
@@ -1273,13 +1273,6 @@ integer register _rs2_, except for entries containing global mappings.
 If the value held in _rs1_ is not a valid virtual address, then the
 SFENCE.VMA instruction has no effect. No exception is raised in this
 case.
-
-When __rs2__≠``x0``, bits SXLEN-1:ASIDMAX of the value held
-in _rs2_ are reserved for future standard use. Until their use is
-defined by a standard extension, they should be zeroed by software and
-ignored by current implementations. Furthermore, if
-ASIDLEN<ASIDMAX, the implementation shall ignore bits
-ASIDMAX-1:ASIDLEN of the value held in _rs2_.
 endif::[]
 
 ifeval::[{note} == true]
@@ -1296,6 +1289,13 @@ in _rs1_ facilitates this type of simplification.
 endif::[]
 
 ifdef::archi-default[]
+When __rs2__&#8800;``x0``, bits SXLEN-1:ASIDMAX of the value held
+in _rs2_ are reserved for future standard use. Until their use is
+defined by a standard extension, they should be zeroed by software and
+ignored by current implementations. Furthermore, if
+ASIDLEN<ASIDMAX, the implementation shall ignore bits
+ASIDMAX-1:ASIDLEN of the value held in _rs2_.
+
 An implicit read of the memory-management data structures may return any
 translation for an address that was valid at any time since the most
 recent SFENCE.VMA that subsumes that address. The ordering implied by
@@ -1357,7 +1357,7 @@ Likewise, changes to `satp`.ASID take effect immediately.
 endif::[]
 
 ifeval::[{note} == true]
-[TIP]
+[NOTE]
 ====
 The following common situations typically require executing an
 SFENCE.VMA instruction:

docs/riscv-isa/src/zabha.adoc

@@ -1,5 +1,5 @@
 [[zabha]]
-== "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0.0
+== "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0
 
 ifeval::[{RVZabha} == false]
 {ohg-config}: This extension is not supported.