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Add Xilinx SRAMs

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Florian Zaruba 2017-11-13 20:07:58 +01:00
parent 2935c7ae92
commit 305e3c552a
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6 changed files with 108 additions and 18 deletions
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2
src/axi_mem_if

@ -1 +1 @@
Subproject commit 3440a861a67f3419d4dbac0d4fa884fa6c6d4745
Subproject commit dbf1f38dd677614394e8e0722c23463ac77176b5

1
src/mult.sv
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@ -440,6 +440,7 @@ module mul (
// Output MUX
always_comb begin
result_o = '0;
case (operator_q)
// MUL performs an XLEN-bit×XLEN-bit multiplication and places the lower XLEN bits in the destination register
MUL: result_o = mult_result[63:0];

32
src/util/gf22_sram.sv
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@ -1,6 +1,6 @@
// Author: Florian Zaruba, ETH Zurich
// Date: 13.10.2017
// Description: SRAM Behavioral Model
// Description: SRAM Model for GF22
//
// Copyright (C) 2017 ETH Zurich, University of Bologna
// All rights reserved.
@ -34,20 +34,20 @@ module sram #(
if (NUM_WORDS == 256) begin
if (DATA_WIDTH == 16) begin
IN22FDX_R1PH_NFHN_W00256B016M02C256 dirtyram (
.CLK ( clk_i ),
.CEN ( ~req_i ),
.RDWEN ( ~we_i ),
.AW ( addr_i[7:1] ),
.AC ( addr_i[0] ),
.D ( wdata_i ),
.BW ( be_i ),
.T_LOGIC ( 1'b0 ),
.MA_SAWL ( '0 ),
.MA_WL ( '0 ),
.MA_WRAS ( '0 ),
.MA_WRASD ( '0 ),
.Q ( rdata_o ),
.OBSV_CTL ( )
.CLK ( clk_i ),
.CEN ( ~req_i ),
.RDWEN ( ~we_i ),
.AW ( addr_i[7:1] ),
.AC ( addr_i[0] ),
.D ( wdata_i ),
.BW ( be_i ),
.T_LOGIC ( 1'b0 ),
.MA_SAWL ( '0 ),
.MA_WL ( '0 ),
.MA_WRAS ( '0 ),
.MA_WRASD ( '0 ),
.Q ( rdata_o ),
.OBSV_CTL ( )
);
end
@ -70,7 +70,7 @@ module sram #(
.MA_WRASD ( '0 ),
.Q ( rdata ),
.OBSV_CTL ( )
);
);
end
if (DATA_WIDTH == 128) begin

88
src/util/xilinx_sram.sv Executable file
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@ -0,0 +1,88 @@
// Author: Florian Zaruba, ETH Zurich
// Date: 13.11.2017
// Description: SRAM Model for Xilinx FPGA
//
// Copyright (C) 2017 ETH Zurich, University of Bologna
// All rights reserved.
//
// This code is under development and not yet released to the public.
// Until it is released, the code is under the copyright of ETH Zurich and
// the University of Bologna, and may contain confidential and/or unpublished
// work. Any reuse/redistribution is strictly forbidden without written
// permission from ETH Zurich.
//
// Bug fixes and contributions will eventually be released under the
// SolderPad open hardware license in the context of the PULP platform
// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
// University of Bologna.
module sram #(
int unsigned DATA_WIDTH = 64,
int unsigned NUM_WORDS = 1024
)(
input logic clk_i,
input logic req_i,
input logic we_i,
input logic [$clog2(NUM_WORDS)-1:0] addr_i,
input logic [DATA_WIDTH-1:0] wdata_i,
input logic [DATA_WIDTH-1:0] be_i,
output logic [DATA_WIDTH-1:0] rdata_o
);
generate
if (NUM_WORDS == 256) begin
// Dirty RAM
if (DATA_WIDTH == 16) begin
localparam NUM_WORDS = 2**8;
logic [NUM_WORDS-1:0][15:0] mem;
always_ff @(posedge clk_i) begin
// write
if (req_i && we_i) begin
for (int unsigned i = 0; i < 16; i++) begin
if (be_i[i])
mem[addr_i][i] <= wdata_i[i];
end
// read
end else if (req_i) begin
rdata_o <= mem[addr_i];
end
end
end
// Data RAM
if (DATA_WIDTH == 44) begin
logic [47:0] data_o;
assign rdata_o = data_o[43:0];
// this is actually 48 bits wide
xilinx_dcache_bank_tag_256x46 TAG_RAM (
.clka ( clk_i ),
.ena ( req_i ),
.wea ( {{be_i[40] & we_i}, {be_i[32] & we_i}, {be_i[24] & we_i}, {be_i[16] & we_i}, {be_i[8] & we_i}, {be_i[0] & we_i}} ),
.addra ( addr_i ),
.dina ( {4'b0, wdata_i} ),
.douta ( data_o )
);
end
// Data RAM
if (DATA_WIDTH == 128) begin
xilinx_dcache_bank_data_256x128 DATA_RAM (
.clka ( clk_i ),
.ena ( req_i ),
.wea ( {{be_i[15] & we_i}, {be_i[14] & we_i}, {be_i[13] & we_i}, {be_i[12] & we_i}, {be_i[11] & we_i}, {be_i[10] & we_i}, {be_i[9] & we_i}, {be_i[8] & we_i}, {be_i[7] & we_i}, {be_i[6] & we_i}, {be_i[5] & we_i}, {be_i[4] & we_i}, {be_i[3] & we_i}, {be_i[2] & we_i}, {be_i[1] & we_i}, {be_i[0] & we_i}}),
.addra ( addr_i ),
.dina ( wdata_i ),
.douta ( rdata_o )
);
end
end
endgenerate
endmodule

1
src_files.yml
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@ -64,4 +64,5 @@ riscv_regfile_fpga:
]
files: [
src/regfile_ff.sv,
src/util/xilinx_sram.sv,
]

2
tb

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Subproject commit a1394543cd537a1fd50fecf2455ddcea360cc133
Subproject commit bbf75b909548c228307acc0e657129e5f3faf154