mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 12:17:19 -04:00
Fix problems with ID width mismatches
This commit is contained in:
Florian Zaruba
parent
644bcd7eeb
commit
31a761e905
10 changed files with 42 additions and 58 deletions
2
.gitignore
vendored
2
.gitignore
vendored
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@ -22,4 +22,4 @@ build/
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*.vcd
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*.log
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*.out
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work-ver/*
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work-*/*
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@ -16,7 +16,7 @@
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*/
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package ariane_axi;
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// 4 is recommended by AXI standard, so lets stick to it
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// 4 is recommended by AXI standard, so lets stick to it, do not change
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localparam IdWidth = 4;
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localparam UserWidth = 1;
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localparam AddrWidth = 64;
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@ -20,9 +20,7 @@ import instruction_tracer_pkg::*;
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//pragma translate_on
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module ariane #(
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parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not
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parameter int unsigned AXI_ID_WIDTH = 10, // minimum 1
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parameter int unsigned AXI_USER_WIDTH = 1 // minimum 1
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parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000 // address on which to decide whether the request is cache-able or not
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)(
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input logic clk_i,
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input logic rst_ni,
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@ -19,9 +19,7 @@ import ariane_pkg::*;
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import std_cache_pkg::*;
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module miss_handler #(
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parameter int unsigned NR_PORTS = 3,
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parameter int unsigned AXI_ID_WIDTH = 10,
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parameter int unsigned AXI_USER_WIDTH = 1
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parameter int unsigned NR_PORTS = 3
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)(
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input logic clk_i,
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input logic rst_ni,
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@ -518,8 +516,8 @@ module miss_handler #(
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logic valid_bypass_fsm;
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logic [63:0] data_bypass_fsm;
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logic [$clog2(NR_PORTS)-1:0] id_fsm_bypass;
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logic [AXI_ID_WIDTH-1:0] id_bypass_fsm;
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logic [AXI_ID_WIDTH-1:0] gnt_id_bypass_fsm;
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logic [3:0] id_bypass_fsm;
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logic [3:0] gnt_id_bypass_fsm;
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arbiter #(
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.NR_PORTS ( NR_PORTS ),
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@ -552,8 +550,8 @@ module miss_handler #(
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);
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axi_adapter #(
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.DATA_WIDTH ( 64 ),
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.AXI_ID_WIDTH ( AXI_ID_WIDTH )
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.DATA_WIDTH ( 64 ),
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.AXI_ID_WIDTH ( 4 )
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) i_bypass_axi_adapter (
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.clk_i,
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.rst_ni,
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@ -580,8 +578,8 @@ module miss_handler #(
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// Cache Line AXI Refill
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// ----------------------
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axi_adapter #(
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.DATA_WIDTH ( DCACHE_LINE_WIDTH ),
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.AXI_ID_WIDTH ( AXI_ID_WIDTH )
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.DATA_WIDTH ( DCACHE_LINE_WIDTH ),
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.AXI_ID_WIDTH ( 4 )
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) i_miss_axi_adapter (
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.clk_i,
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.rst_ni,
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@ -642,13 +640,6 @@ module miss_handler #(
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miss_req_size [i] = miss_req.size;
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end
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end
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//pragma translate_off
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initial begin
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assert (AXI_ID_WIDTH >= $clog2(NR_PORTS)) else $fatal (1, "AXI ID Width needs to be larger than number of requestors");
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end
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//pragma translate_on
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endmodule
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// --------------
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@ -18,7 +18,6 @@ import ariane_pkg::*;
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import std_cache_pkg::*;
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module std_cache_subsystem #(
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parameter int unsigned AXI_ID_WIDTH = 10,
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parameter logic [63:0] CACHE_START_ADDR = 64'h4000_0000
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)(
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input logic clk_i,
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@ -78,7 +77,6 @@ module std_cache_subsystem #(
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// Port 1: Load Unit
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// Port 2: Store Unit
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std_nbdcache #(
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.AXI_ID_WIDTH ( AXI_ID_WIDTH ),
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.CACHE_START_ADDR ( CACHE_START_ADDR )
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) i_nbdcache (
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.clk_i,
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@ -191,9 +189,9 @@ module std_cache_subsystem #(
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);
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always_comb begin
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aw_enable_d = aw_enable_d;
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ar_enable_d = ar_enable_d;
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w_enable_d = w_enable_d;
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aw_enable_d = aw_enable_q;
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ar_enable_d = ar_enable_q;
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w_enable_d = w_enable_q;
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// freeze the arbiter
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if (aw_arbiter_valid) aw_enable_d = 1'b0;
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@ -218,22 +216,22 @@ module std_cache_subsystem #(
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end
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// Route responses based on ID
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// 0000 -> I$
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// 11[00|10|01] -> Bypass
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// 1111 -> D$
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// 0000 -> I$
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// 10[00|10|01|11] -> Bypass
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// 1111 -> D$
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// R Channel
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assign axi_resp_icache.r = axi_resp_i.r;
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assign axi_resp_bypass.r = axi_resp_i.r;
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assign axi_resp_data.r = axi_resp_i.r;
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logic [2:0] r_select;
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logic [1:0] r_select;
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always_comb begin
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r_select = 0;
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unique case (axi_resp_i.r.id)
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4'b0000: r_select = 2; // icache
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4'b1111: r_select = 0; // dcache
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4'b1100, 4'b1101, 4'b1110: r_select = 1; // bypass
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4'b1000, 4'b1001, 4'b1010, 4'b1011: r_select = 1; // bypass
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default: r_select = 0;
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endcase
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end
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@ -249,7 +247,7 @@ module std_cache_subsystem #(
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);
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// B Channel
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logic [2:0] b_select;
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logic [1:0] b_select;
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assign axi_resp_icache.b = axi_resp_i.b;
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assign axi_resp_bypass.b = axi_resp_i.b;
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@ -260,7 +258,7 @@ module std_cache_subsystem #(
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unique case (axi_resp_i.b.id)
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4'b0000: b_select = 2; // icache
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4'b1111: b_select = 0; // dcache
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4'b1100, 4'b1101, 4'b1110: b_select = 1; // bypass
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4'b1000, 4'b1001, 4'b1010, 4'b1011: b_select = 1; // bypass
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default: b_select = 0;
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endcase
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end
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@ -16,7 +16,6 @@ import ariane_pkg::*;
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import std_cache_pkg::*;
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module std_nbdcache #(
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parameter int unsigned AXI_ID_WIDTH = 10,
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parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000
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)(
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input logic clk_i, // Clock
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@ -128,7 +127,6 @@ module std_nbdcache #(
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// Miss Handling Unit
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// ------------------
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miss_handler #(
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.AXI_ID_WIDTH ( AXI_ID_WIDTH ),
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.NR_PORTS ( 3 )
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) i_miss_handler (
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.flush_i ( flush_i ),
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@ -1 +1 @@
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Subproject commit 36d047b8a0f0c5cc05cdc8ccd15c0149074d2d31
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Subproject commit 3b18d9ce9889fb140cd39c8d7c86b3a6cc68872e
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@ -1 +1 @@
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Subproject commit 3e925e169bd02ebf26e3d4ab65cd1832319cf580
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Subproject commit a3ba269c0fc6cfcee6f81e5d9af018a08e479d2b
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@ -13,15 +13,15 @@
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// Date: 15.08.2018
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// Description: SRAM wrapper for FPGA (requires the fpga-support submodule)
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//
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// Note: the wrapped module contains two different implementations for
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// ALTERA and XILINX tools, since these follow different coding styles for
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// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or
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// Note: the wrapped module contains two different implementations for
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// ALTERA and XILINX tools, since these follow different coding styles for
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// inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or
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// `FPGA_TARGET_ALTERA in your build environment (default is ALTERA)
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module sram #(
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parameter DATA_WIDTH = 64,
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parameter NUM_WORDS = 1024,
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parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2)
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parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2)
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)(
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input logic clk_i,
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input logic rst_ni,
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@ -52,23 +52,24 @@ end
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genvar k;
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generate
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for (k = 0; k<(DATA_WIDTH+63)/64; k++) begin
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for (k = 0; k<(DATA_WIDTH+63)/64; k++) begin
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// unused byte-enable segments (8bits) are culled by the tool
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SyncSpRamBeNx64 #(
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.ADDR_WIDTH($clog2(NUM_WORDS)),
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.DATA_DEPTH(NUM_WORDS),
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.OUT_REGS (0)
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.DATA_DEPTH(NUM_WORDS),
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.OUT_REGS (0),
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.SIM_INIT (2)
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) i_ram (
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.Clk_CI ( clk_i ),
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.Rst_RBI ( rst_ni ),
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.CSel_SI ( req_i ),
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.WrEn_SI ( we_i ),
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.BEn_SI ( be_aligned[k*8 +: 8] ),
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.WrData_DI ( wdata_aligned[k*64 +: 64] ),
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.Addr_DI ( addr_i ),
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.WrData_DI ( wdata_aligned[k*64 +: 64] ),
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.Addr_DI ( addr_i ),
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.RdData_DO ( rdata_aligned[k*64 +: 64] )
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);
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end
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);
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end
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endgenerate
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endmodule : sram
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@ -15,15 +15,15 @@
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module ariane_testharness #(
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parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000, // address on which to decide whether the request is cache-able or not
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parameter int unsigned AXI_ID_WIDTH = 10,
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parameter int unsigned AXI_ID_WIDTH = 4,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_ADDRESS_WIDTH = 64,
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parameter int unsigned AXI_DATA_WIDTH = 64,
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parameter int unsigned NUM_WORDS = 2**24 // memory size
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)(
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input logic clk_i,
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input logic rst_ni,
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output logic [31:0] exit_o
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input logic clk_i,
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input logic rst_ni,
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output logic [31:0] exit_o
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);
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// disable test-enable
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@ -70,8 +70,8 @@ module ariane_testharness #(
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assign test_en = 1'b0;
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assign ndmreset_n = ~ndmreset ;
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localparam NB_SLAVE = 4;
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localparam NB_MASTER = 2;
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localparam NB_SLAVE = 2;
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localparam NB_MASTER = 4;
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localparam AXI_ID_WIDTH_SLAVES = AXI_ID_WIDTH + $clog2(NB_SLAVE);
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@ -322,9 +322,7 @@ module ariane_testharness #(
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ariane_axi::resp_t axi_ariane_resp;
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ariane #(
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.CACHE_START_ADDR ( CACHE_START_ADDR ),
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.AXI_ID_WIDTH ( AXI_ID_WIDTH ),
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.AXI_USER_WIDTH ( AXI_USER_WIDTH )
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.CACHE_START_ADDR ( CACHE_START_ADDR )
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) i_ariane (
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.clk_i ( clk_i ),
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.rst_ni ( ndmreset_n ),
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