github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-19 03:44:46 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Parametrization step 2 (#1908)

Browse source
This commit is contained in:
Côme 2024-03-08 22:53:42 +01:00 • committed by GitHub
parent bb2c6bd41f
commit 32a3cd56ee
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
79 changed files with 1004 additions and 608 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
common/local/util/ex_trace_item.svh
View file

@ -13,7 +13,10 @@
// Description: Instruction tracer single exception item
`ifndef VERILATOR
class ex_trace_item;
class ex_trace_item #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
);
// contains a human readable form of the cause value
string cause_s;
logic [63:0] cause;

14
common/local/util/instr_trace_item.svh
View file

@ -22,11 +22,15 @@ function string printPCexpr(input logic [63:0] imm);
end
endfunction
class instr_trace_item;
class instr_trace_item #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bp_resolve_t = logic,
parameter type scoreboard_entry_t = logic
);
// keep a couple of general purpose information inside this instruction item
time simtime;
longint unsigned cycle;
ariane_pkg::scoreboard_entry_t sbe;
scoreboard_entry_t sbe;
logic [31:0] pc;
logic [31:0] instr;
logic [63:0] gp_reg_file [32];
@ -39,13 +43,13 @@ class instr_trace_item;
logic [63:0] result;
logic [riscv::PLEN-1:0] paddr;
string priv_lvl;
ariane_pkg::bp_resolve_t bp;
bp_resolve_t bp;
logic [4:0] rs1, rs2, rs3, rd;
// constructor creating a new instruction trace item, e.g.: a single instruction with all relevant information
function new (time simtime, longint unsigned cycle, ariane_pkg::scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32],
logic [63:0] fp_reg_file [32], logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp);
function new (time simtime, longint unsigned cycle, scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32],
logic [63:0] fp_reg_file [32], logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp);
this.simtime = simtime;
this.cycle = cycle;
this.pc = sbe.pc;

34
common/local/util/instr_tracer.sv
View file

@ -17,8 +17,12 @@
`include "ex_trace_item.svh"
`include "instr_trace_item.svh"
module instr_tracer (
instr_tracer_if tracer_if,
module instr_tracer #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bp_resolve_t = logic,
parameter type scoreboard_entry_t = logic
)(
instr_tracer_if tracer_if,
input logic[riscv::XLEN-1:0] hart_id_i
);
@ -27,10 +31,10 @@ module instr_tracer (
// keep the issued instructions in a queue
logic [31:0] issue_queue [$];
// issue scoreboard entries
ariane_pkg::scoreboard_entry_t issue_sbe_queue [$];
ariane_pkg::scoreboard_entry_t issue_sbe;
scoreboard_entry_t issue_sbe_queue [$];
scoreboard_entry_t issue_sbe;
// store resolved branches, get (mis-)predictions
ariane_pkg::bp_resolve_t bp [$];
bp_resolve_t bp [$];
// shadow copy of the register files
logic [63:0] gp_reg_file [32];
logic [63:0] fp_reg_file [32];
@ -55,13 +59,13 @@ module instr_tracer (
task trace();
automatic logic [31:0] decode_instruction, issue_instruction, issue_commit_instruction;
automatic ariane_pkg::scoreboard_entry_t commit_instruction;
automatic scoreboard_entry_t commit_instruction;
// initialize register 0
gp_reg_file = '{default:0};
fp_reg_file = '{default:0};
forever begin
automatic ariane_pkg::bp_resolve_t bp_instruction = '0;
automatic bp_resolve_t bp_instruction = '0;
// new cycle, we are only interested if reset is de-asserted
@(tracer_if.pck) if (tracer_if.pck.rstn !== 1'b1) begin
flush();
@ -88,7 +92,7 @@ module instr_tracer (
issue_instruction = decode_queue.pop_front();
issue_queue.push_back(issue_instruction);
// also save the scoreboard entry to a separate issue queue
issue_sbe_queue.push_back(ariane_pkg::scoreboard_entry_t'(tracer_if.pck.issue_sbe));
issue_sbe_queue.push_back(scoreboard_entry_t'(tracer_if.pck.issue_sbe));
end
// --------------------
@ -113,7 +117,7 @@ module instr_tracer (
// we are committing an instruction
for (int i = 0; i < 2; i++) begin
if (tracer_if.pck.commit_ack[i]) begin
commit_instruction = ariane_pkg::scoreboard_entry_t'(tracer_if.pck.commit_instr[i]);
commit_instruction = scoreboard_entry_t'(tracer_if.pck.commit_instr[i]);
issue_commit_instruction = issue_queue.pop_front();
issue_sbe = issue_sbe_queue.pop_front();
// check if the instruction retiring is a load or store, get the physical address accordingly
@ -186,8 +190,12 @@ module instr_tracer (
bp = {};
endfunction
function void printInstr(ariane_pkg::scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp);
automatic instr_trace_item iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp);
function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp);
automatic instr_trace_item #(
.CVA6Cfg(CVA6Cfg),
.bp_resolve_t(bp_resolve_t),
.scoreboard_entry_t(scoreboard_entry_t)
) iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp);
// print instruction to console
automatic string print_instr = iti.printInstr();
if (ariane_pkg::ENABLE_SPIKE_COMMIT_LOG && !debug_mode) begin
@ -197,7 +205,9 @@ module instr_tracer (
endfunction
function void printException(logic [riscv::VLEN-1:0] pc, logic [63:0] cause, logic [63:0] tval);
automatic ex_trace_item eti = new (pc, cause, tval);
automatic ex_trace_item #(
.CVA6Cfg(CVA6Cfg)
) eti = new (pc, cause, tval);
automatic string print_ex = eti.printException();
$fwrite(f, {print_ex, "\n"});
endfunction

15
common/local/util/instr_tracer_if.sv
View file

@ -15,7 +15,12 @@
`ifndef VERILATOR
`ifndef INSTR_TRACER_IF_SV
`define INSTR_TRACER_IF_SV
interface instr_tracer_if (
interface instr_tracer_if #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bp_resolve_t = logic,
parameter type exception_t = logic,
parameter type scoreboard_entry_t = logic
)(
input clk
);
@ -28,14 +33,14 @@ interface instr_tracer_if (
logic fetch_ack;
// Issue stage
logic issue_ack; // issue acknowledged
ariane_pkg::scoreboard_entry_t issue_sbe; // issue scoreboard entry
scoreboard_entry_t issue_sbe; // issue scoreboard entry
// WB stage
logic [1:0][4:0] waddr;
logic [1:0][63:0] wdata;
logic [1:0] we_gpr;
logic [1:0] we_fpr;
// commit stage
ariane_pkg::scoreboard_entry_t [1:0] commit_instr; // commit instruction
scoreboard_entry_t [1:0] commit_instr; // commit instruction
logic [1:0] commit_ack;
// address translation
// stores
@ -46,9 +51,9 @@ interface instr_tracer_if (
logic ld_kill;
logic [riscv::PLEN-1:0] ld_paddr;
// misprediction
ariane_pkg::bp_resolve_t resolve_branch;
bp_resolve_t resolve_branch;
// exceptions
ariane_pkg::exception_t exception;
exception_t exception;
// current privilege level
riscv::priv_lvl_t priv_lvl;
logic debug_mode;

1
core/Flist.cva6
View file

@ -67,7 +67,6 @@ ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
${CVA6_REPO_DIR}/core/include/acc_pkg.sv
${CVA6_REPO_DIR}/core/include/build_config_pkg.sv
//CVXIF

53
core/acc_dispatcher.sv
View file

@ -17,11 +17,44 @@ module acc_dispatcher
import ariane_pkg::*;
import riscv::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type acc_req_t = acc_pkg::accelerator_req_t,
parameter type acc_resp_t = acc_pkg::accelerator_resp_t,
parameter type acc_cfg_t = logic,
parameter acc_cfg_t AccCfg = '0
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type exception_t = logic,
parameter type fu_data_t = logic,
parameter type scoreboard_entry_t = logic,
localparam type accelerator_req_t = struct packed {
logic req_valid;
logic resp_ready;
riscv::instruction_t insn;
riscv::xlen_t rs1;
riscv::xlen_t rs2;
fpnew_pkg::roundmode_e frm;
logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
logic store_pending;
// Invalidation interface
logic acc_cons_en;
logic inval_ready;
},
parameter type acc_req_t = accelerator_req_t,
parameter type acc_resp_t = struct packed {
logic req_ready;
logic resp_valid;
riscv::xlen_t result;
logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
logic error;
// Metadata
logic store_pending;
logic store_complete;
logic load_complete;
logic [4:0] fflags;
logic fflags_valid;
// Invalidation interface
logic inval_valid;
logic [63:0] inval_addr;
},
parameter type acc_cfg_t = logic,
parameter acc_cfg_t AccCfg = '0
) (
input logic clk_i,
input logic rst_ni,
@ -190,13 +223,13 @@ module acc_dispatcher
* Accelerator request *
*************************/
acc_pkg::accelerator_req_t acc_req;
logic acc_req_valid;
logic acc_req_ready;
accelerator_req_t acc_req;
logic acc_req_valid;
logic acc_req_ready;
acc_pkg::accelerator_req_t acc_req_int;
accelerator_req_t acc_req_int;
fall_through_register #(
.T(acc_pkg::accelerator_req_t)
.T(accelerator_req_t)
) i_accelerator_req_register (
.clk_i (clk_i),
.rst_ni (rst_ni),

3
core/alu.sv
View file

@ -21,7 +21,8 @@
module alu
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type fu_data_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,

14
core/branch_unit.sv
View file

@ -13,7 +13,11 @@
// Description: Branch target calculation and comparison
module branch_unit #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bp_resolve_t = logic,
parameter type branchpredict_sbe_t = logic,
parameter type exception_t = logic,
parameter type fu_data_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
@ -22,7 +26,7 @@ module branch_unit #(
// Debug mode state - CSR_REGFILE
input logic debug_mode_i,
// FU data needed to execute instruction - ISSUE_STAGE
input ariane_pkg::fu_data_t fu_data_i,
input fu_data_t fu_data_i,
// Instruction PC - ISSUE_STAGE
input logic [riscv::VLEN-1:0] pc_i,
// Instruction is compressed - ISSUE_STAGE
@ -36,13 +40,13 @@ module branch_unit #(
// Brach unit result - ISSUE_STAGE
output logic [riscv::VLEN-1:0] branch_result_o,
// Information of branch prediction - ISSUE_STAGE
input ariane_pkg::branchpredict_sbe_t branch_predict_i,
input branchpredict_sbe_t branch_predict_i,
// Signaling that we resolved the branch - ISSUE_STAGE
output ariane_pkg::bp_resolve_t resolved_branch_o,
output bp_resolve_t resolved_branch_o,
// Branch is resolved, new entries can be accepted by scoreboard - ID_STAGE
output logic resolve_branch_o,
// Branch exception out - TO_BE_COMPLETED
output ariane_pkg::exception_t branch_exception_o
output exception_t branch_exception_o
);
logic [riscv::VLEN-1:0] target_address;
logic [riscv::VLEN-1:0] next_pc;

6
core/cache_subsystem/cache_ctrl.sv
View file

@ -22,7 +22,11 @@ module cache_ctrl
import ariane_pkg::*;
import std_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type cache_line_t = logic,
parameter type cl_be_t = logic,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

14
core/cache_subsystem/cva6_hpdcache_if_adapter.sv
View file

@ -15,8 +15,10 @@ module cva6_hpdcache_if_adapter
// Parameters
// {{{
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter bit is_load_port = 1'b1
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter bit is_load_port = 1'b1
)
// }}}
@ -31,10 +33,10 @@ module cva6_hpdcache_if_adapter
input hpdcache_pkg::hpdcache_req_sid_t hpdcache_req_sid_i,
// Request/response ports from/to the CVA6 core
input ariane_pkg::dcache_req_i_t cva6_req_i,
output ariane_pkg::dcache_req_o_t cva6_req_o,
input ariane_pkg::amo_req_t cva6_amo_req_i,
output ariane_pkg::amo_resp_t cva6_amo_resp_o,
input dcache_req_i_t cva6_req_i,
output dcache_req_o_t cva6_req_o,
input ariane_pkg::amo_req_t cva6_amo_req_i,
output ariane_pkg::amo_resp_t cva6_amo_resp_o,
// Request port to the L1 Dcache
output logic hpdcache_req_valid_o,

60
core/cache_subsystem/cva6_hpdcache_subsystem.sv
View file

@ -17,6 +17,14 @@ module cva6_hpdcache_subsystem
// {{{
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter type icache_req_t = logic,
parameter type icache_rtrn_t = logic,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter int NumPorts = 4,
parameter int NrHwPrefetchers = 4,
// AXI types
@ -44,11 +52,11 @@ module cva6_hpdcache_subsystem
input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together
output logic icache_miss_o, // to performance counter
// address translation requests
input ariane_pkg::icache_areq_t icache_areq_i, // to/from frontend
output ariane_pkg::icache_arsp_t icache_areq_o,
input icache_areq_t icache_areq_i, // to/from frontend
output icache_arsp_t icache_areq_o,
// data requests
input ariane_pkg::icache_dreq_t icache_dreq_i, // to/from frontend
output ariane_pkg::icache_drsp_t icache_dreq_o,
input icache_dreq_t icache_dreq_i, // to/from frontend
output icache_drsp_t icache_dreq_o,
// }}}
// D$
@ -60,17 +68,17 @@ module cva6_hpdcache_subsystem
output logic dcache_miss_o, // we missed on a ld/st
// AMO interface
input ariane_pkg::amo_req_t dcache_amo_req_i, // from LSU
output ariane_pkg::amo_resp_t dcache_amo_resp_o, // to LSU
input ariane_pkg::amo_req_t dcache_amo_req_i, // from LSU
output ariane_pkg::amo_resp_t dcache_amo_resp_o, // to LSU
// CMO interface
input cmo_req_t dcache_cmo_req_i, // from CMO FU
output cmo_rsp_t dcache_cmo_resp_o, // to CMO FU
input cmo_req_t dcache_cmo_req_i, // from CMO FU
output cmo_rsp_t dcache_cmo_resp_o, // to CMO FU
// Request ports
input ariane_pkg::dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // from LSU
output ariane_pkg::dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to LSU
input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // from LSU
output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to LSU
// Write Buffer status
output logic wbuffer_empty_o,
output logic wbuffer_not_ni_o,
output logic wbuffer_empty_o,
output logic wbuffer_not_ni_o,
// Hardware memory prefetcher configuration
input logic [NrHwPrefetchers-1:0] hwpf_base_set_i,
@ -96,16 +104,22 @@ module cva6_hpdcache_subsystem
// I$ instantiation
// {{{
logic icache_miss_valid, icache_miss_ready;
wt_cache_pkg::icache_req_t icache_miss;
icache_req_t icache_miss;
logic icache_miss_resp_valid;
wt_cache_pkg::icache_rtrn_t icache_miss_resp;
icache_rtrn_t icache_miss_resp;
localparam int ICACHE_RDTXID = 1 << (ariane_pkg::MEM_TID_WIDTH - 1);
cva6_icache #(
.CVA6Cfg(CVA6Cfg),
.RdTxId (ICACHE_RDTXID)
.icache_areq_t(icache_areq_t),
.icache_arsp_t(icache_arsp_t),
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t),
.icache_req_t(icache_req_t),
.icache_rtrn_t(icache_rtrn_t),
.RdTxId(ICACHE_RDTXID)
) i_cva6_icache (
.clk_i (clk_i),
.rst_ni (rst_ni),
@ -212,14 +226,16 @@ module cva6_hpdcache_subsystem
hwpf_stride_pkg::hwpf_stride_throttle_t [NrHwPrefetchers-1:0] hwpf_throttle_out;
generate
ariane_pkg::dcache_req_i_t dcache_req_ports[HPDCACHE_NREQUESTERS-1:0];
dcache_req_i_t dcache_req_ports[HPDCACHE_NREQUESTERS-1:0];
for (genvar r = 0; r < (NumPorts - 1); r++) begin : cva6_hpdcache_load_if_adapter_gen
assign dcache_req_ports[r] = dcache_req_ports_i[r];
cva6_hpdcache_if_adapter #(
.CVA6Cfg (CVA6Cfg),
.is_load_port(1'b1)
.CVA6Cfg (CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.is_load_port (1'b1)
) i_cva6_hpdcache_load_if_adapter (
.clk_i,
.rst_ni,
@ -244,8 +260,10 @@ module cva6_hpdcache_subsystem
end
cva6_hpdcache_if_adapter #(
.CVA6Cfg (CVA6Cfg),
.is_load_port(1'b0)
.CVA6Cfg (CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.is_load_port (1'b0)
) i_cva6_hpdcache_store_if_adapter (
.clk_i,
.rst_ni,
@ -480,6 +498,8 @@ module cva6_hpdcache_subsystem
.hpdcache_mem_req_w_t (hpdcache_mem_req_w_t),
.hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t),
.hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t),
.icache_req_t (icache_req_t),
.icache_rtrn_t (icache_rtrn_t),
.AxiAddrWidth (CVA6Cfg.AxiAddrWidth),
.AxiDataWidth (CVA6Cfg.AxiDataWidth),

14
core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
View file

@ -22,6 +22,8 @@ module cva6_hpdcache_subsystem_axi_arbiter
parameter type hpdcache_mem_req_w_t = logic,
parameter type hpdcache_mem_resp_r_t = logic,
parameter type hpdcache_mem_resp_w_t = logic,
parameter type icache_req_t = logic,
parameter type icache_rtrn_t = logic,
parameter int unsigned AxiAddrWidth = 1,
parameter int unsigned AxiDataWidth = 1,
@ -47,13 +49,13 @@ module cva6_hpdcache_subsystem_axi_arbiter
// Interfaces from/to I$
// {{{
input logic icache_miss_valid_i,
output logic icache_miss_ready_o,
input wt_cache_pkg::icache_req_t icache_miss_i,
input hpdcache_mem_id_t icache_miss_id_i,
input logic icache_miss_valid_i,
output logic icache_miss_ready_o,
input icache_req_t icache_miss_i,
input hpdcache_mem_id_t icache_miss_id_i,
output logic icache_miss_resp_valid_o,
output wt_cache_pkg::icache_rtrn_t icache_miss_resp_o,
output logic icache_miss_resp_valid_o,
output icache_rtrn_t icache_miss_resp_o,
// }}}
// Interfaces from/to D$

6
core/cache_subsystem/cva6_icache.sv
View file

@ -30,6 +30,12 @@ module cva6_icache
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter type icache_req_t = logic,
parameter type icache_rtrn_t = logic,
/// ID to be used for read transactions
parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0
) (

14
core/cache_subsystem/cva6_icache_axi_wrapper.sv
View file

@ -18,6 +18,12 @@ module cva6_icache_axi_wrapper
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter type icache_req_t = logic,
parameter type icache_rtrn_t = logic,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
) (
@ -102,7 +108,13 @@ module cva6_icache_axi_wrapper
cva6_icache #(
// use ID 0 for icache reads
.CVA6Cfg(CVA6Cfg),
.RdTxId (0)
.icache_areq_t(icache_areq_t),
.icache_arsp_t(icache_arsp_t),
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t),
.icache_req_t(icache_req_t),
.icache_rtrn_t(icache_rtrn_t),
.RdTxId(0)
) i_cva6_icache (
.clk_i (clk_i),
.rst_ni (rst_ni),

10
core/cache_subsystem/miss_handler.sv
View file

@ -20,10 +20,12 @@ module miss_handler
import ariane_pkg::*;
import std_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned NR_PORTS = 4,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned NR_PORTS = 4,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic,
parameter type cache_line_t = logic,
parameter type cl_be_t = logic
) (
input logic clk_i,
input logic rst_ni,

22
core/cache_subsystem/std_cache_subsystem.sv
View file

@ -20,6 +20,14 @@ module std_cache_subsystem
import std_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter type icache_req_t = logic,
parameter type icache_rtrn_t = logic,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter int unsigned NumPorts = 4,
parameter type axi_ar_chan_t = logic,
parameter type axi_aw_chan_t = logic,
@ -68,7 +76,13 @@ module std_cache_subsystem
axi_rsp_t axi_resp_data;
cva6_icache_axi_wrapper #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.icache_areq_t(icache_areq_t),
.icache_arsp_t(icache_arsp_t),
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t),
.icache_req_t(icache_req_t),
.icache_rtrn_t(icache_rtrn_t),
.axi_req_t(axi_req_t),
.axi_rsp_t(axi_rsp_t)
) i_cva6_icache_axi_wrapper (
@ -92,8 +106,10 @@ module std_cache_subsystem
// Port 2: Accelerator
// Port 3: Store Unit
std_nbdcache #(
.CVA6Cfg (CVA6Cfg),
.NumPorts (NumPorts),
.CVA6Cfg(CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.NumPorts(NumPorts),
.axi_req_t(axi_req_t),
.axi_rsp_t(axi_rsp_t)
) i_nbdcache (

30
core/cache_subsystem/std_nbdcache.sv
View file

@ -18,6 +18,8 @@ module std_nbdcache
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter int unsigned NumPorts = 4,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
@ -44,6 +46,18 @@ module std_nbdcache
import std_cache_pkg::*;
localparam type cache_line_t = struct packed {
logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag; // tag array
logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // data array
logic valid; // state array
logic dirty; // state array
};
localparam type cl_be_t = struct packed {
logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array
logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] vldrty; // bit enable into state array (valid for a pair of dirty/valid bits)
};
// -------------------------------
// Controller <-> Arbiter
// -------------------------------
@ -95,7 +109,11 @@ module std_nbdcache
generate
for (genvar i = 0; i < NumPorts; i++) begin : master_ports
cache_ctrl #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.cache_line_t(cache_line_t),
.cl_be_t(cl_be_t),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t)
) i_cache_ctrl (
.bypass_i (~enable_i),
.busy_o (busy[i]),
@ -134,10 +152,12 @@ module std_nbdcache
// Miss Handling Unit
// ------------------
miss_handler #(
.CVA6Cfg (CVA6Cfg),
.NR_PORTS (NumPorts),
.CVA6Cfg(CVA6Cfg),
.NR_PORTS(NumPorts),
.axi_req_t(axi_req_t),
.axi_rsp_t(axi_rsp_t)
.axi_rsp_t(axi_rsp_t),
.cache_line_t(cache_line_t),
.cl_be_t(cl_be_t)
) i_miss_handler (
.flush_i (flush_i),
.busy_i (|busy),
@ -248,6 +268,8 @@ module std_nbdcache
.CVA6Cfg (CVA6Cfg),
.NR_PORTS (NumPorts + 1),
.ADDR_WIDTH (DCACHE_INDEX_WIDTH),
.l_data_t (cache_line_t),
.l_be_t (cl_be_t),
.DCACHE_SET_ASSOC(DCACHE_SET_ASSOC)
) i_tag_cmp (
.req_i (req),

4
core/cache_subsystem/tag_cmp.sv
View file

@ -19,8 +19,8 @@ module tag_cmp #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned NR_PORTS = 3,
parameter int unsigned ADDR_WIDTH = 64,
parameter type l_data_t = std_cache_pkg::cache_line_t,
parameter type l_be_t = std_cache_pkg::cl_be_t,
parameter type l_data_t = logic,
parameter type l_be_t = logic,
parameter int unsigned DCACHE_SET_ASSOC = 8
) (
input logic clk_i,

11
core/cache_subsystem/wt_axi_adapter.sv
View file

@ -20,9 +20,14 @@ module wt_axi_adapter
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned ReqFifoDepth = 2,
parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX,
parameter int unsigned MetaFifoDepth = CVA6Cfg.DCACHE_MAX_TX,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
parameter type axi_rsp_t = logic,
parameter type dcache_req_t = logic,
parameter type dcache_rtrn_t = logic,
parameter type dcache_inval_t = logic,
parameter type icache_req_t = logic,
parameter type icache_rtrn_t = logic
) (
input logic clk_i,
input logic rst_ni,
@ -438,7 +443,7 @@ module wt_axi_adapter
logic [DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:0][CVA6Cfg.AxiDataWidth-1:0]
dcache_rd_shift_d, dcache_rd_shift_q;
wt_cache_pkg::dcache_in_t dcache_rtrn_type_d, dcache_rtrn_type_q;
wt_cache_pkg::dcache_inval_t dcache_rtrn_inv_d, dcache_rtrn_inv_q;
dcache_inval_t dcache_rtrn_inv_d, dcache_rtrn_inv_q;
logic dcache_sc_rtrn, axi_rd_last;
always_comb begin : p_axi_rtrn_shift

79
core/cache_subsystem/wt_cache_subsystem.sv
View file

@ -23,10 +23,18 @@ module wt_cache_subsystem
import ariane_pkg::*;
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned NumPorts = 4,
parameter type noc_req_t = logic,
parameter type noc_resp_t = logic
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type icache_req_t = logic,
parameter type icache_rtrn_t = logic,
parameter int unsigned NumPorts = 4,
parameter type noc_req_t = logic,
parameter type noc_resp_t = logic
) (
input logic clk_i,
input logic rst_ni,
@ -67,19 +75,53 @@ module wt_cache_subsystem
// TODO: interrupt interface
);
// dcache interface
localparam type dcache_inval_t = struct packed {
logic vld; // invalidate only affected way
logic all; // invalidate all ways
logic [ariane_pkg::DCACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate
logic [L15_WAY_WIDTH-1:0] way; // way to invalidate
};
localparam type dcache_req_t = struct packed {
wt_cache_pkg::dcache_out_t rtype; // see definitions above
logic [2:0] size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte)
logic [L1D_WAY_WIDTH-1:0] way; // way to replace
logic [riscv::PLEN-1:0] paddr; // physical address
riscv::xlen_t data; // word width of processor (no block stores at the moment)
logic [ariane_pkg::DATA_USER_WIDTH-1:0] user; // user width of processor (no block stores at the moment)
logic nc; // noncacheable
logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
ariane_pkg::amo_t amo_op; // amo opcode
};
localparam type dcache_rtrn_t = struct packed {
wt_cache_pkg::dcache_in_t rtype; // see definitions above
logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // full cache line width
logic [ariane_pkg::DCACHE_USER_LINE_WIDTH-1:0] user; // user bits
dcache_inval_t inv; // invalidation vector
logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
};
logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld;
wt_cache_pkg::icache_req_t icache_adapter;
wt_cache_pkg::icache_rtrn_t adapter_icache;
icache_req_t icache_adapter;
icache_rtrn_t adapter_icache;
logic dcache_adapter_data_req, adapter_dcache_data_ack, adapter_dcache_rtrn_vld;
wt_cache_pkg::dcache_req_t dcache_adapter;
wt_cache_pkg::dcache_rtrn_t adapter_dcache;
dcache_req_t dcache_adapter;
dcache_rtrn_t adapter_dcache;
cva6_icache #(
// use ID 0 for icache reads
.CVA6Cfg(CVA6Cfg),
.RdTxId (0)
.icache_areq_t(icache_areq_t),
.icache_arsp_t(icache_arsp_t),
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t),
.icache_req_t(icache_req_t),
.icache_rtrn_t(icache_rtrn_t),
.RdTxId(0)
) i_cva6_icache (
.clk_i (clk_i),
.rst_ni (rst_ni),
@ -103,7 +145,11 @@ module wt_cache_subsystem
// they have equal prio and are RR arbited
// Port 2 is write only and goes into the merging write buffer
wt_dcache #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.dcache_req_t(dcache_req_t),
.dcache_rtrn_t(dcache_rtrn_t),
// use ID 1 for dcache reads and amos. note that the writebuffer
// uses all IDs up to DCACHE_MAX_TX-1 for write transactions.
.RdAmoTxId(1)
@ -137,6 +183,10 @@ module wt_cache_subsystem
`ifdef PITON_ARIANE
wt_l15_adapter #(
.CVA6Cfg(CVA6Cfg),
.dcache_req_t(dcache_req_t),
.dcache_rtrn_t(dcache_rtrn_t),
.icache_req_t(icache_req_t),
.icache_rtrn_t(icache_rtrn_t)
) i_adapter (
.clk_i (clk_i),
.rst_ni (rst_ni),
@ -155,9 +205,14 @@ module wt_cache_subsystem
);
`else
wt_axi_adapter #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.axi_req_t(noc_req_t),
.axi_rsp_t(noc_resp_t)
.axi_rsp_t(noc_resp_t),
.dcache_req_t(dcache_req_t),
.dcache_rtrn_t(dcache_rtrn_t),
.dcache_inval_t(dcache_inval_t),
.icache_req_t(icache_req_t),
.icache_rtrn_t(icache_rtrn_t)
) i_adapter (
.clk_i (clk_i),
.rst_ni (rst_ni),

39
core/cache_subsystem/wt_dcache.sv
View file

@ -18,6 +18,10 @@ module wt_dcache
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type dcache_req_t = logic,
parameter type dcache_rtrn_t = logic,
parameter int unsigned NumPorts = 4, // number of miss ports
// ID to be used for read and AMO transactions.
// note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions
@ -51,6 +55,17 @@ module wt_dcache
output dcache_req_t mem_data_o
);
localparam type wbuffer_t = struct packed {
logic [ariane_pkg::DCACHE_TAG_WIDTH+(ariane_pkg::DCACHE_INDEX_WIDTH-riscv::XLEN_ALIGN_BYTES)-1:0] wtag;
riscv::xlen_t data;
logic [ariane_pkg::DCACHE_USER_WIDTH-1:0] user;
logic [(riscv::XLEN/8)-1:0] dirty; // byte is dirty
logic [(riscv::XLEN/8)-1:0] valid; // byte is valid
logic [(riscv::XLEN/8)-1:0] txblock; // byte is part of transaction in-flight
logic checked; // if cache state of this word has been checked
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] hit_oh; // valid way in the cache
};
// miss unit <-> read controllers
logic cache_en;
@ -101,8 +116,8 @@ module wt_dcache
logic [ DCACHE_SET_ASSOC-1:0] rd_hit_oh;
// miss unit <-> wbuffer
logic [ DCACHE_MAX_TX-1:0][ riscv::PLEN-1:0] tx_paddr;
logic [ DCACHE_MAX_TX-1:0] tx_vld;
logic [ CVA6Cfg.DCACHE_MAX_TX-1:0][ riscv::PLEN-1:0] tx_paddr;
logic [ CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld;
// wbuffer <-> memory
wbuffer_t [ DCACHE_WBUF_DEPTH-1:0] wbuffer_data;
@ -113,8 +128,10 @@ module wt_dcache
///////////////////////////////////////////////////////
wt_dcache_missunit #(
.CVA6Cfg (CVA6Cfg),
.AmoTxId (RdAmoTxId),
.CVA6Cfg(CVA6Cfg),
.dcache_req_t(dcache_req_t),
.dcache_rtrn_t(dcache_rtrn_t),
.AmoTxId(RdAmoTxId),
.NumPorts(NumPorts)
) i_wt_dcache_missunit (
.clk_i (clk_i),
@ -175,7 +192,9 @@ module wt_dcache
assign rd_prio[k] = 1'b1;
wt_dcache_ctrl #(
.CVA6Cfg(CVA6Cfg),
.RdTxId (RdAmoTxId)
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.RdTxId(RdAmoTxId)
) i_wt_dcache_ctrl (
.clk_i (clk_i),
.rst_ni (rst_ni),
@ -238,7 +257,10 @@ module wt_dcache
assign rd_prio[NumPorts-1] = 1'b0;
wt_dcache_wbuffer #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.wbuffer_t(wbuffer_t)
) i_wt_dcache_wbuffer (
.clk_i (clk_i),
.rst_ni (rst_ni),
@ -295,8 +317,9 @@ module wt_dcache
///////////////////////////////////////////////////////
wt_dcache_mem #(
.CVA6Cfg (CVA6Cfg),
.NumPorts(NumPorts)
.CVA6Cfg (CVA6Cfg),
.wbuffer_t(wbuffer_t),
.NumPorts (NumPorts)
) i_wt_dcache_mem (
.clk_i (clk_i),
.rst_ni (rst_ni),

4
core/cache_subsystem/wt_dcache_ctrl.sv
View file

@ -18,7 +18,9 @@ module wt_dcache_ctrl
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

5
core/cache_subsystem/wt_dcache_mem.sv
View file

@ -30,8 +30,9 @@ module wt_dcache_mem
import ariane_pkg::*;
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned NumPorts = 3
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type wbuffer_t = logic,
parameter int unsigned NumPorts = 3
) (
input logic clk_i,
input logic rst_ni,

10
core/cache_subsystem/wt_dcache_missunit.sv
View file

@ -19,6 +19,8 @@ module wt_dcache_missunit
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_t = logic,
parameter type dcache_rtrn_t = logic,
parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs
parameter int unsigned NumPorts = 4 // number of miss ports
) (
@ -52,8 +54,8 @@ module wt_dcache_missunit
output logic [NumPorts-1:0] miss_rtrn_vld_o,
output logic [CACHE_ID_WIDTH-1:0] miss_rtrn_id_o, // only used for writes, set to zero fro reads
// from writebuffer
input logic [DCACHE_MAX_TX-1:0][riscv::PLEN-1:0] tx_paddr_i, // used to check for address collisions with read operations
input logic [DCACHE_MAX_TX-1:0] tx_vld_i, // used to check for address collisions with read operations
input logic [CVA6Cfg.DCACHE_MAX_TX-1:0][riscv::PLEN-1:0] tx_paddr_i, // used to check for address collisions with read operations
input logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_i, // used to check for address collisions with read operations
// write interface to cache memory
output logic wr_cl_vld_o, // writes a full cacheline
output logic wr_cl_nc_o, // writes a full cacheline
@ -232,7 +234,7 @@ module wt_dcache_missunit
// read collides with inflight TX
always_comb begin : p_tx_coll
tx_rdwr_collision = 1'b0;
for (int k = 0; k < DCACHE_MAX_TX; k++) begin
for (int k = 0; k < CVA6Cfg.DCACHE_MAX_TX; k++) begin
tx_rdwr_collision |= (miss_paddr_i[miss_port_idx][riscv::PLEN-1:DCACHE_OFFSET_WIDTH] == tx_paddr_i[k][riscv::PLEN-1:DCACHE_OFFSET_WIDTH]) && tx_vld_i[k];
end
end
@ -325,7 +327,7 @@ module wt_dcache_missunit
// keep track of pending stores
logic store_sent;
logic [$clog2(wt_cache_pkg::DCACHE_MAX_TX + 1)-1:0] stores_inflight_d, stores_inflight_q;
logic [$clog2(CVA6Cfg.DCACHE_MAX_TX + 1)-1:0] stores_inflight_d, stores_inflight_q;
assign store_sent = mem_data_req_o & mem_data_ack_i & (mem_data_o.rtype == DCACHE_STORE_REQ);
assign stores_inflight_d = (store_ack && store_sent) ? stores_inflight_q :

25
core/cache_subsystem/wt_dcache_wbuffer.sv
View file

@ -53,7 +53,10 @@ module wt_dcache_wbuffer
import ariane_pkg::*;
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type wbuffer_t = logic
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
@ -101,11 +104,17 @@ module wt_dcache_wbuffer
output logic [DCACHE_USER_WIDTH-1:0] wr_user_o,
// to forwarding logic and miss unit
output wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_data_o,
output logic [DCACHE_MAX_TX-1:0][riscv::PLEN-1:0] tx_paddr_o, // used to check for address collisions with read operations
output logic [DCACHE_MAX_TX-1:0] tx_vld_o
output logic [CVA6Cfg.DCACHE_MAX_TX-1:0][riscv::PLEN-1:0] tx_paddr_o, // used to check for address collisions with read operations
output logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_o
);
tx_stat_t [DCACHE_MAX_TX-1:0] tx_stat_d, tx_stat_q;
typedef struct packed {
logic vld;
logic [(riscv::XLEN/8)-1:0] be;
logic [$clog2(DCACHE_WBUF_DEPTH)-1:0] ptr;
} tx_stat_t;
tx_stat_t [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_stat_d, tx_stat_q;
wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_d, wbuffer_q;
logic [DCACHE_WBUF_DEPTH-1:0] valid;
logic [DCACHE_WBUF_DEPTH-1:0] dirty;
@ -165,7 +174,7 @@ module wt_dcache_wbuffer
assign miss_vld_bits_o = '0;
assign wbuffer_data_o = wbuffer_q;
for (genvar k = 0; k < DCACHE_MAX_TX; k++) begin : gen_tx_vld
for (genvar k = 0; k < CVA6Cfg.DCACHE_MAX_TX; k++) begin : gen_tx_vld
assign tx_vld_o[k] = tx_stat_q[k].vld;
assign tx_paddr_o[k] = {
{riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[tx_stat_q[k].ptr].wtag << riscv::XLEN_ALIGN_BYTES
@ -238,8 +247,8 @@ module wt_dcache_wbuffer
// TODO: todo: make this fall through if timing permits it
fifo_v3 #(
.FALL_THROUGH(1'b0),
.DATA_WIDTH ($clog2(DCACHE_MAX_TX)),
.DEPTH (DCACHE_MAX_TX)
.DATA_WIDTH ($clog2(CVA6Cfg.DCACHE_MAX_TX)),
.DEPTH (CVA6Cfg.DCACHE_MAX_TX)
) i_rtrn_id_fifo (
.clk_i (clk_i),
.rst_ni (rst_ni),
@ -287,7 +296,7 @@ module wt_dcache_wbuffer
// next word to lookup in the cache
rr_arb_tree #(
.NumIn (DCACHE_MAX_TX),
.NumIn (CVA6Cfg.DCACHE_MAX_TX),
.LockIn (1'b1),
.DataWidth(1)
) i_tx_id_rr (

51
core/cache_subsystem/wt_l15_adapter.sv
View file

@ -53,7 +53,11 @@ module wt_l15_adapter
import ariane_pkg::*;
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type icache_req_t = logic,
parameter type icache_rtrn_t = logic,
parameter type dcache_req_t = logic,
parameter type dcache_rtrn_t = logic
) (
input logic clk_i,
input logic rst_ni,
@ -79,6 +83,51 @@ module wt_l15_adapter
input l15_rtrn_t l15_rtrn_i
);
localparam type l15_req_t = struct packed {
logic l15_val; // valid signal, asserted with request
logic l15_req_ack; // ack for response
wt_cache_pkg::l15_reqtypes_t l15_rqtype; // see below for encoding
logic l15_nc; // non-cacheable bit
logic [2:0] l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte)
logic [wt_cache_pkg::L15_TID_WIDTH-1:0] l15_threadid; // currently 0 or 1
logic l15_prefetch; // unused in openpiton
logic l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment
logic l15_blockstore; // unused in openpiton
logic l15_blockinitstore; // unused in openpiton
logic [wt_cache_pkg::L15_WAY_WIDTH-1:0] l15_l1rplway; // way to replace
logic [39:0] l15_address; // physical address
logic [63:0] l15_data; // word to write
logic [63:0] l15_data_next_entry; // unused in Ariane (only used for CAS atomic requests)
logic [wt_cache_pkg::L15_TLB_CSM_WIDTH-1:0] l15_csm_data; // unused in Ariane
logic [3:0] l15_amo_op; // atomic operation type
};
localparam type l15_rtrn_t = struct packed {
logic l15_ack; // ack for request struct
logic l15_header_ack; // ack for request struct
logic l15_val; // valid signal for return struct
wt_l15_adapter::l15_rtrntypes_t l15_returntype; // see below for encoding
logic l15_l2miss; // unused in Ariane
logic [1:0] l15_error; // unused in openpiton
logic l15_noncacheable; // non-cacheable bit
logic l15_atomic; // asserted in load return and store ack packets of atomic tx
logic [wt_cache_pkg::L15_TID_WIDTH-1:0] l15_threadid; // used as transaction ID
logic l15_prefetch; // unused in openpiton
logic l15_f4b; // 4byte instruction fill from I/O space (nc).
logic [63:0] l15_data_0; // used for both caches
logic [63:0] l15_data_1; // used for both caches
logic [63:0] l15_data_2; // currently only used for I$
logic [63:0] l15_data_3; // currently only used for I$
logic l15_inval_icache_all_way; // invalidate all ways
logic l15_inval_dcache_all_way; // unused in openpiton
logic [15:4] l15_inval_address_15_4; // invalidate selected cacheline
logic l15_cross_invalidate; // unused in openpiton
logic [wt_cache_pkg::L15_WAY_WIDTH-1:0] l15_cross_invalidate_way; // unused in openpiton
logic l15_inval_dcache_inval; // invalidate selected cacheline and way
logic l15_inval_icache_inval; // unused in openpiton
logic [wt_cache_pkg::L15_WAY_WIDTH-1:0] l15_inval_way; // way to invalidate
logic l15_blockinitstore; // unused in openpiton
};
// request path
icache_req_t icache_data;
logic icache_data_full, icache_data_empty;

4
core/commit_stage.sv
View file

@ -16,7 +16,9 @@
module commit_stage
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type exception_t = logic,
parameter type scoreboard_entry_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,

3
core/controller.sv
View file

@ -16,7 +16,8 @@
module controller
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bp_resolve_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,

3
core/csr_buffer.sv
View file

@ -17,7 +17,8 @@
module csr_buffer
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type fu_data_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,

21
core/csr_regfile.sv
View file

@ -16,9 +16,12 @@
module csr_regfile
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int AsidWidth = 1,
parameter int unsigned MHPMCounterNum = 6
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type exception_t = logic,
parameter type irq_ctrl_t = logic,
parameter type scoreboard_entry_t = logic,
parameter int AsidWidth = 1,
parameter int unsigned MHPMCounterNum = 6
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
@ -140,6 +143,12 @@ module csr_regfile
output rvfi_probes_csr_t rvfi_csr_o
);
typedef struct packed {
logic [riscv::ModeW-1:0] mode;
logic [riscv::ASIDW-1:0] asid;
logic [riscv::PPNW-1:0] ppn;
} satp_t;
// internal signal to keep track of access exceptions
logic read_access_exception, update_access_exception, privilege_violation;
logic csr_we, csr_read;
@ -155,7 +164,7 @@ module csr_regfile
logic dirty_fp_state_csr;
riscv::mstatus_rv_t mstatus_q, mstatus_d;
riscv::xlen_t mstatus_extended;
riscv::satp_t satp_q, satp_d;
satp_t satp_q, satp_d;
riscv::dcsr_t dcsr_q, dcsr_d;
riscv::csr_t csr_addr;
// privilege level register
@ -596,7 +605,7 @@ module csr_regfile
// ---------------------------
riscv::xlen_t mask;
always_comb begin : csr_update
automatic riscv::satp_t satp;
automatic satp_t satp;
automatic logic [63:0] instret;
@ -817,7 +826,7 @@ module csr_regfile
// intercept SATP writes if in S-Mode and TVM is enabled
if (priv_lvl_o == riscv::PRIV_LVL_S && mstatus_q.tvm) update_access_exception = 1'b1;
else begin
satp = riscv::satp_t'(csr_wdata);
satp = satp_t'(csr_wdata);
// only make ASID_LEN - 1 bit stick, that way software can figure out how many ASID bits are supported
satp.asid = satp.asid & {{(riscv::ASIDW - AsidWidth) {1'b0}}, {AsidWidth{1'b1}}};
// only update if we actually support this mode

293
core/cva6.sv
View file

@ -21,6 +21,169 @@ module cva6
cva6_config_pkg::cva6_cfg
),
// branchpredict scoreboard entry
// this is the struct which we will inject into the pipeline to guide the various
// units towards the correct branch decision and resolve
parameter type branchpredict_sbe_t = struct packed {
cf_t cf; // type of control flow prediction
logic [riscv::VLEN-1:0] predict_address; // target address at which to jump, or not
},
parameter type exception_t = struct packed {
logic [riscv::XLEN-1:0] cause; // cause of exception
logic [riscv::XLEN-1:0] tval; // additional information of causing exception (e.g.: instruction causing it),
// address of LD/ST fault
logic valid;
},
// cache request ports
// I$ address translation requests
parameter type icache_areq_t = struct packed {
logic fetch_valid; // address translation valid
logic [riscv::PLEN-1:0] fetch_paddr; // physical address in
exception_t fetch_exception; // exception occurred during fetch
},
parameter type icache_arsp_t = struct packed {
logic fetch_req; // address translation request
logic [riscv::VLEN-1:0] fetch_vaddr; // virtual address out
},
// I$ data requests
parameter type icache_dreq_t = struct packed {
logic req; // we request a new word
logic kill_s1; // kill the current request
logic kill_s2; // kill the last request
logic spec; // request is speculative
logic [riscv::VLEN-1:0] vaddr; // 1st cycle: 12 bit index is taken for lookup
},
parameter type icache_drsp_t = struct packed {
logic ready; // icache is ready
logic valid; // signals a valid read
logic [ariane_pkg::FETCH_WIDTH-1:0] data; // 2+ cycle out: tag
logic [ariane_pkg::FETCH_USER_WIDTH-1:0] user; // User bits
logic [riscv::VLEN-1:0] vaddr; // virtual address out
exception_t ex; // we've encountered an exception
},
// IF/ID Stage
// store the decompressed instruction
parameter type fetch_entry_t = struct packed {
logic [riscv::VLEN-1:0] address; // the address of the instructions from below
logic [31:0] instruction; // instruction word
branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path
exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions
},
// ID/EX/WB Stage
parameter type scoreboard_entry_t = struct packed {
logic [riscv::VLEN-1:0] pc; // PC of instruction
logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry
// with the transaction id in any case make the width more generic
fu_t fu; // functional unit to use
fu_op op; // operation to perform in each functional unit
logic [REG_ADDR_SIZE-1:0] rs1; // register source address 1
logic [REG_ADDR_SIZE-1:0] rs2; // register source address 2
logic [REG_ADDR_SIZE-1:0] rd; // register destination address
riscv::xlen_t result; // for unfinished instructions this field also holds the immediate,
// for unfinished floating-point that are partly encoded in rs2, this field also holds rs2
// for unfinished floating-point fused operations (FMADD, FMSUB, FNMADD, FNMSUB)
// this field holds the address of the third operand from the floating-point register file
logic valid; // is the result valid
logic use_imm; // should we use the immediate as operand b?
logic use_zimm; // use zimm as operand a
logic use_pc; // set if we need to use the PC as operand a, PC from exception
exception_t ex; // exception has occurred
branchpredict_sbe_t bp; // branch predict scoreboard data structure
logic is_compressed; // signals a compressed instructions, we need this information at the commit stage if
// we want jump accordingly e.g.: +4, +2
logic vfp; // is this a vector floating-point instruction?
},
// branch-predict
// this is the struct we get back from ex stage and we will use it to update
// all the necessary data structures
// bp_resolve_t
parameter type bp_resolve_t = struct packed {
logic valid; // prediction with all its values is valid
logic [riscv::VLEN-1:0] pc; // PC of predict or mis-predict
logic [riscv::VLEN-1:0] target_address; // target address at which to jump, or not
logic is_mispredict; // set if this was a mis-predict
logic is_taken; // branch is taken
cf_t cf_type; // Type of control flow change
},
// All information needed to determine whether we need to associate an interrupt
// with the corresponding instruction or not.
parameter type irq_ctrl_t = struct packed {
logic [riscv::XLEN-1:0] mie;
logic [riscv::XLEN-1:0] mip;
logic [riscv::XLEN-1:0] mideleg;
logic sie;
logic global_enable;
},
parameter type lsu_ctrl_t = struct packed {
logic valid;
logic [riscv::VLEN-1:0] vaddr;
logic overflow;
logic [riscv::XLEN-1:0] data;
logic [(riscv::XLEN/8)-1:0] be;
fu_t fu;
fu_op operation;
logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
},
parameter type fu_data_t = struct packed {
fu_t fu;
fu_op operation;
logic [riscv::XLEN-1:0] operand_a;
logic [riscv::XLEN-1:0] operand_b;
logic [riscv::XLEN-1:0] imm;
logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
},
parameter type icache_req_t = struct packed {
logic [$clog2(ariane_pkg::ICACHE_SET_ASSOC)-1:0] way; // way to replace
logic [riscv::PLEN-1:0] paddr; // physical address
logic nc; // noncacheable
logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
},
parameter type icache_rtrn_t = struct packed {
wt_cache_pkg::icache_in_t rtype; // see definitions above
logic [ariane_pkg::ICACHE_LINE_WIDTH-1:0] data; // full cache line width
logic [ariane_pkg::ICACHE_USER_LINE_WIDTH-1:0] user; // user bits
struct packed {
logic vld; // invalidate only affected way
logic all; // invalidate all ways
logic [ariane_pkg::ICACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate
logic [wt_cache_pkg::L1I_WAY_WIDTH-1:0] way; // way to invalidate
} inv; // invalidation vector
logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
},
// D$ data requests
parameter type dcache_req_i_t = struct packed {
logic [DCACHE_INDEX_WIDTH-1:0] address_index;
logic [DCACHE_TAG_WIDTH-1:0] address_tag;
logic [riscv::XLEN-1:0] data_wdata;
logic [DCACHE_USER_WIDTH-1:0] data_wuser;
logic data_req;
logic data_we;
logic [(riscv::XLEN/8)-1:0] data_be;
logic [1:0] data_size;
logic [DCACHE_TID_WIDTH-1:0] data_id;
logic kill_req;
logic tag_valid;
},
parameter type dcache_req_o_t = struct packed {
logic data_gnt;
logic data_rvalid;
logic [DCACHE_TID_WIDTH-1:0] data_rid;
logic [riscv::XLEN-1:0] data_rdata;
logic [DCACHE_USER_WIDTH-1:0] data_ruser;
},
parameter type rvfi_probes_t = struct packed {
logic csr; //disabled
rvfi_probes_instr_t instr;
@ -365,7 +528,11 @@ module cva6
// Frontend
// --------------
frontend #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.bp_resolve_t(bp_resolve_t),
.fetch_entry_t(fetch_entry_t),
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t)
) i_frontend (
.flush_i (flush_ctrl_if), // not entirely correct
.flush_bp_i (1'b0),
@ -392,7 +559,12 @@ module cva6
// ID
// ---------
id_stage #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.branchpredict_sbe_t(branchpredict_sbe_t),
.exception_t(exception_t),
.fetch_entry_t(fetch_entry_t),
.irq_ctrl_t(irq_ctrl_t),
.scoreboard_entry_t(scoreboard_entry_t)
) id_stage_i (
.clk_i,
.rst_ni,
@ -491,7 +663,12 @@ module cva6
// Issue
// ---------
issue_stage #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.bp_resolve_t(bp_resolve_t),
.branchpredict_sbe_t(branchpredict_sbe_t),
.exception_t(exception_t),
.fu_data_t(fu_data_t),
.scoreboard_entry_t(scoreboard_entry_t)
) issue_stage_i (
.clk_i,
.rst_ni,
@ -565,6 +742,17 @@ module cva6
// ---------
ex_stage #(
.CVA6Cfg (CVA6Cfg),
.bp_resolve_t(bp_resolve_t),
.branchpredict_sbe_t(branchpredict_sbe_t),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.exception_t(exception_t),
.fu_data_t(fu_data_t),
.icache_areq_t(icache_areq_t),
.icache_arsp_t(icache_arsp_t),
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t),
.lsu_ctrl_t(lsu_ctrl_t),
.ASID_WIDTH(ASID_WIDTH)
) ex_stage_i (
.clk_i (clk_i),
@ -678,7 +866,9 @@ module cva6
assign no_st_pending_commit = no_st_pending_ex & dcache_commit_wbuffer_empty;
commit_stage #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.exception_t(exception_t),
.scoreboard_entry_t(scoreboard_entry_t)
) commit_stage_i (
.clk_i,
.rst_ni,
@ -717,9 +907,12 @@ module cva6
// CSR
// ---------
csr_regfile #(
.CVA6Cfg (CVA6Cfg),
.AsidWidth (ASID_WIDTH),
.MHPMCounterNum(MHPMCounterNum)
.CVA6Cfg (CVA6Cfg),
.exception_t (exception_t),
.irq_ctrl_t (irq_ctrl_t),
.scoreboard_entry_t(scoreboard_entry_t),
.AsidWidth (ASID_WIDTH),
.MHPMCounterNum (MHPMCounterNum)
) csr_regfile_i (
.flush_o (flush_csr_ctrl),
.halt_csr_o (halt_csr_ctrl),
@ -786,7 +979,13 @@ module cva6
// ------------------------
if (PERF_COUNTER_EN) begin : gen_perf_counter
perf_counters #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.bp_resolve_t(bp_resolve_t),
.exception_t(exception_t),
.scoreboard_entry_t(scoreboard_entry_t),
.icache_dreq_t(icache_dreq_t),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.NumPorts(NumPorts)
) perf_counters_i (
.clk_i (clk_i),
@ -825,7 +1024,8 @@ module cva6
// Controller
// ------------
controller #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.bp_resolve_t(bp_resolve_t)
) controller_i (
// flush ports
.set_pc_commit_o (set_pc_ctrl_pcgen),
@ -890,6 +1090,14 @@ module cva6
// this is a cache subsystem that is compatible with OpenPiton
wt_cache_subsystem #(
.CVA6Cfg (CVA6Cfg),
.icache_areq_t(icache_areq_t),
.icache_arsp_t(icache_arsp_t),
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t),
.icache_req_t(icache_req_t),
.icache_rtrn_t(icache_rtrn_t),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.NumPorts (NumPorts),
.noc_req_t (noc_req_t),
.noc_resp_t(noc_resp_t)
@ -930,6 +1138,14 @@ module cva6
end else if (DCACHE_TYPE == int'(config_pkg::HPDCACHE)) begin : gen_cache_hpd
cva6_hpdcache_subsystem #(
.CVA6Cfg (CVA6Cfg),
.icache_areq_t(icache_areq_t),
.icache_arsp_t(icache_arsp_t),
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t),
.icache_req_t(icache_req_t),
.icache_rtrn_t(icache_rtrn_t),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.NumPorts (NumPorts),
.axi_ar_chan_t(axi_ar_chan_t),
.axi_aw_chan_t(axi_aw_chan_t),
@ -989,13 +1205,21 @@ module cva6
// note: this only works with one cacheable region
// not as important since this cache subsystem is about to be
// deprecated
.CVA6Cfg (CVA6Cfg),
.NumPorts (NumPorts),
.axi_ar_chan_t(axi_ar_chan_t),
.axi_aw_chan_t(axi_aw_chan_t),
.axi_w_chan_t (axi_w_chan_t),
.axi_req_t (noc_req_t),
.axi_rsp_t (noc_resp_t)
.CVA6Cfg (CVA6Cfg),
.icache_areq_t (icache_areq_t),
.icache_arsp_t (icache_arsp_t),
.icache_dreq_t (icache_dreq_t),
.icache_drsp_t (icache_drsp_t),
.icache_req_t (icache_req_t),
.icache_rtrn_t (icache_rtrn_t),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.NumPorts (NumPorts),
.axi_ar_chan_t (axi_ar_chan_t),
.axi_aw_chan_t (axi_aw_chan_t),
.axi_w_chan_t (axi_w_chan_t),
.axi_req_t (noc_req_t),
.axi_rsp_t (noc_resp_t)
) i_cache_subsystem (
// to D$
.clk_i (clk_i),
@ -1036,11 +1260,16 @@ module cva6
if (CVA6Cfg.EnableAccelerator) begin : gen_accelerator
acc_dispatcher #(
.CVA6Cfg (CVA6Cfg),
.acc_cfg_t (acc_cfg_t),
.AccCfg (AccCfg),
.acc_req_t (cvxif_req_t),
.acc_resp_t(cvxif_resp_t)
.CVA6Cfg (CVA6Cfg),
.fu_data_t (fu_data_t),
.dcache_req_i_t (dcache_req_i_t),
.dcache_req_o_t (dcache_req_o_t),
.exception_t (exception_t),
.scoreboard_entry_t(scoreboard_entry_t),
.acc_cfg_t (acc_cfg_t),
.AccCfg (AccCfg),
.acc_req_t (cvxif_req_t),
.acc_resp_t (cvxif_resp_t)
) i_acc_dispatcher (
.clk_i (clk_i),
.rst_ni (rst_ni),
@ -1167,7 +1396,14 @@ module cva6
`endif // PITON_ARIANE
`ifndef VERILATOR
instr_tracer_if tracer_if (clk_i);
instr_tracer_if #(
.CVA6Cfg(CVA6Cfg),
.bp_resolve_t(bp_resolve_t),
.exception_t(exception_t),
.scoreboard_entry_t(scoreboard_entry_t)
) tracer_if (
clk_i
);
// assign instruction tracer interface
// control signals
assign tracer_if.rstn = rst_ni;
@ -1204,7 +1440,11 @@ module cva6
assign tracer_if.priv_lvl = priv_lvl;
assign tracer_if.debug_mode = debug_mode;
instr_tracer instr_tracer_i (
instr_tracer #(
.CVA6Cfg(CVA6Cfg),
.bp_resolve_t(bp_resolve_t),
.scoreboard_entry_t(scoreboard_entry_t)
) instr_tracer_i (
.tracer_if(tracer_if),
.hart_id_i
);
@ -1270,8 +1510,11 @@ module cva6
//RVFI INSTR
cva6_rvfi_probes #(
.CVA6Cfg (CVA6Cfg),
.rvfi_probes_t(rvfi_probes_t)
.CVA6Cfg (CVA6Cfg),
.exception_t (exception_t),
.scoreboard_entry_t(scoreboard_entry_t),
.lsu_ctrl_t (lsu_ctrl_t),
.rvfi_probes_t (rvfi_probes_t)
) i_cva6_rvfi_probes (
.flush_i (flush_ctrl_if),

4
core/cva6_accel_first_pass_decoder_stub.sv
View file

@ -9,7 +9,9 @@
module cva6_accel_first_pass_decoder
import ariane_pkg::*;
(
#(
parameter type scoreboard_entry_t = logic
) (
input logic [31:0] instruction_i, // instruction from IF
input riscv::xs_t fs_i, // floating point extension status
input riscv::xs_t vs_i, // vector extension status

3
core/cva6_rvfi_probes.sv
View file

@ -13,6 +13,9 @@ module cva6_rvfi_probes
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type exception_t = logic,
parameter type scoreboard_entry_t = logic,
parameter type lsu_ctrl_t = logic,
parameter type rvfi_probes_t = logic
) (

4
core/cvxif_fu.sv
View file

@ -13,7 +13,9 @@
module cvxif_fu
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type exception_t = logic,
parameter type fu_data_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,

10
core/decoder.sv
View file

@ -22,7 +22,11 @@
module decoder
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type branchpredict_sbe_t = logic,
parameter type exception_t = logic,
parameter type irq_ctrl_t = logic,
parameter type scoreboard_entry_t = logic
) (
// Debug (async) request - SUBSYSTEM
input logic debug_req_i,
@ -103,7 +107,9 @@ module decoder
// This module is responsible for a light-weight decoding of accelerator instructions,
// identifying them, but also whether they read/write scalar registers.
// Accelerators are supposed to define this module.
cva6_accel_first_pass_decoder i_accel_decoder (
cva6_accel_first_pass_decoder #(
.scoreboard_entry_t(scoreboard_entry_t)
) i_accel_decoder (
.instruction_i(instruction_i),
.fs_i(fs_i),
.vs_i(vs_i),

43
core/ex_stage.sv
View file

@ -18,6 +18,17 @@ module ex_stage
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bp_resolve_t = logic,
parameter type branchpredict_sbe_t = logic,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type exception_t = logic,
parameter type fu_data_t = logic,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter type lsu_ctrl_t = logic,
parameter int unsigned ASID_WIDTH = 1
) (
// Subsystem Clock - SUBSYSTEM
@ -229,7 +240,8 @@ module ex_stage
assign alu_data = (alu_valid_i | branch_valid_i) ? fu_data_i : '0;
alu #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg (CVA6Cfg),
.fu_data_t(fu_data_t)
) alu_i (
.clk_i,
.rst_ni,
@ -242,7 +254,11 @@ module ex_stage
// we don't silence the branch unit as this is already critical and we do
// not want to add another layer of logic
branch_unit #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.bp_resolve_t(bp_resolve_t),
.branchpredict_sbe_t(branchpredict_sbe_t),
.exception_t(exception_t),
.fu_data_t(fu_data_t)
) branch_unit_i (
.clk_i,
.rst_ni,
@ -263,7 +279,8 @@ module ex_stage
// 3. CSR (sequential)
csr_buffer #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg (CVA6Cfg),
.fu_data_t(fu_data_t)
) csr_buffer_i (
.clk_i,
.rst_ni,
@ -306,7 +323,8 @@ module ex_stage
assign mult_data = mult_valid_i ? fu_data_i : '0;
mult #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg (CVA6Cfg),
.fu_data_t(fu_data_t)
) i_mult (
.clk_i,
.rst_ni,
@ -328,7 +346,9 @@ module ex_stage
assign fpu_data = fpu_valid_i ? fu_data_i : '0;
fpu_wrap #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.exception_t(exception_t),
.fu_data_t(fu_data_t)
) fpu_i (
.clk_i,
.rst_ni,
@ -363,6 +383,15 @@ module ex_stage
load_store_unit #(
.CVA6Cfg (CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.exception_t(exception_t),
.fu_data_t (fu_data_t),
.icache_areq_t(icache_areq_t),
.icache_arsp_t(icache_arsp_t),
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t),
.lsu_ctrl_t(lsu_ctrl_t),
.ASID_WIDTH(ASID_WIDTH)
) lsu_i (
.clk_i,
@ -416,7 +445,9 @@ module ex_stage
fu_data_t cvxif_data;
assign cvxif_data = x_valid_i ? fu_data_i : '0;
cvxif_fu #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.exception_t(exception_t),
.fu_data_t(fu_data_t)
) cvxif_fu_i (
.clk_i,
.rst_ni,

4
core/fpu_wrap.sv
View file

@ -16,7 +16,9 @@
module fpu_wrap
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type exception_t = logic,
parameter type fu_data_t = logic
) (
input logic clk_i,
input logic rst_ni,

3
core/frontend/bht.sv
View file

@ -20,6 +20,7 @@
module bht #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bht_update_t = logic,
parameter int unsigned NR_ENTRIES = 1024
) (
// Subsystem Clock - SUBSYSTEM
@ -33,7 +34,7 @@ module bht #(
// Virtual PC - CACHE
input logic [riscv::VLEN-1:0] vpc_i,
// Update bht with resolved address - EXECUTE
input ariane_pkg::bht_update_t bht_update_i,
input bht_update_t bht_update_i,
// Prediction from bht - FRONTEND
output ariane_pkg::bht_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] bht_prediction_o
);

10
core/frontend/btb.sv
View file

@ -27,6 +27,8 @@
// branch target buffer
module btb #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type btb_update_t = logic,
parameter type btb_prediction_t = logic,
parameter int NR_ENTRIES = 8
) (
// Subsystem Clock - SUBSYSTEM
@ -40,9 +42,9 @@ module btb #(
// Virtual PC - CACHE
input logic [riscv::VLEN-1:0] vpc_i,
// Update BTB with resolved address - EXECUTE
input ariane_pkg::btb_update_t btb_update_i,
input btb_update_t btb_update_i,
// BTB Prediction - FRONTEND
output ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] btb_prediction_o
output btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] btb_prediction_o
);
// the last bit is always zero, we don't need it for indexing
localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2;
@ -56,7 +58,7 @@ module btb #(
// prevent aliasing to degrade performance
localparam ANTIALIAS_BITS = 8;
// number of bits par word in the bram
localparam BRAM_WORD_BITS = $bits(ariane_pkg::btb_prediction_t);
localparam BRAM_WORD_BITS = $bits(btb_prediction_t);
// we are not interested in all bits of the address
unread i_unread (.d_i(|vpc_i));
@ -146,7 +148,7 @@ module btb #(
// typedef for all branch target entries
// we may want to try to put a tag field that fills the rest of the PC in-order to mitigate aliasing effects
ariane_pkg::btb_prediction_t
btb_prediction_t
btb_d[NR_ROWS-1:0][ariane_pkg::INSTR_PER_FETCH-1:0],
btb_q[NR_ROWS-1:0][ariane_pkg::INSTR_PER_FETCH-1:0];

44
core/frontend/frontend.sv
View file

@ -18,7 +18,11 @@
module frontend
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bp_resolve_t = logic,
parameter type fetch_entry_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
@ -61,6 +65,29 @@ module frontend
// Handshake's ready between fetch and decode - ID_STAGE
input logic fetch_entry_ready_i
);
localparam type bht_update_t = struct packed {
logic valid;
logic [riscv::VLEN-1:0] pc; // update at PC
logic taken;
};
localparam type btb_prediction_t = struct packed {
logic valid;
logic [riscv::VLEN-1:0] target_address;
};
localparam type btb_update_t = struct packed {
logic valid;
logic [riscv::VLEN-1:0] pc; // update at PC
logic [riscv::VLEN-1:0] target_address;
};
localparam type ras_t = struct packed {
logic valid;
logic [riscv::VLEN-1:0] ra;
};
// Instruction Cache Registers, from I$
logic [ FETCH_WIDTH-1:0] icache_data_q;
logic icache_valid_q;
@ -422,15 +449,16 @@ module frontend
end else begin : ras_gen
ras #(
.CVA6Cfg(CVA6Cfg),
.ras_t (ras_t),
.DEPTH (CVA6Cfg.RASDepth)
) i_ras (
.clk_i,
.rst_ni,
.flush_bp_i(flush_bp_i),
.push_i (ras_push),
.pop_i (ras_pop),
.data_i (ras_update),
.data_o (ras_predict)
.push_i(ras_push),
.pop_i(ras_pop),
.data_i(ras_update),
.data_o(ras_predict)
);
end
@ -444,6 +472,8 @@ module frontend
end else begin : btb_gen
btb #(
.CVA6Cfg (CVA6Cfg),
.btb_update_t(btb_update_t),
.btb_prediction_t(btb_prediction_t),
.NR_ENTRIES(CVA6Cfg.BTBEntries)
) i_btb (
.clk_i,
@ -461,6 +491,7 @@ module frontend
end else begin : bht_gen
bht #(
.CVA6Cfg (CVA6Cfg),
.bht_update_t(bht_update_t),
.NR_ENTRIES(CVA6Cfg.BHTEntries)
) i_bht (
.clk_i,
@ -497,7 +528,8 @@ module frontend
end
instr_queue #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.fetch_entry_t(fetch_entry_t)
) i_instr_queue (
.clk_i (clk_i),
.rst_ni (rst_ni),

5
core/frontend/instr_queue.sv
View file

@ -46,7 +46,8 @@
module instr_queue
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type fetch_entry_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
@ -77,7 +78,7 @@ module instr_queue
// Address at which to replay the fetch - FRONTEND
output logic [riscv::VLEN-1:0] replay_addr_o,
// Handshake’s data with ID_STAGE - ID_STAGE
output ariane_pkg::fetch_entry_t fetch_entry_o,
output fetch_entry_t fetch_entry_o,
// Handshake’s valid with ID_STAGE - ID_STAGE
output logic fetch_entry_valid_o,
// Handshake’s ready with ID_STAGE - ID_STAGE

5
core/frontend/ras.sv
View file

@ -16,6 +16,7 @@
// return address stack
module ras #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type ras_t = logic,
parameter int unsigned DEPTH = 2
) (
// Subsystem Clock - SUBSYSTEM
@ -31,10 +32,10 @@ module ras #(
// Data to be pushed - FRONTEND
input logic [riscv::VLEN-1:0] data_i,
// Popped data - FRONTEND
output ariane_pkg::ras_t data_o
output ras_t data_o
);
ariane_pkg::ras_t [DEPTH-1:0] stack_d, stack_q;
ras_t [DEPTH-1:0] stack_d, stack_q;
assign data_o = stack_q[0];

39
core/id_stage.sv
View file

@ -14,7 +14,12 @@
// issue and read operands.
module id_stage #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type branchpredict_sbe_t = logic,
parameter type exception_t = logic,
parameter type fetch_entry_t = logic,
parameter type irq_ctrl_t = logic,
parameter type scoreboard_entry_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
@ -25,13 +30,13 @@ module id_stage #(
// Debug (async) request - SUBSYSTEM
input logic debug_req_i,
// Handshake's data between fetch and decode - FRONTEND
input ariane_pkg::fetch_entry_t fetch_entry_i,
input fetch_entry_t fetch_entry_i,
// Handshake's valid between fetch and decode - FRONTEND
input logic fetch_entry_valid_i,
// Handshake's ready between fetch and decode - FRONTEND
output logic fetch_entry_ready_o,
// Handshake's data between decode and issue - ISSUE
output ariane_pkg::scoreboard_entry_t issue_entry_o,
output scoreboard_entry_t issue_entry_o,
// Instruction value - ISSUE
output logic [31:0] orig_instr_o,
// Handshake's valid between decode and issue - ISSUE
@ -53,7 +58,7 @@ module id_stage #(
// Level sensitive (async) interrupts - SUBSYSTEM
input logic [1:0] irq_i,
// Interrupt control status - CSR_REGFILE
input ariane_pkg::irq_ctrl_t irq_ctrl_i,
input irq_ctrl_t irq_ctrl_i,
// Is current mode debug ? - CSR_REGFILE
input logic debug_mode_i,
// Trap virtual memory - CSR_REGFILE
@ -65,20 +70,20 @@ module id_stage #(
);
// ID/ISSUE register stage
typedef struct packed {
logic valid;
ariane_pkg::scoreboard_entry_t sbe;
logic [31:0] orig_instr;
logic is_ctrl_flow;
logic valid;
scoreboard_entry_t sbe;
logic [31:0] orig_instr;
logic is_ctrl_flow;
} issue_struct_t;
issue_struct_t issue_n, issue_q;
logic is_control_flow_instr;
ariane_pkg::scoreboard_entry_t decoded_instruction;
logic [31:0] orig_instr;
logic is_control_flow_instr;
scoreboard_entry_t decoded_instruction;
logic [31:0] orig_instr;
logic is_illegal;
logic [31:0] instruction;
logic is_compressed;
logic is_illegal;
logic [31:0] instruction;
logic is_compressed;
if (CVA6Cfg.RVC) begin
// ---------------------------------------------------------
@ -103,7 +108,11 @@ module id_stage #(
// 2. Decode and emit instruction to issue stage
// ---------------------------------------------------------
decoder #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.branchpredict_sbe_t(branchpredict_sbe_t),
.exception_t(exception_t),
.irq_ctrl_t(irq_ctrl_t),
.scoreboard_entry_t(scoreboard_entry_t)
) decoder_i (
.debug_req_i,
.irq_ctrl_i,

47
core/include/acc_pkg.sv
View file

@ -1,47 +0,0 @@
// Copyright 2023 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
// Authors: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
// Nils Wistoff <nwistoff@iis.ee.ethz.ch>
// Package defining the accelerator interface as used by Ara + CVA6
package acc_pkg;
// ----------------------
// Accelerator Interface
// ----------------------
typedef struct packed {
logic req_valid;
logic resp_ready;
riscv::instruction_t insn;
riscv::xlen_t rs1;
riscv::xlen_t rs2;
fpnew_pkg::roundmode_e frm;
logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
logic store_pending;
// Invalidation interface
logic acc_cons_en;
logic inval_ready;
} accelerator_req_t;
typedef struct packed {
logic req_ready;
logic resp_valid;
riscv::xlen_t result;
logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
logic error;
// Metadata
logic store_pending;
logic store_complete;
logic load_complete;
logic [4:0] fflags;
logic fflags_valid;
// Invalidation interface
logic inval_valid;
logic [63:0] inval_addr;
} accelerator_resp_t;
endpackage

188
core/include/ariane_pkg.sv
View file

@ -167,15 +167,6 @@ package ariane_pkg;
localparam int unsigned INSTR_PER_FETCH = RVC == 1'b1 ? (FETCH_WIDTH / 16) : 1;
localparam int unsigned LOG2_INSTR_PER_FETCH = RVC == 1'b1 ? $clog2(INSTR_PER_FETCH) : 1;
// Only use struct when signals have same direction
// exception
typedef struct packed {
riscv::xlen_t cause; // cause of exception
riscv::xlen_t tval; // additional information of causing exception (e.g.: instruction causing it),
// address of LD/ST fault
logic valid;
} exception_t;
typedef enum logic [2:0] {
NoCF, // No control flow prediction
Branch, // Branch
@ -184,49 +175,6 @@ package ariane_pkg;
Return // Return Address Prediction
} cf_t;
// branch-predict
// this is the struct we get back from ex stage and we will use it to update
// all the necessary data structures
// bp_resolve_t
typedef struct packed {
logic valid; // prediction with all its values is valid
logic [riscv::VLEN-1:0] pc; // PC of predict or mis-predict
logic [riscv::VLEN-1:0] target_address; // target address at which to jump, or not
logic is_mispredict; // set if this was a mis-predict
logic is_taken; // branch is taken
cf_t cf_type; // Type of control flow change
} bp_resolve_t;
// branchpredict scoreboard entry
// this is the struct which we will inject into the pipeline to guide the various
// units towards the correct branch decision and resolve
typedef struct packed {
cf_t cf; // type of control flow prediction
logic [riscv::VLEN-1:0] predict_address; // target address at which to jump, or not
} branchpredict_sbe_t;
typedef struct packed {
logic valid;
logic [riscv::VLEN-1:0] pc; // update at PC
logic [riscv::VLEN-1:0] target_address;
} btb_update_t;
typedef struct packed {
logic valid;
logic [riscv::VLEN-1:0] target_address;
} btb_prediction_t;
typedef struct packed {
logic valid;
logic [riscv::VLEN-1:0] ra;
} ras_t;
typedef struct packed {
logic valid;
logic [riscv::VLEN-1:0] pc; // update at PC
logic taken;
} bht_update_t;
typedef struct packed {
logic valid;
logic taken;
@ -256,16 +204,6 @@ package ariane_pkg;
localparam SupervisorIrq = 1;
localparam MachineIrq = 0;
// All information needed to determine whether we need to associate an interrupt
// with the corresponding instruction or not.
typedef struct packed {
riscv::xlen_t mie;
riscv::xlen_t mip;
riscv::xlen_t mideleg;
logic sie;
logic global_enable;
} irq_ctrl_t;
// ---------------
// Cache config
// ---------------
@ -554,15 +492,6 @@ package ariane_pkg;
CZERO_NEZ
} fu_op;
typedef struct packed {
fu_t fu;
fu_op operation;
riscv::xlen_t operand_a;
riscv::xlen_t operand_b;
riscv::xlen_t imm;
logic [TRANS_ID_BITS-1:0] trans_id;
} fu_data_t;
function automatic logic op_is_branch(input fu_op op);
unique case (op) inside
EQ, NE, LTS, GES, LTU, GEU: return 1'b1;
@ -647,56 +576,6 @@ package ariane_pkg;
endcase
endfunction
typedef struct packed {
logic valid;
logic [riscv::VLEN-1:0] vaddr;
logic overflow;
riscv::xlen_t data;
logic [(riscv::XLEN/8)-1:0] be;
fu_t fu;
fu_op operation;
logic [TRANS_ID_BITS-1:0] trans_id;
} lsu_ctrl_t;
// ---------------
// IF/ID Stage
// ---------------
// store the decompressed instruction
typedef struct packed {
logic [riscv::VLEN-1:0] address; // the address of the instructions from below
logic [31:0] instruction; // instruction word
branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path
exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions
} fetch_entry_t;
// ---------------
// ID/EX/WB Stage
// ---------------
typedef struct packed {
logic [riscv::VLEN-1:0] pc; // PC of instruction
logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry
// with the transaction id in any case make the width more generic
fu_t fu; // functional unit to use
fu_op op; // operation to perform in each functional unit
logic [REG_ADDR_SIZE-1:0] rs1; // register source address 1
logic [REG_ADDR_SIZE-1:0] rs2; // register source address 2
logic [REG_ADDR_SIZE-1:0] rd; // register destination address
riscv::xlen_t result; // for unfinished instructions this field also holds the immediate,
// for unfinished floating-point that are partly encoded in rs2, this field also holds rs2
// for unfinished floating-point fused operations (FMADD, FMSUB, FNMADD, FNMSUB)
// this field holds the address of the third operand from the floating-point register file
logic valid; // is the result valid
logic use_imm; // should we use the immediate as operand b?
logic use_zimm; // use zimm as operand a
logic use_pc; // set if we need to use the PC as operand a, PC from exception
exception_t ex; // exception has occurred
branchpredict_sbe_t bp; // branch predict scoreboard data structure
logic is_compressed; // signals a compressed instructions, we need this information at the commit stage if
// we want jump accordingly e.g.: +4, +2
logic vfp; // is this a vector floating-point instruction?
} scoreboard_entry_t;
// ---------------
// MMU instanciation
// ---------------
@ -731,15 +610,6 @@ package ariane_pkg;
AMO_CAS2 = 4'b1101 // unused, not part of riscv spec, but provided in OpenPiton
} amo_t;
typedef struct packed {
logic valid; // valid flag
logic is_2M; //
logic is_1G; //
logic [27-1:0] vpn; // VPN (39bits) = 27bits + 12bits offset
logic [ASID_WIDTH-1:0] asid;
riscv::pte_t content;
} tlb_update_t;
// Bits required for representation of physical address space as 4K pages
// (e.g. 27*4K == 39bit address space).
localparam PPN4K_WIDTH = 38;
@ -758,39 +628,6 @@ package ariane_pkg;
FE_INSTR_PAGE_FAULT
} frontend_exception_t;
// ----------------------
// cache request ports
// ----------------------
// I$ address translation requests
typedef struct packed {
logic fetch_valid; // address translation valid
logic [riscv::PLEN-1:0] fetch_paddr; // physical address in
exception_t fetch_exception; // exception occurred during fetch
} icache_areq_t;
typedef struct packed {
logic fetch_req; // address translation request
logic [riscv::VLEN-1:0] fetch_vaddr; // virtual address out
} icache_arsp_t;
// I$ data requests
typedef struct packed {
logic req; // we request a new word
logic kill_s1; // kill the current request
logic kill_s2; // kill the last request
logic spec; // request is speculative
logic [riscv::VLEN-1:0] vaddr; // 1st cycle: 12 bit index is taken for lookup
} icache_dreq_t;
typedef struct packed {
logic ready; // icache is ready
logic valid; // signals a valid read
logic [FETCH_WIDTH-1:0] data; // 2+ cycle out: tag
logic [FETCH_USER_WIDTH-1:0] user; // User bits
logic [riscv::VLEN-1:0] vaddr; // virtual address out
exception_t ex; // we've encountered an exception
} icache_drsp_t;
// AMO request going to cache. this request is unconditionally valid as soon
// as request goes high.
// Furthermore, those signals are kept stable until the response indicates
@ -809,29 +646,6 @@ package ariane_pkg;
logic [63:0] result; // sign-extended, result
} amo_resp_t;
// D$ data requests
typedef struct packed {
logic [DCACHE_INDEX_WIDTH-1:0] address_index;
logic [DCACHE_TAG_WIDTH-1:0] address_tag;
riscv::xlen_t data_wdata;
logic [DCACHE_USER_WIDTH-1:0] data_wuser;
logic data_req;
logic data_we;
logic [(riscv::XLEN/8)-1:0] data_be;
logic [1:0] data_size;
logic [DCACHE_TID_WIDTH-1:0] data_id;
logic kill_req;
logic tag_valid;
} dcache_req_i_t;
typedef struct packed {
logic data_gnt;
logic data_rvalid;
logic [DCACHE_TID_WIDTH-1:0] data_rid;
riscv::xlen_t data_rdata;
logic [DCACHE_USER_WIDTH-1:0] data_ruser;
} dcache_req_o_t;
// RVFI instr
typedef struct packed {
logic [TRANS_ID_BITS-1:0] issue_pointer;
@ -890,7 +704,7 @@ package ariane_pkg;
riscv::xlen_t sepc_q;
riscv::xlen_t scause_q;
riscv::xlen_t stval_q;
riscv::satp_t satp_q;
riscv::xlen_t satp_q;
riscv::xlen_t mstatus_extended;
riscv::xlen_t medeleg_q;
riscv::xlen_t mideleg_q;

3
core/include/build_config_pkg.sv
View file

@ -28,6 +28,7 @@ package build_config_pkg;
cfg.AxiDataWidth = CVA6Cfg.AxiDataWidth;
cfg.AxiIdWidth = CVA6Cfg.AxiIdWidth;
cfg.AxiUserWidth = CVA6Cfg.AxiUserWidth;
cfg.MEM_TID_WIDTH = CVA6Cfg.MemTidWidth;
cfg.NrLoadBufEntries = CVA6Cfg.NrLoadBufEntries;
cfg.FpuEn = CVA6Cfg.FpuEn;
cfg.XF16 = CVA6Cfg.XF16;
@ -83,6 +84,8 @@ package build_config_pkg;
cfg.NonIdemPotenceEn = CVA6Cfg.NrNonIdempotentRules && CVA6Cfg.NonIdempotentLength;
cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn;
cfg.DCACHE_MAX_TX = unsigned'(2 ** CVA6Cfg.MemTidWidth);
return cfg;
endfunction

5
core/include/config_pkg.sv
View file

@ -46,6 +46,8 @@ package config_pkg;
int unsigned AxiIdWidth;
// AXI User width
int unsigned AxiUserWidth;
// TODO
int unsigned MemTidWidth;
// Load buffer entry buffer
int unsigned NrLoadBufEntries;
// Floating Point
@ -137,6 +139,7 @@ package config_pkg;
int unsigned AxiDataWidth;
int unsigned AxiIdWidth;
int unsigned AxiUserWidth;
int unsigned MEM_TID_WIDTH;
int unsigned NrLoadBufEntries;
bit FpuEn;
bit XF16;
@ -191,6 +194,8 @@ package config_pkg;
bit DebugEn;
bit NonIdemPotenceEn; // Currently only used by V extension (Ara)
bit AxiBurstWriteEn;
int unsigned DCACHE_MAX_TX;
} cva6_cfg_t;
/// Empty configuration to sanity check proper parameter passing. Whenever

1
core/include/cv32a60x_config_pkg.sv
View file

@ -80,6 +80,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv32a65x_config_pkg.sv
View file

@ -79,6 +79,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv32a6_embedded_config_pkg.sv
View file

@ -79,6 +79,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
View file

@ -80,6 +80,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv32a6_imac_sv0_config_pkg.sv
View file

@ -80,6 +80,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv32a6_imac_sv32_config_pkg.sv
View file

@ -80,6 +80,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv32a6_imafc_sv32_config_pkg.sv
View file

@ -80,6 +80,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
View file

@ -80,6 +80,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file

@ -80,6 +80,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
View file

@ -87,6 +87,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
View file

@ -80,6 +80,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
View file

@ -80,6 +80,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

1
core/include/cv64a6_imafdcv_sv39_config_pkg.sv
View file

@ -80,6 +80,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),

6
core/include/riscv_pkg.sv
View file

@ -123,12 +123,6 @@ package riscv;
logic wpri0; // writes preserved reads ignored
} mstatus_rv_t;
typedef struct packed {
logic [ModeW-1:0] mode;
logic [ASIDW-1:0] asid;
logic [PPNW-1:0] ppn;
} satp_t;
// --------------------
// Instruction Types
// --------------------

14
core/include/std_cache_pkg.sv
View file

@ -61,20 +61,6 @@ package std_cache_pkg;
logic [63:0] rdata;
} bypass_rsp_t;
typedef struct packed {
logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag; // tag array
logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // data array
logic valid; // state array
logic dirty; // state array
} cache_line_t;
// cache line byte enable
typedef struct packed {
logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array
logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] vldrty; // bit enable into state array (valid for a pair of dirty/valid bits)
} cl_be_t;
// convert one hot to bin for -> needed for cache replacement
function automatic logic [DCACHE_SET_ASSOC_WIDTH-1:0] one_hot_to_bin(
input logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] in);

118
core/include/wt_cache_pkg.sv
View file

@ -64,31 +64,12 @@ package wt_cache_pkg;
// write buffer parameterization
localparam DCACHE_WBUF_DEPTH = ariane_pkg::WT_DCACHE_WBUF_DEPTH;
localparam DCACHE_MAX_TX = 2 ** L15_TID_WIDTH;
localparam CACHE_ID_WIDTH = L15_TID_WIDTH;
typedef struct packed {
logic [ariane_pkg::DCACHE_TAG_WIDTH+(ariane_pkg::DCACHE_INDEX_WIDTH-riscv::XLEN_ALIGN_BYTES)-1:0] wtag;
riscv::xlen_t data;
logic [ariane_pkg::DCACHE_USER_WIDTH-1:0] user;
logic [(riscv::XLEN/8)-1:0] dirty; // byte is dirty
logic [(riscv::XLEN/8)-1:0] valid; // byte is valid
logic [(riscv::XLEN/8)-1:0] txblock; // byte is part of transaction in-flight
logic checked; // if cache state of this word has been checked
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] hit_oh; // valid way in the cache
} wbuffer_t;
// TX status registers are indexed with the transaction ID
// they basically store which bytes from which buffer entry are part
// of that transaction
typedef struct packed {
logic vld;
logic [(riscv::XLEN/8)-1:0] be;
logic [$clog2(DCACHE_WBUF_DEPTH)-1:0] ptr;
} tx_stat_t;
// local interfaces between caches and L15 adapter
typedef enum logic [1:0] {
DCACHE_STORE_REQ,
@ -110,58 +91,6 @@ package wt_cache_pkg;
ICACHE_IFILL_ACK
} icache_in_t;
// icache interface
typedef struct packed {
logic vld; // invalidate only affected way
logic all; // invalidate all ways
logic [ariane_pkg::ICACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate
logic [L1I_WAY_WIDTH-1:0] way; // way to invalidate
} icache_inval_t;
typedef struct packed {
logic [$clog2(ariane_pkg::ICACHE_SET_ASSOC)-1:0] way; // way to replace
logic [riscv::PLEN-1:0] paddr; // physical address
logic nc; // noncacheable
logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
} icache_req_t;
typedef struct packed {
icache_in_t rtype; // see definitions above
logic [ariane_pkg::ICACHE_LINE_WIDTH-1:0] data; // full cache line width
logic [ariane_pkg::ICACHE_USER_LINE_WIDTH-1:0] user; // user bits
icache_inval_t inv; // invalidation vector
logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
} icache_rtrn_t;
// dcache interface
typedef struct packed {
logic vld; // invalidate only affected way
logic all; // invalidate all ways
logic [ariane_pkg::DCACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate
logic [L15_WAY_WIDTH-1:0] way; // way to invalidate
} dcache_inval_t;
typedef struct packed {
dcache_out_t rtype; // see definitions above
logic [2:0] size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte)
logic [L1D_WAY_WIDTH-1:0] way; // way to replace
logic [riscv::PLEN-1:0] paddr; // physical address
riscv::xlen_t data; // word width of processor (no block stores at the moment)
logic [ariane_pkg::DATA_USER_WIDTH-1:0] user; // user width of processor (no block stores at the moment)
logic nc; // noncacheable
logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
ariane_pkg::amo_t amo_op; // amo opcode
} dcache_req_t;
typedef struct packed {
dcache_in_t rtype; // see definitions above
logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // full cache line width
logic [ariane_pkg::DCACHE_USER_LINE_WIDTH-1:0] user; // user bits
dcache_inval_t inv; // invalidation vector
logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane)
} dcache_rtrn_t;
// taken from iop.h in openpiton
// to l1.5 (only marked subset is used)
typedef enum logic [4:0] {
@ -201,53 +130,6 @@ package wt_cache_pkg;
L15_CPX_RESTYPE_ATOMIC_RES = 4'b1110 // custom type for atomic responses
} l15_rtrntypes_t;
typedef struct packed {
logic l15_val; // valid signal, asserted with request
logic l15_req_ack; // ack for response
l15_reqtypes_t l15_rqtype; // see below for encoding
logic l15_nc; // non-cacheable bit
logic [2:0] l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte)
logic [L15_TID_WIDTH-1:0] l15_threadid; // currently 0 or 1
logic l15_prefetch; // unused in openpiton
logic l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment
logic l15_blockstore; // unused in openpiton
logic l15_blockinitstore; // unused in openpiton
logic [L15_WAY_WIDTH-1:0] l15_l1rplway; // way to replace
logic [39:0] l15_address; // physical address
logic [63:0] l15_data; // word to write
logic [63:0] l15_data_next_entry; // unused in Ariane (only used for CAS atomic requests)
logic [L15_TLB_CSM_WIDTH-1:0] l15_csm_data; // unused in Ariane
logic [3:0] l15_amo_op; // atomic operation type
} l15_req_t;
typedef struct packed {
logic l15_ack; // ack for request struct
logic l15_header_ack; // ack for request struct
logic l15_val; // valid signal for return struct
l15_rtrntypes_t l15_returntype; // see below for encoding
logic l15_l2miss; // unused in Ariane
logic [1:0] l15_error; // unused in openpiton
logic l15_noncacheable; // non-cacheable bit
logic l15_atomic; // asserted in load return and store ack packets of atomic tx
logic [L15_TID_WIDTH-1:0] l15_threadid; // used as transaction ID
logic l15_prefetch; // unused in openpiton
logic l15_f4b; // 4byte instruction fill from I/O space (nc).
logic [63:0] l15_data_0; // used for both caches
logic [63:0] l15_data_1; // used for both caches
logic [63:0] l15_data_2; // currently only used for I$
logic [63:0] l15_data_3; // currently only used for I$
logic l15_inval_icache_all_way; // invalidate all ways
logic l15_inval_dcache_all_way; // unused in openpiton
logic [15:4] l15_inval_address_15_4; // invalidate selected cacheline
logic l15_cross_invalidate; // unused in openpiton
logic [L15_WAY_WIDTH-1:0] l15_cross_invalidate_way; // unused in openpiton
logic l15_inval_dcache_inval; // invalidate selected cacheline and way
logic l15_inval_icache_inval; // unused in openpiton
logic [L15_WAY_WIDTH-1:0] l15_inval_way; // way to invalidate
logic l15_blockinitstore; // unused in openpiton
} l15_rtrn_t;
// swap endianess in a 64bit word
function automatic logic [63:0] swendian64(input logic [63:0] in);
automatic logic [63:0] out;

3
core/issue_read_operands.sv
View file

@ -18,6 +18,9 @@ module issue_read_operands
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type branchpredict_sbe_t = logic,
parameter type fu_data_t = logic,
parameter type scoreboard_entry_t = logic,
parameter type rs3_len_t = logic
) (
// Subsystem Clock - SUBSYSTEM

19
core/issue_stage.sv
View file

@ -17,7 +17,12 @@
module issue_stage
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bp_resolve_t = logic,
parameter type branchpredict_sbe_t = logic,
parameter type exception_t = logic,
parameter type fu_data_t = logic,
parameter type scoreboard_entry_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
@ -157,8 +162,11 @@ module issue_stage
// 2. Manage instructions in a scoreboard
// ---------------------------------------------------------
scoreboard #(
.CVA6Cfg (CVA6Cfg),
.rs3_len_t(rs3_len_t)
.CVA6Cfg (CVA6Cfg),
.rs3_len_t (rs3_len_t),
.bp_resolve_t(bp_resolve_t),
.exception_t(exception_t),
.scoreboard_entry_t(scoreboard_entry_t)
) i_scoreboard (
.sb_full_o (sb_full_o),
.unresolved_branch_i(1'b0),
@ -193,7 +201,10 @@ module issue_stage
// 3. Issue instruction and read operand, also commit
// ---------------------------------------------------------
issue_read_operands #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.branchpredict_sbe_t(branchpredict_sbe_t),
.fu_data_t(fu_data_t),
.scoreboard_entry_t(scoreboard_entry_t),
.rs3_len_t(rs3_len_t)
) i_issue_read_operands (
.flush_i (flush_unissued_instr_i),

39
core/load_store_unit.sv
View file

@ -17,6 +17,15 @@ module load_store_unit
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type exception_t = logic,
parameter type fu_data_t = logic,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter type lsu_ctrl_t = logic,
parameter int unsigned ASID_WIDTH = 1
) (
// Subsystem Clock - SUBSYSTEM
@ -118,6 +127,7 @@ module load_store_unit
// RVFI information - RVFI
output [riscv::PLEN-1:0] rvfi_mem_paddr_o
);
// data is misaligned
logic data_misaligned;
// --------------------------------------
@ -178,6 +188,13 @@ module load_store_unit
if (MMU_PRESENT && (riscv::XLEN == 64)) begin : gen_mmu_sv39
mmu #(
.CVA6Cfg (CVA6Cfg),
.exception_t (exception_t),
.icache_areq_t (icache_areq_t),
.icache_arsp_t (icache_arsp_t),
.icache_dreq_t (icache_dreq_t),
.icache_drsp_t (icache_drsp_t),
.dcache_req_i_t (dcache_req_i_t),
.dcache_req_o_t (dcache_req_o_t),
.INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES),
.DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES),
.ASID_WIDTH (ASID_WIDTH)
@ -207,6 +224,13 @@ module load_store_unit
end else if (MMU_PRESENT && (riscv::XLEN == 32)) begin : gen_mmu_sv32
cva6_mmu_sv32 #(
.CVA6Cfg (CVA6Cfg),
.exception_t (exception_t),
.icache_areq_t (icache_areq_t),
.icache_arsp_t (icache_arsp_t),
.icache_dreq_t (icache_dreq_t),
.icache_drsp_t (icache_drsp_t),
.dcache_req_i_t (dcache_req_i_t),
.dcache_req_o_t (dcache_req_o_t),
.INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES),
.DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES),
.ASID_WIDTH (ASID_WIDTH)
@ -281,7 +305,11 @@ module load_store_unit
// Store Unit
// ------------------
store_unit #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.exception_t(exception_t),
.lsu_ctrl_t(lsu_ctrl_t)
) i_store_unit (
.clk_i,
.rst_ni,
@ -323,7 +351,11 @@ module load_store_unit
// Load Unit
// ------------------
load_unit #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.exception_t(exception_t),
.lsu_ctrl_t(lsu_ctrl_t)
) i_load_unit (
.valid_i (ld_valid_i),
.lsu_ctrl_i(lsu_ctrl),
@ -517,7 +549,8 @@ module load_store_unit
};
lsu_bypass #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.lsu_ctrl_t(lsu_ctrl_t)
) lsu_bypass_i (
.lsu_req_i (lsu_req_i),
.lsu_req_valid_i(lsu_valid_i),

6
core/load_unit.sv
View file

@ -21,7 +21,11 @@
module load_unit
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type exception_t = logic,
parameter type lsu_ctrl_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,

3
core/lsu_bypass.sv
View file

@ -26,7 +26,8 @@
module lsu_bypass
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type lsu_ctrl_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,

9
core/mmu_sv32/cva6_mmu_sv32.sv
View file

@ -30,6 +30,13 @@ module cva6_mmu_sv32
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type exception_t = logic,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter int unsigned INSTR_TLB_ENTRIES = 2,
parameter int unsigned DATA_TLB_ENTRIES = 2,
parameter int unsigned ASID_WIDTH = 1
@ -199,6 +206,8 @@ module cva6_mmu_sv32
cva6_ptw_sv32 #(
.CVA6Cfg (CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.ASID_WIDTH(ASID_WIDTH)
) i_ptw (
.clk_i (clk_i),

2
core/mmu_sv32/cva6_ptw_sv32.sv
View file

@ -30,6 +30,8 @@ module cva6_ptw_sv32
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter int ASID_WIDTH = 1
) (
input logic clk_i, // Clock

33
core/mmu_sv39/mmu.sv
View file

@ -19,6 +19,13 @@ module mmu
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type exception_t = logic,
parameter int unsigned INSTR_TLB_ENTRIES = 4,
parameter int unsigned DATA_TLB_ENTRIES = 4,
parameter int unsigned ASID_WIDTH = 1
@ -68,6 +75,15 @@ module mmu
input logic [15:0][riscv::PLEN-3:0] pmpaddr_i
);
localparam type tlb_update_t = struct packed {
logic valid; // valid flag
logic is_2M; //
logic is_1G; //
logic [27-1:0] vpn; // VPN (39bits) = 27bits + 12bits offset
logic [ASID_WIDTH-1:0] asid;
riscv::pte_t content;
};
logic iaccess_err; // insufficient privilege to access this instruction page
logic daccess_err; // insufficient privilege to access this data page
logic ptw_active; // PTW is currently walking a page table
@ -98,9 +114,10 @@ module mmu
tlb #(
.CVA6Cfg (CVA6Cfg),
.TLB_ENTRIES(INSTR_TLB_ENTRIES),
.ASID_WIDTH (ASID_WIDTH)
.CVA6Cfg (CVA6Cfg),
.tlb_update_t(tlb_update_t),
.TLB_ENTRIES (INSTR_TLB_ENTRIES),
.ASID_WIDTH (ASID_WIDTH)
) i_itlb (
.clk_i (clk_i),
.rst_ni (rst_ni),
@ -121,9 +138,10 @@ module mmu
);
tlb #(
.CVA6Cfg (CVA6Cfg),
.TLB_ENTRIES(DATA_TLB_ENTRIES),
.ASID_WIDTH (ASID_WIDTH)
.CVA6Cfg (CVA6Cfg),
.tlb_update_t(tlb_update_t),
.TLB_ENTRIES (DATA_TLB_ENTRIES),
.ASID_WIDTH (ASID_WIDTH)
) i_dtlb (
.clk_i (clk_i),
.rst_ni (rst_ni),
@ -146,6 +164,9 @@ module mmu
ptw #(
.CVA6Cfg (CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.tlb_update_t(tlb_update_t),
.ASID_WIDTH(ASID_WIDTH)
) i_ptw (
.clk_i (clk_i),

3
core/mmu_sv39/ptw.sv
View file

@ -19,6 +19,9 @@ module ptw
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type tlb_update_t = logic,
parameter int ASID_WIDTH = 1
) (
input logic clk_i, // Clock

1
core/mmu_sv39/tlb.sv
View file

@ -19,6 +19,7 @@ module tlb
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type tlb_update_t = logic,
parameter int unsigned TLB_ENTRIES = 4,
parameter int unsigned ASID_WIDTH = 1
) (

3
core/mult.sv
View file

@ -3,7 +3,8 @@
module mult
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type fu_data_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,

10
core/perf_counters.sv
View file

@ -16,8 +16,14 @@
module perf_counters
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned NumPorts = 3 // number of miss ports
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bp_resolve_t = logic,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type exception_t = logic,
parameter type icache_dreq_t = logic,
parameter type scoreboard_entry_t = logic,
parameter int unsigned NumPorts = 3 // number of miss ports
) (
input logic clk_i,
input logic rst_ni,

31
core/scoreboard.sv
View file

@ -14,6 +14,9 @@
module scoreboard #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type bp_resolve_t = logic,
parameter type exception_t = logic,
parameter type scoreboard_entry_t = logic,
parameter type rs3_len_t = logic
) (
// Subsystem Clock - SUBSYSTEM
@ -56,39 +59,39 @@ module scoreboard #(
// advertise instruction to commit stage, if commit_ack_i is asserted advance the commit pointer
// TO_BE_COMPLETED - TO_BE_COMPLETED
output ariane_pkg::scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o,
output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
// instruction to put on top of scoreboard e.g.: top pointer
// we can always put this instruction to the top unless we signal with asserted full_o
// TO_BE_COMPLETED - TO_BE_COMPLETED
input ariane_pkg::scoreboard_entry_t decoded_instr_i,
input scoreboard_entry_t decoded_instr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [31:0] orig_instr_i,
input logic [31:0] orig_instr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic decoded_instr_valid_i,
input logic decoded_instr_valid_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic decoded_instr_ack_o,
output logic decoded_instr_ack_o,
// instruction to issue logic, if issue_instr_valid and issue_ready is asserted, advance the issue pointer
// Issue scoreboard entry - ACC_DISPATCHER
output ariane_pkg::scoreboard_entry_t issue_instr_o,
output scoreboard_entry_t issue_instr_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic [31:0] orig_instr_o,
output logic [31:0] orig_instr_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic issue_instr_valid_o,
output logic issue_instr_valid_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic issue_ack_i,
input logic issue_ack_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input ariane_pkg::bp_resolve_t resolved_branch_i,
input bp_resolve_t resolved_branch_i,
// Transaction ID at which to write the result back - TO_BE_COMPLETED
input logic [CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i,
// Results to write back - TO_BE_COMPLETED
input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i,
// Exception from a functional unit (e.g.: ld/st exception) - TO_BE_COMPLETED
input ariane_pkg::exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i,
input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i,
// Indicates valid results - TO_BE_COMPLETED
input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i,
// Cvxif we for writeback - TO_BE_COMPLETED
@ -104,7 +107,7 @@ module scoreboard #(
typedef struct packed {
logic issued; // this bit indicates whether we issued this instruction e.g.: if it is valid
logic is_rd_fpr_flag; // redundant meta info, added for speed
ariane_pkg::scoreboard_entry_t sbe; // this is the score board entry we will send to ex
scoreboard_entry_t sbe; // this is the score board entry we will send to ex
} sb_mem_t;
sb_mem_t [ariane_pkg::NR_SB_ENTRIES-1:0] mem_q, mem_n;
@ -121,7 +124,7 @@ module scoreboard #(
assign sb_full_o = issue_full;
ariane_pkg::scoreboard_entry_t decoded_instr;
scoreboard_entry_t decoded_instr;
always_comb begin
decoded_instr = decoded_instr_i;
end

4
core/store_buffer.sv
View file

@ -17,7 +17,9 @@
module store_buffer
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

10
core/store_unit.sv
View file

@ -16,7 +16,11 @@
module store_unit
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type exception_t = logic,
parameter type lsu_ctrl_t = logic
) (
// Subsystem Clock - SUBSYSTEM
input logic clk_i,
@ -247,7 +251,9 @@ module store_unit
// Store Queue
// ---------------
store_buffer #(
.CVA6Cfg(CVA6Cfg)
.CVA6Cfg(CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t)
) store_buffer_i (
.clk_i,
.rst_ni,

1
corev_apu/fpga/src/ariane_xilinx.sv
View file

@ -161,6 +161,7 @@ localparam config_pkg::cva6_user_cfg_t CVA6UserCfg = '{
AxiDataWidth: cva6_config_pkg::CVA6ConfigAxiDataWidth,
AxiIdWidth: cva6_config_pkg::CVA6ConfigAxiIdWidth,
AxiUserWidth: cva6_config_pkg::CVA6ConfigDataUserWidth,
MemTidWidth: cva6_config_pkg::CVA6ConfigMemTidWidth,
NrLoadBufEntries: cva6_config_pkg::CVA6ConfigNrLoadBufEntries,
RASDepth: cva6_config_pkg::CVA6ConfigRASDepth,
BTBEntries: cva6_config_pkg::CVA6ConfigBTBEntries,