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Removed flush issue from scoreboard

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If an branch instruction is issued the consecutive instruction can't
enter until the branch is resolved.
This commit is contained in:
Florian Zaruba 2017-06-21 14:46:34 +02:00
parent de2fced8c4
commit 332c048b8a
5 changed files with 6 additions and 8 deletions
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2
src/ariane.sv
View file

@ -247,7 +247,6 @@ module ariane
if_stage if_stage_i (
.flush_i ( flush_ctrl_if ),
.if_busy_o ( if_ready_if_pcgen ),
.id_ready_i ( ready_id_if ),
.fetch_address_i ( fetch_address_pcgen_if ),
.fetch_valid_i ( fetch_valid_pcgen_if ),
.branch_predict_i ( branch_predict_pcgen_if ),
@ -279,7 +278,6 @@ module ariane
.fetch_entry_i ( fetch_entry_if_id ),
.fetch_entry_valid_i ( fetch_valid_if_id ),
.decoded_instr_ack_o ( decode_ack_id_if ),
.ready_o ( ready_id_if ),
.priv_lvl_i ( priv_lvl ),
.tvm_i ( tvm_csr_id ),
.tw_i ( tw_csr_id ),

4
src/fetch_fifo.sv
View file

@ -143,7 +143,7 @@ module fetch_fifo
// check if the instruction is compressed
if (in_rdata_q[1:0] != 2'b11) begin
// it is compressed
mem_n[write_pointer_q] = {
mem_n[write_pointer_q] = {
branch_predict_q, ex_q, in_addr_q, decompressed_instruction[0], 1'b1, is_illegal[0]
};
@ -158,7 +158,7 @@ module fetch_fifo
// but only if we predicted it to be taken, the predict was on the lower 16 bit compressed instruction
if (in_rdata_q[17:16] != 2'b11 && !(branch_predict_q.valid && branch_predict_q.predict_taken && branch_predict_q.is_lower_16)) begin
mem_n[write_pointer_q + 1'b1] = {
mem_n[write_pointer_q + 1'b1] = {
branch_predict_q, ex_q, {in_addr_q[63:2], 2'b10}, decompressed_instruction[1], 1'b1, is_illegal[1]
};

5
src/id_stage.sv
View file

@ -39,7 +39,6 @@ module id_stage #(
input logic tw_i,
input logic tsr_i,
output logic ready_o, // id is ready
output fu_t fu_o,
output fu_op operator_o,
output logic [63:0] operand_a_o,
@ -84,6 +83,7 @@ module id_stage #(
// Global signals
// ---------------------------------------------------
logic full;
logic decode_instr_ack;
// ---------------------------------------------------
// Scoreboard (SB) <-> Issue and Read Operands (iro)
// ---------------------------------------------------
@ -133,7 +133,7 @@ module id_stage #(
end
// we are ready if we are not full and don't have any unresolved branches, but it can be
// the case that we have an unresolved branch which is cleared in that cycle (resolved_branch_i.valid == 1)
assign ready_o = ~full && (~unresolved_branch_q || resolve_branch_i);
assign decoded_instr_ack_o = decode_instr_ack && !unresolved_branch_q;
decoder decoder_i (
.pc_i ( fetch_entry_i.address ),
@ -163,6 +163,7 @@ module id_stage #(
.rs2_valid_o ( rs2_valid_iro_sb ),
.commit_instr_o ( commit_instr_o ),
.commit_ack_i ( commit_ack_i ),
.decoded_instr_ack_o ( decode_instr_ack ),
.decoded_instr_i ( decoded_instr_dc_sb ),
.decoded_instr_valid_i ( fetch_entry_valid_i ),
.issue_instr_o ( issue_instr_sb_iro ),

1
src/if_stage.sv
View file

@ -24,7 +24,6 @@ module if_stage (
// control signals
input logic flush_i,
output logic if_busy_o, // is the IF stage busy fetching instructions?
input logic id_ready_i, // ID stage is ready
// fetch direction from PC Gen
input logic [63:0] fetch_address_i, // address to fetch from
input logic fetch_valid_i, // the fetch address is valid

2
src/scoreboard.sv
View file

@ -87,7 +87,7 @@ module scoreboard #(
issue_instr_o = decoded_instr_i;
// make sure we assign the correct trans ID
issue_instr_o.trans_id = issue_pointer_q;
issue_instr_valid_o = ~issue_full && decoded_instr_valid_i && !flush_unissued_instr_i;
issue_instr_valid_o = !issue_full && decoded_instr_valid_i;
decoded_instr_ack_o = issue_ack_i;
end
// maintain a FIFO with issued instructions