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🐛 Fix in branch delay slot instruction taken

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This commit is contained in:
Florian Zaruba 2017-06-21 19:23:21 +02:00
parent f6f33eafaf
commit 34519aa8d0
5 changed files with 20 additions and 20 deletions
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2
src/ariane.sv
View file

@ -276,7 +276,7 @@ module ariane
// ID
// ---------
id_stage id_stage_i (
.flush_i ( flush_ctrl_id ),
.flush_i ( flush_ctrl_if ),
.fetch_entry_i ( fetch_entry_if_id ),
.fetch_entry_valid_i ( fetch_valid_if_id ),
.decoded_instr_ack_o ( decode_ack_id_if ),

3
src/id_stage.sv
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@ -74,11 +74,12 @@ module id_stage (
issue_n = issue_q;
decoded_instr_ack_o = 1'b0;
if (issue_instr_ack_i)
issue_n.valid = 1'b0;
// if we have a space in the register and the fetch is valid, go get it
if (!issue_q.valid && fetch_entry_valid_i) begin
decoded_instr_ack_o = 1'b1;
issue_n = { 1'b1, decoded_instruction, is_control_flow_instr};
issue_n.valid = 1'b1;
end
// we have something in the register but issue stage already acknowledged

13
src/issue_stage.sv
View file

@ -77,12 +77,6 @@ module issue_stage #(
output scoreboard_entry commit_instr_o,
input logic commit_ack_i
);
// ---------------------------------------------------
// Global signals
// ---------------------------------------------------
logic full;
logic decoded_instr_ack;
// ---------------------------------------------------
// Scoreboard (SB) <-> Issue and Read Operands (IRO)
// ---------------------------------------------------
@ -123,9 +117,6 @@ module issue_stage #(
unresolved_branch_n = 1'b0;
end
end
// we are ready if we are not full and don't have any unresolved branches, but it can be
// the case that we have an unresolved branch which is cleared in that cycle (resolved_branch_i == 1)
assign decoded_instr_ack_o = ~full && (~unresolved_branch_q) && decoded_instr_ack;
issue_read_operands issue_read_operands_i (
.flush_i ( flush_unissued_instr_i ),
@ -148,7 +139,7 @@ module issue_stage #(
)
scoreboard_i
(
.full_o ( full ),
.unresolved_branch_i ( unresolved_branch_q ),
.rd_clobber_o ( rd_clobber_sb_iro ),
.rs1_i ( rs1_iro_sb ),
.rs1_o ( rs1_sb_iro ),
@ -157,8 +148,6 @@ module issue_stage #(
.rs2_o ( rs2_sb_iro ),
.rs2_valid_o ( rs2_valid_iro_sb ),
.decoded_instr_ack_o ( decoded_instr_ack ),
.issue_instr_o ( issue_instr_sb_iro ),
.issue_instr_valid_o ( issue_instr_valid_sb_iro ),
.issue_ack_i ( issue_ack_iro_sb ),

11
src/scoreboard.sv
View file

@ -27,9 +27,8 @@ module scoreboard #(
(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
output logic full_o, // We can't take anymore data
input logic flush_i, // flush whole scoreboard
input logic flush_unissued_instr_i,
input logic unresolved_branch_i, // we have an unresolved branch
// list of clobbered registers to issue stage
output fu_t [31:0] rd_clobber_o,
@ -78,7 +77,7 @@ module scoreboard #(
// the issue queue is full don't issue any new instructions
assign issue_full = (issue_cnt_q == NR_ENTRIES-1);
assign full_o = issue_full;
// output commit instruction directly
assign commit_instr_o = mem_q[commit_pointer_q].sbe;
@ -87,7 +86,9 @@ module scoreboard #(
issue_instr_o = decoded_instr_i;
// make sure we assign the correct trans ID
issue_instr_o.trans_id = issue_pointer_q;
issue_instr_valid_o = decoded_instr_valid_i;
// we are ready if we are not full and don't have any unresolved branches, but it can be
// the case that we have an unresolved branch which is cleared in that cycle (resolved_branch_i == 1)
issue_instr_valid_o = decoded_instr_valid_i && !unresolved_branch_i && !issue_full;
decoded_instr_ack_o = issue_ack_i;
end
@ -101,7 +102,7 @@ module scoreboard #(
issue_pointer_n = issue_pointer_q;
// if we got a acknowledge from the issue stage, put this scoreboard entry in the queue
if (issue_ack_i) begin
if (issue_instr_valid_o) begin
// the decoded instruction we put in there is valid (1st bit)
// increase the issue counter
issue_cnt++;

11
tb/wave/wave_core.do
View file

@ -1,12 +1,18 @@
add wave -noupdate -group core /core_tb/dut/*
add wave -noupdate -group pcgen_stage -group btb /core_tb/dut/pcgen_i/btb_i/*
add wave -noupdate -group pcgen_stage /core_tb/dut/pcgen_i/*
add wave -noupdate -group if_stage -group fetch_fifo /core_tb/dut/if_stage_i/fetch_fifo_i/*
add wave -noupdate -group if_stage /core_tb/dut/if_stage_i/*
add wave -noupdate -group id_stage -group decoder /core_tb/dut/id_stage_i/decoder_i/*
add wave -noupdate -group id_stage /core_tb/dut/id_stage_i/*
add wave -noupdate -group issue_stage -group scoreboard /core_tb/dut/issue_stage_i/scoreboard_i/*
add wave -noupdate -group issue_stage -group issue_read_operands /core_tb/dut/issue_stage_i/issue_read_operands_i/*
add wave -noupdate -group id_stage /core_tb/dut/id_stage_i/*
add wave -noupdate -group issue_stage /core_tb/dut/issue_stage_i/*
add wave -noupdate -group ex_stage -group alu /core_tb/dut/ex_stage_i/alu_i/*
add wave -noupdate -group ex_stage -group lsu -group mmu /core_tb/dut/ex_stage_i/lsu_i/mmu_i/*
add wave -noupdate -group ex_stage -group lsu -group mmu -group itlb /core_tb/dut/ex_stage_i/lsu_i/mmu_i/itlb_i/*
@ -23,6 +29,9 @@ add wave -noupdate -group ex_stage -group lsu -group lsu_arbiter /core_tb/dut/ex
add wave -noupdate -group ex_stage -group branch_unit /core_tb/dut/ex_stage_i/branch_unit_i/*
add wave -noupdate -group ex_stage -group csr_buffer /core_tb/dut/ex_stage_i/csr_buffer_i/*
add wave -noupdate -group ex_stage /core_tb/dut/ex_stage_i/*
add wave -noupdate -group commit_stage /core_tb/dut/commit_stage_i/*
add wave -noupdate -group csr_file /core_tb/dut/csr_regfile_i/*
add wave -noupdate -group controller /core_tb/dut/controller_i/*