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Replace SyncDpRam by tc_ram (#861)

Browse source 
Signed-off-by: Jean-Roch Coulon  <jean-roch.coulon@thalesgroup.com>
This commit is contained in:
JeanRochCoulon 2022-04-28 20:13:55 +02:00 • committed by GitHub
parent c318548f22
commit 35f430d8c6
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
17 changed files with 193 additions and 423 deletions
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17
Makefile
View file

@ -110,7 +110,6 @@ ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
util := core/include/instr_tracer_pkg.sv \
common/local/util/instr_tracer_if.sv \
common/local/util/instr_tracer.sv \
corev_apu/src/tech_cells_generic/src/cluster_clock_gating.sv \
corev_apu/tb/common/mock_uart.sv \
common/local/util/sram.sv
@ -187,9 +186,6 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
corev_apu/riscv-dbg/debug_rom/debug_rom.sv \
corev_apu/register_interface/src/apb_to_reg.sv \
corev_apu/axi/src/axi_multicut.sv \
common/submodules/common_cells/src/deprecated/generic_fifo.sv \
common/submodules/common_cells/src/deprecated/pulp_sync.sv \
common/submodules/common_cells/src/deprecated/find_first_one.sv \
common/submodules/common_cells/src/rstgen_bypass.sv \
common/submodules/common_cells/src/rstgen.sv \
common/submodules/common_cells/src/stream_mux.sv \
@ -207,7 +203,6 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
corev_apu/axi/src/axi_mux.sv \
corev_apu/axi/src/axi_demux.sv \
corev_apu/axi/src/axi_xbar.sv \
corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv \
common/submodules/common_cells/src/unread.sv \
common/submodules/common_cells/src/sync.sv \
common/submodules/common_cells/src/cdc_2phase.sv \
@ -231,9 +226,11 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
common/submodules/common_cells/src/delta_counter.sv \
common/submodules/common_cells/src/counter.sv \
common/submodules/common_cells/src/shift_reg.sv \
corev_apu/src/tech_cells_generic/src/pulp_clock_gating.sv \
corev_apu/src/tech_cells_generic/src/cluster_clock_inverter.sv \
corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv \
corev_apu/src/tech_cells_generic/src/deprecated/cluster_clk_cells.sv \
corev_apu/src/tech_cells_generic/src/deprecated/pulp_clk_cells.sv \
common/local/util/tc_sram_wrapper.sv \
corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv \
corev_apu/src/tech_cells_generic/src/rtl/tc_clk.sv \
corev_apu/tb/ariane_testharness.sv \
corev_apu/tb/ariane_peripherals.sv \
corev_apu/tb/rvfi_tracer.sv \
@ -257,7 +254,7 @@ copro_src := $(addprefix $(root-dir), $(copro_src))
uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/*.vhd)
uart_src := $(addprefix $(root-dir), $(uart_src))
fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv)
fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) corev_apu/src/tech_cells_generic/src/fpga/tc_sram_xilinx.sv common/local/util/tc_sram_xilinx_wrapper.sv
fpga_src := $(addprefix $(root-dir), $(fpga_src))
# look for testbenches
@ -770,6 +767,8 @@ fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv)
fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv)
fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer_if.sv)
fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer.sv)
fpga_filter += $(addprefix $(root-dir), corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv)
fpga_filter += $(addprefix $(root-dir), common/local/util/tc_sram_wrapper.sv)
fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src) $(copro_src)
@echo "[FPGA] Generate sources"

67
common/local/util/sram.sv
View file

@ -23,6 +23,7 @@ module sram #(
parameter USER_WIDTH = 1,
parameter USER_EN = 0,
parameter NUM_WORDS = 1024,
parameter SIM_INIT = "none",
parameter OUT_REGS = 0, // enables output registers in FPGA macro (read lat = 2)
parameter DROMAJO_RAM = 0
)(
@ -95,40 +96,42 @@ end
end
end else begin : gen_mem
// unused byte-enable segments (8bits) are culled by the tool
SyncSpRamBeNx64 #(
.ADDR_WIDTH($clog2(NUM_WORDS)),
.DATA_DEPTH(NUM_WORDS),
.OUT_REGS (0),
// this initializes the memory with 0es. adjust to taste...
// 0: no init, 1: zero init, 2: random init, 3: deadbeef init
.SIM_INIT (1)
) i_ram (
.Clk_CI ( clk_i ),
.Rst_RBI ( rst_ni ),
.CSel_SI ( req_i ),
.WrEn_SI ( we_i ),
.BEn_SI ( be_aligned[k*8 +: 8] ),
.WrData_DI ( wdata_aligned[k*64 +: 64] ),
.Addr_DI ( addr_i ),
.RdData_DO ( rdata_aligned[k*64 +: 64] )
tc_sram_wrapper #(
.NumWords(NUM_WORDS), // Number of Words in data array
.DataWidth(64), // Data signal width
.ByteWidth(32'd8), // Width of a data byte
.NumPorts(32'd1), // Number of read and write ports
.Latency(32'd1), // Latency when the read data is available
.SimInit(SIM_INIT), // Simulation initialization
.PrintSimCfg(1'b0) // Print configuration
) i_tc_sram_wrapper (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req_i ),
.we_i ( we_i ),
.be_i ( be_aligned[k*8 +: 8] ),
.wdata_i ( wdata_aligned[k*64 +: 64] ),
.addr_i ( addr_i ),
.rdata_o ( rdata_aligned[k*64 +: 64] )
);
if (USER_EN) begin : gen_mem_user
SyncSpRamBeNx64 #(
.ADDR_WIDTH($clog2(NUM_WORDS)),
.DATA_DEPTH(NUM_WORDS),
.OUT_REGS (0),
// this initializes the memory with 0es. adjust to taste...
// 0: no init, 1: zero init, 2: random init, 3: deadbeef init
.SIM_INIT (1)
) i_ram_user (
.Clk_CI ( clk_i ),
.Rst_RBI ( rst_ni ),
.CSel_SI ( req_i ),
.WrEn_SI ( we_i ),
.BEn_SI ( be_aligned[k*8 +: 8] ),
.WrData_DI ( wuser_aligned[k*64 +: 64] ),
.Addr_DI ( addr_i ),
.RdData_DO ( ruser_aligned[k*64 +: 64] )
tc_sram_wrapper #(
.NumWords(NUM_WORDS), // Number of Words in data array
.DataWidth(64), // Data signal width
.ByteWidth(32'd8), // Width of a data byte
.NumPorts(32'd1), // Number of read and write ports
.Latency(32'd1), // Latency when the read data is available
.SimInit(SIM_INIT), // Simulation initialization
.PrintSimCfg(1'b0) // Print configuration
) i_tc_sram_wrapper_user (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req_i ),
.we_i ( we_i ),
.be_i ( be_aligned[k*8 +: 8] ),
.wdata_i ( wuser_aligned[k*64 +: 64] ),
.addr_i ( addr_i ),
.rdata_o ( ruser_aligned[k*64 +: 64] )
);
end
end

60
common/local/util/tc_sram_wrapper.sv Normal file
View file

@ -0,0 +1,60 @@
// Copyright 2022 Thales DIS design services SAS
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
module tc_sram_wrapper #(
parameter int unsigned NumWords = 32'd1024, // Number of Words in data array
parameter int unsigned DataWidth = 32'd128, // Data signal width
parameter int unsigned ByteWidth = 32'd8, // Width of a data byte
parameter int unsigned NumPorts = 32'd2, // Number of read and write ports
parameter int unsigned Latency = 32'd1, // Latency when the read data is available
parameter SimInit = "none", // Simulation initialization
parameter bit PrintSimCfg = 1'b0, // Print configuration
// DEPENDENT PARAMETERS, DO NOT OVERWRITE!
parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div
parameter type addr_t = logic [AddrWidth-1:0],
parameter type data_t = logic [DataWidth-1:0],
parameter type be_t = logic [BeWidth-1:0]
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// input ports
input logic [NumPorts-1:0] req_i, // request
input logic [NumPorts-1:0] we_i, // write enable
input addr_t [NumPorts-1:0] addr_i, // request address
input data_t [NumPorts-1:0] wdata_i, // write data
input be_t [NumPorts-1:0] be_i, // write byte enable
// output ports
output data_t [NumPorts-1:0] rdata_o // read data
);
// synthesis translate_off
tc_sram #(
.NumWords(NumWords),
.DataWidth(DataWidth),
.ByteWidth(ByteWidth),
.NumPorts(NumPorts),
.Latency(Latency),
.SimInit(SimInit),
.PrintSimCfg(PrintSimCfg)
) i_tc_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req_i ),
.we_i ( we_i ),
.be_i ( be_i ),
.wdata_i ( wdata_i ),
.addr_i ( addr_i ),
.rdata_o ( rdata_o )
);
// synthesis translate_on
endmodule

58
common/local/util/tc_sram_xilinx_wrapper.sv Normal file
View file

@ -0,0 +1,58 @@
// Copyright 2022 Thales DIS design services SAS
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
module tc_sram_wrapper #(
parameter int unsigned NumWords = 32'd1024, // Number of Words in data array
parameter int unsigned DataWidth = 32'd128, // Data signal width
parameter int unsigned ByteWidth = 32'd8, // Width of a data byte
parameter int unsigned NumPorts = 32'd2, // Number of read and write ports
parameter int unsigned Latency = 32'd1, // Latency when the read data is available
parameter SimInit = "none", // Simulation initialization
parameter bit PrintSimCfg = 1'b0, // Print configuration
// DEPENDENT PARAMETERS, DO NOT OVERWRITE!
parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div
parameter type addr_t = logic [AddrWidth-1:0],
parameter type data_t = logic [DataWidth-1:0],
parameter type be_t = logic [BeWidth-1:0]
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
// input ports
input logic [NumPorts-1:0] req_i, // request
input logic [NumPorts-1:0] we_i, // write enable
input addr_t [NumPorts-1:0] addr_i, // request address
input data_t [NumPorts-1:0] wdata_i, // write data
input be_t [NumPorts-1:0] be_i, // write byte enable
// output ports
output data_t [NumPorts-1:0] rdata_o // read data
);
tc_sram #(
.NumWords(NumWords),
.DataWidth(DataWidth),
.ByteWidth(ByteWidth),
.NumPorts(NumPorts),
.Latency(Latency),
.SimInit(SimInit),
.PrintSimCfg(PrintSimCfg)
) i_tc_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req_i ),
.we_i ( we_i ),
.be_i ( be_i ),
.wdata_i ( wdata_i ),
.addr_i ( addr_i ),
.rdata_o ( rdata_o )
);
endmodule

3
core/Flist.cv32a6_imac_sv0
View file

@ -41,7 +41,6 @@ ${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
// Packages
@ -146,6 +145,8 @@ ${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
// Tracer (behavioral code, not RTL)
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv
// MMU Sv32

3
core/Flist.cv32a6_imac_sv32
View file

@ -41,7 +41,6 @@ ${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
// Packages
@ -146,6 +145,8 @@ ${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
// Tracer (behavioral code, not RTL)
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv
// MMU Sv32

3
core/Flist.cv32a6_imafc_sv32
View file

@ -41,7 +41,6 @@ ${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
// Packages
@ -146,6 +145,8 @@ ${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
// Tracer (behavioral code, not RTL)
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv
// MMU Sv32

3
core/Flist.cv64a6_imafdc_sv39
View file

@ -41,7 +41,6 @@ ${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
// Packages
@ -153,6 +152,8 @@ ${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
// Tracer (behavioral code, not RTL)
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv
// MMU Sv39

3
core/Flist.cv64a6_imafdc_sv39_gate
View file

@ -24,4 +24,5 @@ ${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
${LIB_VERILOG}
${CVA6_REPO_DIR}/pd/synth/ariane_synth_modified.v
${CVA6_REPO_DIR}/pd/synth/SyncSpRamBeNx64_1.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv

2
corev_apu/src/tech_cells_generic

@ -1 +1 @@
Subproject commit ffe7818dc24eba29cf3634d404d1b3b85034272b
Subproject commit 8283d6c020d38a032f972988cfd79a952b54d309

4
corev_apu/tb/ariane_tb.cpp
View file

@ -320,8 +320,8 @@ done_processing:
// Preload memory.
size_t mem_size = 0xFFFFFF;
memif.read(0x80000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__i_ram__DOT__Mem_DP);
// memif.read(0x84000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__gen_mem_user__DOT__i_ram_user__DOT__Mem_DP);
memif.read(0x80000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__i_tc_sram_wrapper__DOT__i_tc_sram__DOT__sram);
// memif.read(0x84000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__gen_mem_user__DOT__i_ram_user__DOT__sram);
#ifndef DROMAJO
while (!dtm->done() && !jtag->done()) {

8
corev_apu/tb/ariane_tb.sv
View file

@ -19,8 +19,8 @@ import uvm_pkg::*;
`include "uvm_macros.svh"
`define MAIN_MEM(P) dut.i_sram.gen_cut[0].gen_mem.i_ram.Mem_DP[(``P``)]
// `define USER_MEM(P) dut.i_sram.gen_user_cut[0].gen_user_mem.i_ram_user.Mem_DP[(``P``)]
`define MAIN_MEM(P) dut.i_sram.gen_cut[0].gen_mem.i_tc_sram_wrapper.i_tc_sram.init_val[(``P``)]
// `define USER_MEM(P) dut.i_sram.gen_user_cut[0].gen_user_mem.i_ram_user.sram[(``P``)]
import "DPI-C" function read_elf(input string filename);
import "DPI-C" function byte get_section(output longint address, output longint len);
@ -34,7 +34,7 @@ module ariane_tb;
// toggle with RTC period
localparam int unsigned RTC_CLOCK_PERIOD = 30.517us;
localparam NUM_WORDS = 2**25;
localparam NUM_WORDS = 2**16;
logic clk_i;
logic rst_ni;
logic rtc_i;
@ -131,7 +131,7 @@ module ariane_tb;
void'(read_elf(binary));
// wait with preloading, otherwise randomization will overwrite the existing value
wait(rst_ni);
wait(clk_i);
// while there are more sections to process
while (get_section(address, len)) begin

5
corev_apu/tb/ariane_testharness.sv
View file

@ -452,6 +452,11 @@ module ariane_testharness #(
.DATA_WIDTH ( AXI_DATA_WIDTH ),
.USER_WIDTH ( AXI_USER_WIDTH ),
.USER_EN ( AXI_USER_EN ),
`ifdef VERILATOR
.SIM_INIT ( "none" ),
`else
.SIM_INIT ( "zeros" ),
`endif
`ifdef DROMAJO
.DROMAJO_RAM (1),
`endif

4
pd/synth/Makefile
View file

@ -29,14 +29,14 @@ ifndef TECH_NAME
endif
pre_cva6_synth:
grep "CVA6_REPO_DIR\}" ../../core/Flist.$(TARGET)|grep -v "instr_tracer"|grep -v "incdir"|grep -v "SyncSpRamBeNx64" > Flist.cva6_synth
grep "CVA6_REPO_DIR\}" ../../core/Flist.$(TARGET)|grep -v "instr_tracer"|grep -v "incdir" > Flist.cva6_synth
sed -i "s/^/analyze -f sverilog -define {WT_DCACHE,RVFI_TRACE} -lib ariane_lib /" Flist.cva6_synth
echo "analyze -f sverilog -define WT_DCACHE -lib ariane_lib SyncSpRamBeNx64.sv" >> Flist.cva6_synth
cva6_synth: pre_cva6_synth
@echo $(PERIOD)
@export $(EXPORT_LIST); $(DC_SHELL_PATH)/dc_shell -f ./cva6_synth.tcl -output synthesis_batch.log
python scripts/gate_analysis.py '$(DESIGN_NAME)/reports/$(PERIOD)/$(DESIGN_NAME)_$(TECH_NAME)_synth_area.rpt' $(NAND2_AREA)
sed 's/tc_sram_256_64_00000008_00000001_00000001_none_0 gen/tc_sram gen/' ariane_synth.v > ariane_synth_modified.v
cva6_read:
@export $(EXPORT_LIST); $(DC_SHELL_PATH)/dc_shell -f cva6_read.tcl -gui

180
pd/synth/SyncSpRamBeNx64.sv
View file

@ -1,180 +0,0 @@
// Copyright 2014 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
/**
* Inferable, Synchronous Single-Port N x 64bit RAM with Byte-Wise Enable
*
* This module contains an implementation for either Xilinx or Altera FPGAs. To synthesize for
* Xilinx, define `FPGA_TARGET_XILINX`. To synthesize for Altera, define `FPGA_TARGET_ALTERA`. The
* implementations follow the respective guidelines:
* - Xilinx UG901 Vivado Design Suite User Guide: Synthesis (p. 106)
* - Altera Quartus II Handbook Volume 1: Design and Synthesis (p. 768)
*
* Current Maintainers:
* - Michael Schaffner <schaffer@iis.ee.ethz.ch>
*/
`ifndef FPGA_TARGET_ALTERA
`define FPGA_TARGET_XILINX
`endif
module SyncSpRamBeNx64
#(
parameter ADDR_WIDTH = 10,
parameter DATA_DEPTH = 1024, // usually 2**ADDR_WIDTH, but can be lower
parameter OUT_REGS = 0, // set to 1 to enable outregs
parameter SIM_INIT = 0 // for simulation only, will not be synthesized
// 0: no init, 1: zero init, 2: random init, 3: deadbeef init
// note: on verilator, 2 is not supported. define the VERILATOR macro to work around.
)(
input logic Clk_CI,
input logic Rst_RBI,
input logic CSel_SI,
input logic WrEn_SI,
input logic [7:0] BEn_SI,
input logic [63:0] WrData_DI,
input logic [ADDR_WIDTH-1:0] Addr_DI,
output logic [63:0] RdData_DO
);
// synthesis translate_off
////////////////////////////
// signals, localparams
////////////////////////////
// needs to be consistent with the Altera implemenation below
localparam DATA_BYTES = 8;
logic [DATA_BYTES*8-1:0] RdData_DN;
logic [DATA_BYTES*8-1:0] RdData_DP;
////////////////////////////
// XILINX implementation
////////////////////////////
`ifdef FPGA_TARGET_XILINX
logic [DATA_BYTES*8-1:0] Mem_DP[DATA_DEPTH-1:0];
always_ff @(posedge Clk_CI) begin
//pragma translate_off
automatic logic [63:0] val;
if(Rst_RBI == 1'b0 && SIM_INIT>0) begin
for(int k=0; k<DATA_DEPTH;k++) begin
if(SIM_INIT==1) val = '0;
`ifndef VERILATOR
else if(SIM_INIT==2) void'(randomize(val));
`endif
else val = 64'hdeadbeefdeadbeef;
Mem_DP[k] = val;
end
end else
//pragma translate_on
if(CSel_SI) begin
if(WrEn_SI) begin
if(BEn_SI[0]) Mem_DP[Addr_DI][7:0] <= WrData_DI[7:0];
if(BEn_SI[1]) Mem_DP[Addr_DI][15:8] <= WrData_DI[15:8];
if(BEn_SI[2]) Mem_DP[Addr_DI][23:16] <= WrData_DI[23:16];
if(BEn_SI[3]) Mem_DP[Addr_DI][31:24] <= WrData_DI[31:24];
if(BEn_SI[4]) Mem_DP[Addr_DI][39:32] <= WrData_DI[39:32];
if(BEn_SI[5]) Mem_DP[Addr_DI][47:40] <= WrData_DI[47:40];
if(BEn_SI[6]) Mem_DP[Addr_DI][55:48] <= WrData_DI[55:48];
if(BEn_SI[7]) Mem_DP[Addr_DI][63:56] <= WrData_DI[63:56];
end
RdData_DN <= Mem_DP[Addr_DI];
end
end
`endif
////////////////////////////
// ALTERA implementation
////////////////////////////
`ifdef FPGA_TARGET_ALTERA
logic [DATA_BYTES-1:0][7:0] Mem_DP[0:DATA_DEPTH-1];
always_ff @(posedge Clk_CI) begin
//pragma translate_off
automatic logic [63:0] val;
if(Rst_RBI == 1'b0 && SIM_INIT>0) begin
for(int k=0; k<DATA_DEPTH;k++) begin
if(SIM_INIT==1) val = '0;
`ifndef VERILATOR
else if(SIM_INIT==2) void'(randomize(val));
`endif
else val = 64'hdeadbeefdeadbeef;
Mem_DP[k] = val;
end
end else
//pragma translate_on
if(CSel_SI) begin
if(WrEn_SI) begin // needs to be static, otherwise Altera wont infer it
if(BEn_SI[0]) Mem_DP[Addr_DI][0] <= WrData_DI[7:0];
if(BEn_SI[1]) Mem_DP[Addr_DI][1] <= WrData_DI[15:8];
if(BEn_SI[2]) Mem_DP[Addr_DI][2] <= WrData_DI[23:16];
if(BEn_SI[3]) Mem_DP[Addr_DI][3] <= WrData_DI[31:24];
if(BEn_SI[4]) Mem_DP[Addr_DI][4] <= WrData_DI[39:32];
if(BEn_SI[5]) Mem_DP[Addr_DI][5] <= WrData_DI[47:40];
if(BEn_SI[6]) Mem_DP[Addr_DI][6] <= WrData_DI[55:48];
if(BEn_SI[7]) Mem_DP[Addr_DI][7] <= WrData_DI[63:56];
end
RdData_DN <= Mem_DP[Addr_DI];
end
end
`endif
////////////////////////////
// optional output regs
////////////////////////////
// output regs
generate
if (OUT_REGS>0) begin : g_outreg
always_ff @(posedge Clk_CI or negedge Rst_RBI) begin
if(Rst_RBI == 1'b0)
begin
RdData_DP <= 0;
end
else
begin
RdData_DP <= RdData_DN;
end
end
end
endgenerate // g_outreg
// output reg bypass
generate
if (OUT_REGS==0) begin : g_oureg_byp
assign RdData_DP = RdData_DN;
end
endgenerate// g_oureg_byp
assign RdData_DO = RdData_DP;
////////////////////////////
// assertions
////////////////////////////
// pragma translate_off
assert property
(@(posedge Clk_CI) (longint'(2)**longint'(ADDR_WIDTH) >= longint'(DATA_DEPTH)))
else $error("depth out of bounds");
// pragma translate_on
`ifndef FPGA_TARGET_XILINX
`ifndef FPGA_TARGET_ALTERA
$error("FPGA target not defined, define FPGA_TARGET_XILINX or FPGA_TARGET_ALTERA.");
`endif
`endif
// synthesis translate_on
endmodule // SyncSpRamBeNx64

180
pd/synth/SyncSpRamBeNx64_1.sv
View file

@ -1,180 +0,0 @@
// Copyright 2014 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
/**
* Inferable, Synchronous Single-Port N x 64bit RAM with Byte-Wise Enable
*
* This module contains an implementation for either Xilinx or Altera FPGAs. To synthesize for
* Xilinx, define `FPGA_TARGET_XILINX`. To synthesize for Altera, define `FPGA_TARGET_ALTERA`. The
* implementations follow the respective guidelines:
* - Xilinx UG901 Vivado Design Suite User Guide: Synthesis (p. 106)
* - Altera Quartus II Handbook Volume 1: Design and Synthesis (p. 768)
*
* Current Maintainers:
* - Michael Schaffner <schaffer@iis.ee.ethz.ch>
*/
`ifndef FPGA_TARGET_ALTERA
`define FPGA_TARGET_XILINX
`endif
module SyncSpRamBeNx64_1
#(
parameter ADDR_WIDTH = 10,
parameter DATA_DEPTH = 1024, // usually 2**ADDR_WIDTH, but can be lower
parameter OUT_REGS = 0, // set to 1 to enable outregs
parameter SIM_INIT = 0 // for simulation only, will not be synthesized
// 0: no init, 1: zero init, 2: random init, 3: deadbeef init
// note: on verilator, 2 is not supported. define the VERILATOR macro to work around.
)(
input logic clk_ci,
input logic rst_rbi,
input logic csel_si,
input logic wren_si,
input logic [7:0] ben_si,
input logic [63:0] wrdata_di,
input logic [ADDR_WIDTH-1:0] addr_di,
output logic [63:0] rddata_do
);
// synthesis translate_off
////////////////////////////
// signals, localparams
////////////////////////////
// needs to be consistent with the Altera implemenation below
localparam DATA_BYTES = 8;
logic [DATA_BYTES*8-1:0] RdData_DN;
logic [DATA_BYTES*8-1:0] RdData_DP;
////////////////////////////
// XILINX implementation
////////////////////////////
`ifdef FPGA_TARGET_XILINX
logic [DATA_BYTES*8-1:0] Mem_DP[DATA_DEPTH-1:0];
always_ff @(posedge clk_ci) begin
//pragma translate_off
automatic logic [63:0] val;
if(rst_rbi == 1'b0 && SIM_INIT>0) begin
for(int k=0; k<DATA_DEPTH;k++) begin
if(SIM_INIT==1) val = '0;
`ifndef VERILATOR
else if(SIM_INIT==2) void'(randomize(val));
`endif
else val = 64'hdeadbeefdeadbeef;
Mem_DP[k] = val;
end
end else
//pragma translate_on
if(csel_si) begin
if(wren_si) begin
if(ben_si[0]) Mem_DP[addr_di][7:0] <= wrdata_di[7:0];
if(ben_si[1]) Mem_DP[addr_di][15:8] <= wrdata_di[15:8];
if(ben_si[2]) Mem_DP[addr_di][23:16] <= wrdata_di[23:16];
if(ben_si[3]) Mem_DP[addr_di][31:24] <= wrdata_di[31:24];
if(ben_si[4]) Mem_DP[addr_di][39:32] <= wrdata_di[39:32];
if(ben_si[5]) Mem_DP[addr_di][47:40] <= wrdata_di[47:40];
if(ben_si[6]) Mem_DP[addr_di][55:48] <= wrdata_di[55:48];
if(ben_si[7]) Mem_DP[addr_di][63:56] <= wrdata_di[63:56];
end
RdData_DN <= Mem_DP[addr_di];
end
end
`endif
////////////////////////////
// ALTERA implementation
////////////////////////////
`ifdef FPGA_TARGET_ALTERA
logic [DATA_BYTES-1:0][7:0] Mem_DP[0:DATA_DEPTH-1];
always_ff @(posedge clk_ci) begin
//pragma translate_off
automatic logic [63:0] val;
if(rst_rbi == 1'b0 && SIM_INIT>0) begin
for(int k=0; k<DATA_DEPTH;k++) begin
if(SIM_INIT==1) val = '0;
`ifndef VERILATOR
else if(SIM_INIT==2) void'(randomize(val));
`endif
else val = 64'hdeadbeefdeadbeef;
Mem_DP[k] = val;
end
end else
//pragma translate_on
if(csel_si) begin
if(wren_si) begin // needs to be static, otherwise Altera wont infer it
if(ben_si[0]) Mem_DP[addr_di][0] <= wrdata_di[7:0];
if(ben_si[1]) Mem_DP[addr_di][1] <= wrdata_di[15:8];
if(ben_si[2]) Mem_DP[addr_di][2] <= wrdata_di[23:16];
if(ben_si[3]) Mem_DP[addr_di][3] <= wrdata_di[31:24];
if(ben_si[4]) Mem_DP[addr_di][4] <= wrdata_di[39:32];
if(ben_si[5]) Mem_DP[addr_di][5] <= wrdata_di[47:40];
if(ben_si[6]) Mem_DP[addr_di][6] <= wrdata_di[55:48];
if(ben_si[7]) Mem_DP[addr_di][7] <= wrdata_di[63:56];
end
RdData_DN <= Mem_DP[addr_di];
end
end
`endif
////////////////////////////
// optional output regs
////////////////////////////
// output regs
generate
if (OUT_REGS>0) begin : g_outreg
always_ff @(posedge clk_ci or negedge rst_rbi) begin
if(rst_rbi == 1'b0)
begin
RdData_DP <= 0;
end
else
begin
RdData_DP <= RdData_DN;
end
end
end
endgenerate // g_outreg
// output reg bypass
generate
if (OUT_REGS==0) begin : g_oureg_byp
assign RdData_DP = RdData_DN;
end
endgenerate// g_oureg_byp
assign rddata_do = RdData_DP;
////////////////////////////
// assertions
////////////////////////////
// pragma translate_off
assert property
(@(posedge clk_ci) (longint'(2)**longint'(ADDR_WIDTH) >= longint'(DATA_DEPTH)))
else $error("depth out of bounds");
// pragma translate_on
`ifndef FPGA_TARGET_XILINX
`ifndef FPGA_TARGET_ALTERA
$error("FPGA target not defined, define FPGA_TARGET_XILINX or FPGA_TARGET_ALTERA.");
`endif
`endif
// synthesis translate_on
endmodule // SyncSpRamBeNx64

16
pd/synth/cva6_synth.tcl
View file

@ -47,10 +47,10 @@ change_name -rule verilog -hier
set_fix_multiple_port_nets -all -buffer_constants
#constraint the timing to and from the sram black boxes
set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_ram/rddata_do[*]
set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_ram/rddata_do[*]
set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_ram/rddata_do[*]
set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_ram/rddata_do[*]
set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
set_input_delay -clock main_clk -max $input_delay i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
set_output_delay $output_delay -max -clock main_clk i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/addr_i[*]
set_output_delay $output_delay -max -clock main_clk i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/addr_i[*]
@ -69,10 +69,10 @@ write -format verilog -hierarchy -output ${DESIGN_NAME}_synth.v
write -format ddc -hierarchy -output ${DCRM_FINAL_DDC_OUTPUT_FILE}
report_timing -nworst 10 > ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_ram/rddata_do[*] >> ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_ram/rddata_do[*] >> ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_ram/rddata_do[*] >> ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_ram/rddata_do[*] >> ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_ram/rdata_o[*] >> ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}
report_timing -through i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/addr_i[*] >> ${DCRM_FINAL_TIMING_REPORT}