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Fix SuperScalar
config and add CVA6Cfg
to first pass decoder (#2047)
* Add `CVA6Cfg` to first pass decoder * Fix `verilator` `SELRANGE` warnings * Update core/decoder.sv Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> * Update core/cva6_accel_first_pass_decoder_stub.sv Co-authored-by: Côme <124148386+cathales@users.noreply.github.com> * Update core/decoder.sv Co-authored-by: Côme <124148386+cathales@users.noreply.github.com> * Update core/frontend/instr_queue.sv Co-authored-by: Côme <124148386+cathales@users.noreply.github.com> --------- Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
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parent
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commit
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3 changed files with 19 additions and 14 deletions
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@ -10,6 +10,7 @@
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module cva6_accel_first_pass_decoder
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import ariane_pkg::*;
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#(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = '0,
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parameter type scoreboard_entry_t = logic
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) (
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input logic [31:0] instruction_i, // instruction from IF
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@ -135,6 +135,7 @@ module decoder
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// identifying them, but also whether they read/write scalar registers.
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// Accelerators are supposed to define this module.
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cva6_accel_first_pass_decoder #(
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.CVA6Cfg(CVA6Cfg),
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.scoreboard_entry_t(scoreboard_entry_t)
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) i_accel_decoder (
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.instruction_i(instruction_i),
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@ -88,6 +88,9 @@ module instr_queue
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input logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_ready_i
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);
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// Calculate next index based on whether superscalar is enabled or not.
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localparam NID = ariane_pkg::SUPERSCALAR > 0 ? 1 : 0;
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typedef struct packed {
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logic [31:0] instr; // instruction word
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ariane_pkg::cf_t cf; // branch was taken
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@ -302,9 +305,9 @@ ariane_pkg::FETCH_FIFO_DEPTH
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// ----------------------
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// as long as there is at least one queue which can take the value we have a valid instruction
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assign fetch_entry_valid_o[0] = ~(&instr_queue_empty);
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if (ariane_pkg::SUPERSCALAR) begin : gen_fetch_entry_valid_1
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if (ariane_pkg::SUPERSCALAR > 0) begin : gen_fetch_entry_valid_1
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// TODO Maybe this additional fetch_entry_is_cf check is useless as issue-stage already performs it?
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assign fetch_entry_valid_o[1] = ~|(instr_queue_empty & idx_ds[1]) & ~(&fetch_entry_is_cf);
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assign fetch_entry_valid_o[NID] = ~|(instr_queue_empty & idx_ds[1]) & ~(&fetch_entry_is_cf);
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end
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assign idx_ds[0] = idx_ds_q;
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@ -364,26 +367,26 @@ ariane_pkg::FETCH_FIFO_DEPTH
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pop_instr[i] = fetch_entry_fire[0];
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end
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if (ariane_pkg::SUPERSCALAR) begin
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if (ariane_pkg::SUPERSCALAR > 0) begin
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if (idx_ds[1][i]) begin
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if (instr_data_out[i].ex == ariane_pkg::FE_INSTR_ACCESS_FAULT) begin
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fetch_entry_o[1].ex.cause = riscv::INSTR_ACCESS_FAULT;
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fetch_entry_o[NID].ex.cause = riscv::INSTR_ACCESS_FAULT;
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end else begin
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fetch_entry_o[1].ex.cause = riscv::INSTR_PAGE_FAULT;
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fetch_entry_o[NID].ex.cause = riscv::INSTR_PAGE_FAULT;
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end
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fetch_entry_o[1].instruction = instr_data_out[i].instr;
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fetch_entry_o[1].ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE;
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fetch_entry_o[1].ex.tval = {{64 - riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr};
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fetch_entry_o[1].branch_predict.cf = instr_data_out[i].cf;
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fetch_entry_o[NID].instruction = instr_data_out[i].instr;
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fetch_entry_o[NID].ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE;
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fetch_entry_o[NID].ex.tval = {{64 - riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr};
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fetch_entry_o[NID].branch_predict.cf = instr_data_out[i].cf;
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// Cannot output two CF the same cycle.
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pop_instr[i] = fetch_entry_fire[1];
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pop_instr[i] = fetch_entry_fire[NID];
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end
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end
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end
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// rotate the pointer left
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if (fetch_entry_fire[0]) begin
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if (ariane_pkg::SUPERSCALAR) begin
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idx_ds_d = fetch_entry_fire[1] ? idx_ds[2] : idx_ds[1];
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if (ariane_pkg::SUPERSCALAR > 0) begin
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idx_ds_d = fetch_entry_fire[NID] ? idx_ds[2] : idx_ds[1];
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end else begin
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idx_ds_d = idx_ds[1];
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end
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@ -445,8 +448,8 @@ ariane_pkg::FETCH_FIFO_DEPTH
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if (fetch_entry_fire[0]) begin
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pc_d = pc_j[1];
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if (ariane_pkg::SUPERSCALAR) begin
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if (fetch_entry_fire[1]) begin
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if (ariane_pkg::SUPERSCALAR > 0) begin
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if (fetch_entry_fire[NID]) begin
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pc_d = pc_j[2];
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end
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end
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