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Fix SuperScalar config and add CVA6Cfg to first pass decoder (#2047)

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* Add `CVA6Cfg` to first pass decoder

* Fix `verilator` `SELRANGE` warnings

* Update core/decoder.sv

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>

* Update core/cva6_accel_first_pass_decoder_stub.sv

Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>

* Update core/decoder.sv

Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>

* Update core/frontend/instr_queue.sv

Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>

---------

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
Co-authored-by: Côme <124148386+cathales@users.noreply.github.com>
This commit is contained in:
Florian Zaruba 2024-04-17 16:34:08 +02:00 • committed by GitHub
parent 82b2d15127
commit 377b0de154
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GPG key ID: B5690EEEBB952194
3 changed files with 19 additions and 14 deletions
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1
core/cva6_accel_first_pass_decoder_stub.sv
View file

@ -10,6 +10,7 @@
module cva6_accel_first_pass_decoder module cva6_accel_first_pass_decoder
import ariane_pkg::*; import ariane_pkg::*;
#( #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = '0,
parameter type scoreboard_entry_t = logic parameter type scoreboard_entry_t = logic
) ( ) (
input logic [31:0] instruction_i, // instruction from IF input logic [31:0] instruction_i, // instruction from IF

1
core/decoder.sv
View file

@ -135,6 +135,7 @@ module decoder
// identifying them, but also whether they read/write scalar registers. // identifying them, but also whether they read/write scalar registers.
// Accelerators are supposed to define this module. // Accelerators are supposed to define this module.
cva6_accel_first_pass_decoder #( cva6_accel_first_pass_decoder #(
.CVA6Cfg(CVA6Cfg),
.scoreboard_entry_t(scoreboard_entry_t) .scoreboard_entry_t(scoreboard_entry_t)
) i_accel_decoder ( ) i_accel_decoder (
.instruction_i(instruction_i), .instruction_i(instruction_i),

31
core/frontend/instr_queue.sv
View file

@ -88,6 +88,9 @@ module instr_queue
input logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_ready_i input logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_ready_i
); );
// Calculate next index based on whether superscalar is enabled or not.
localparam NID = ariane_pkg::SUPERSCALAR > 0 ? 1 : 0;
typedef struct packed { typedef struct packed {
logic [31:0] instr; // instruction word logic [31:0] instr; // instruction word
ariane_pkg::cf_t cf; // branch was taken ariane_pkg::cf_t cf; // branch was taken
@ -302,9 +305,9 @@ ariane_pkg::FETCH_FIFO_DEPTH
// ---------------------- // ----------------------
// as long as there is at least one queue which can take the value we have a valid instruction // as long as there is at least one queue which can take the value we have a valid instruction
assign fetch_entry_valid_o[0] = ~(&instr_queue_empty); assign fetch_entry_valid_o[0] = ~(&instr_queue_empty);
if (ariane_pkg::SUPERSCALAR) begin : gen_fetch_entry_valid_1 if (ariane_pkg::SUPERSCALAR > 0) begin : gen_fetch_entry_valid_1
// TODO Maybe this additional fetch_entry_is_cf check is useless as issue-stage already performs it? // TODO Maybe this additional fetch_entry_is_cf check is useless as issue-stage already performs it?
assign fetch_entry_valid_o[1] = ~|(instr_queue_empty & idx_ds[1]) & ~(&fetch_entry_is_cf); assign fetch_entry_valid_o[NID] = ~|(instr_queue_empty & idx_ds[1]) & ~(&fetch_entry_is_cf);
end end
assign idx_ds[0] = idx_ds_q; assign idx_ds[0] = idx_ds_q;
@ -364,26 +367,26 @@ ariane_pkg::FETCH_FIFO_DEPTH
pop_instr[i] = fetch_entry_fire[0]; pop_instr[i] = fetch_entry_fire[0];
end end
if (ariane_pkg::SUPERSCALAR) begin if (ariane_pkg::SUPERSCALAR > 0) begin
if (idx_ds[1][i]) begin if (idx_ds[1][i]) begin
if (instr_data_out[i].ex == ariane_pkg::FE_INSTR_ACCESS_FAULT) begin if (instr_data_out[i].ex == ariane_pkg::FE_INSTR_ACCESS_FAULT) begin
fetch_entry_o[1].ex.cause = riscv::INSTR_ACCESS_FAULT; fetch_entry_o[NID].ex.cause = riscv::INSTR_ACCESS_FAULT;
end else begin end else begin
fetch_entry_o[1].ex.cause = riscv::INSTR_PAGE_FAULT; fetch_entry_o[NID].ex.cause = riscv::INSTR_PAGE_FAULT;
end end
fetch_entry_o[1].instruction = instr_data_out[i].instr; fetch_entry_o[NID].instruction = instr_data_out[i].instr;
fetch_entry_o[1].ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE; fetch_entry_o[NID].ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE;
fetch_entry_o[1].ex.tval = {{64 - riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr}; fetch_entry_o[NID].ex.tval = {{64 - riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr};
fetch_entry_o[1].branch_predict.cf = instr_data_out[i].cf; fetch_entry_o[NID].branch_predict.cf = instr_data_out[i].cf;
// Cannot output two CF the same cycle. // Cannot output two CF the same cycle.
pop_instr[i] = fetch_entry_fire[1]; pop_instr[i] = fetch_entry_fire[NID];
end end
end end
end end
// rotate the pointer left // rotate the pointer left
if (fetch_entry_fire[0]) begin if (fetch_entry_fire[0]) begin
if (ariane_pkg::SUPERSCALAR) begin if (ariane_pkg::SUPERSCALAR > 0) begin
idx_ds_d = fetch_entry_fire[1] ? idx_ds[2] : idx_ds[1]; idx_ds_d = fetch_entry_fire[NID] ? idx_ds[2] : idx_ds[1];
end else begin end else begin
idx_ds_d = idx_ds[1]; idx_ds_d = idx_ds[1];
end end
@ -445,8 +448,8 @@ ariane_pkg::FETCH_FIFO_DEPTH
if (fetch_entry_fire[0]) begin if (fetch_entry_fire[0]) begin
pc_d = pc_j[1]; pc_d = pc_j[1];
if (ariane_pkg::SUPERSCALAR) begin if (ariane_pkg::SUPERSCALAR > 0) begin
if (fetch_entry_fire[1]) begin if (fetch_entry_fire[NID]) begin
pc_d = pc_j[2]; pc_d = pc_j[2];
end end
end end