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Merge branch 'ariane_next' into fpnew

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Florian Zaruba 2018-09-13 18:21:49 +02:00
commit 39a8935d55
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25 changed files with 543 additions and 263 deletions
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59
.gitlab-ci.yml
View file

@ -1,77 +1,84 @@
before_script:
- export CXX=g++-4.8.3 CC=gcc-4.8.3
# paths to local or network installation (the riscv toolchain and
# verilator are not built in a ci job in this case)
- export QUESTASIM_HOME=/scratch/$USER/questasim
- export CXX=g++-7 CC=gcc-7
# paths to local or network installations (the riscv toolchain and
# verilator are not built in the ci job as in travis)
- export QUESTASIM_HOME=
- export QUESTASIM_VERSION=
- export RISCV=/scratch/$USER/riscv_install
- export VERILATOR_ROOT=/scratch/$USER/verilator-3.924
- export QUESTASIM_FLAGS=
- export RISCV=/scratch/$USER/projects/riscv_install
- export VERILATOR_ROOT=/scratch/$USER/projects/verilator-3.924
# setup dependent paths
- export PATH=${RISCV}/bin:$VERILATOR_ROOT/bin:${PATH}
- export LIBRARY_PATH=$CI_PROJECT_DIR/tmp/lib
- export LD_LIBRARY_PATH=$CI_PROJECT_DIR/tmp/lib
- export C_INCLUDE_PATH=$CI_PROJECT_DIR/tmp/include:$VERILATOR_ROOT/include
- export CPLUS_INCLUDE_PATH=$CI_PROJECT_DIR/tmp/include:$VERILATOR_ROOT/include
- export LIBRARY_PATH=$RISCV/lib
- export LD_LIBRARY_PATH=$RISCV/lib
- export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
- export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
# number of parallel jobs to use for make commands and simulation
- export NUM_JOBS=4
- ci/make-tmp.sh
- git submodule update --init --recursive
variables:
GIT_SUBMODULE_STRATEGY: recursive
stages:
- build
- test
- test_std
# prepare
build:
stage: build
script:
- ci/install-fesvr.sh
- ci/build-riscv-tests.sh
- ci/get-torture.sh
- make clean
- make build questa_version=$QUESTASIM_VERSION
- make verilate verilator=$VERILATOR_ROOT/bin/verilator
- make torture-gen
artifacts:
paths:
- tmp
# rv64ui-p-* and rv64ui-v-* tests
run-asm-tests-questa:
stage: test
stage: test_std
script:
- make -j${NUM_JOBS} run-asm-tests questa_version=$QUESTASIM_VERSION
- make -j${NUM_JOBS} run-asm-tests
dependencies:
- build
run-benchmarks-questa:
stage: test
stage: test_std
script:
- make -j${NUM_JOBS} run-benchmarks questa_version=$QUESTASIM_VERSION
- make -j${NUM_JOBS} run-benchmarks
dependencies:
- build
# rv64ui-p-* tests
run-asm-tests1-verilator:
stage: test
stage: test_std
script:
- make -j${NUM_JOBS} run-asm-tests1-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-asm-tests1-verilator
dependencies:
- build
# rv64ui-v-* tests
run-asm-tests2-verilator:
stage: test
stage: test_std
script:
- make -j${NUM_JOBS} run-asm-tests2-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-asm-tests2-verilator
dependencies:
- build
run-benchmarks-verilator:
stage: test
stage: test_std
script:
- make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-benchmarks-verilator
dependencies:
- build
torture:
stage: test_std
script:
- make torture-rtest
- make torture-rtest-verilator
dependencies:
- build

6
.gitmodules vendored
View file

@ -1,6 +1,3 @@
[submodule "riscv-torture"]
path = riscv-torture
url = https://github.com/pulp-platform/riscv-torture.git
[submodule "src/axi_mem_if"]
path = src/axi_mem_if
url = https://github.com/pulp-platform/axi_mem_if.git
@ -22,3 +19,6 @@
[submodule "src/fpu_legacy"]
path = src/fpu_legacy
url = git@iis-git.ee.ethz.ch:sasa/fpu.git
[submodule "src/axi"]
path = src/axi
url = https://github.com/pulp-platform/axi.git

51
.travis.yml
View file

@ -13,8 +13,8 @@ addons:
sources:
- ubuntu-toolchain-r-test
packages:
- gcc-4.8
- g++-4.8
- gcc-7
- g++-7
- gperf
- autoconf
- automake
@ -29,7 +29,7 @@ addons:
- texinfo
- python-pexpect
- libusb-1.0-0-dev
- device-tree-compiler
- default-jdk
env:
global:
- RISCV="/home/travis/riscv_install"
@ -41,49 +41,60 @@ branches:
- ariane_next
before_install:
- export CXX=g++-4.8 CC=gcc-4.8
- export CXX=g++-7 CC=gcc-7
# setup dependent paths
- export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
- export LIBRARY_PATH=$TRAVIS_BUILD_DIR/tmp/lib
- export LD_LIBRARY_PATH=$TRAVIS_BUILD_DIR/tmp/lib
- export C_INCLUDE_PATH=$TRAVIS_BUILD_DIR/tmp/include:$VERILATOR_ROOT/include
- export CPLUS_INCLUDE_PATH=$TRAVIS_BUILD_DIR/tmp/include:$VERILATOR_ROOT/include
- export LIBRARY_PATH=$RISCV/lib
- export LD_LIBRARY_PATH=$RISCV/lib
- export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
- export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
# number of parallel jobs to use for make commands and simulation
- export NUM_JOBS=4
- ci/make-tmp.sh
- git submodule update --init --recursive
stages:
- compile
- compile1
- compile2
- test
jobs:
include:
- stage: compile
name: prepare cache
- stage: compile1
name: build gcc
script:
- ci/build-riscv-gcc.sh
- stage: compile2
name: build tools
script:
- ci/install-fesvr.sh
- ci/install-verilator.sh
- ci/install-dtc.sh
- ci/install-spike.sh
- stage: test
name: run riscv benchmarks
script:
- ci/install-fesvr.sh
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-benchmarks-verilator
# rv64ui-p-* tests
- stage: test
name: run rv64ui-p-* asm tests
name: run asm tests1
script:
- ci/install-fesvr.sh
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests1-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-asm-tests1-verilator
# rv64ui-v-* tests
- stage: test
name: run rv64ui-v-* asm tests
name: run asm tests2
script:
- ci/install-fesvr.sh
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests2-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-asm-tests2-verilator
- stage: test
name: run torture
script:
- ci/get-torture.sh
- make clean
- make torture-gen
- make torture-rtest-verilator
# extra time during long builds
install: travis_wait

4
Bender.yml
View file

@ -6,10 +6,10 @@ dependencies:
axi: { git: "git@iis-git.ee.ethz.ch:sasa/axi.git", rev: master }
axi2per: { git: "git@iis-git.ee.ethz.ch:pulp-open/axi2per.git", rev: master }
axi_mem_if: { git: "git@github.com:pulp-platform/axi_mem_if.git", rev: master }
axi_node: { git: "git@iis-git.ee.ethz.ch:pulp-open/axi_node.git", version: 1.0.3 }
axi_node: { git: "git@iis-git.ee.ethz.ch:pulp-open/axi_node.git", version: v1.1.0 }
axi_slice: { git: "git@iis-git.ee.ethz.ch:sasa/axi_slice.git", version: 1.1.2 }
tech_cells_generic: { git: "git@iis-git.ee.ethz.ch:pulp-open/tech_cells_generic.git", rev: master }
common_cells: { git: "git@iis-git.ee.ethz.ch:sasa/common_cells.git", version: v1.7.0 }
common_cells: { git: "git@iis-git.ee.ethz.ch:sasa/common_cells.git", version: v1.7.4 }
fpga-support: { git: "https://github.com/pulp-platform/fpga-support.git", version: v0.3.2 }
sources:
- src/fpu_legacy/hdl/fpu_utils/fpu_ff.sv

179
Makefile
View file

@ -2,8 +2,12 @@
# Date: 03/19/2017
# Description: Makefile for linting and testing Ariane.
# compile everything in the following library
# questa library
library ?= work
# verilator lib
ver-library ?= work-ver
# library for DPI
dpi-library ?= work-dpi
# Top level module to compile
top_level ?= ariane_tb
test_top_level ?= ariane_tb
@ -14,16 +18,18 @@ test_case ?= core_test
# QuestaSim Version
questa_version ?= ${QUESTASIM_VERSION}
# verilator version
verilator ?= verilator
verilator ?= ${VERILATOR_ROOT}/bin/verilator
# traget option
target-options ?=
# additional definess
defines ?=
# Sources
# Package files -> compile first
ariane_pkg := include/riscv_pkg.sv \
src/debug/dm_pkg.sv \
include/ariane_pkg.sv \
include/std_cache_pkg.sv \
include/axi_if.sv \
ariane_pkg := include/riscv_pkg.sv \
src/debug/dm_pkg.sv \
include/ariane_pkg.sv \
include/std_cache_pkg.sv \
include/axi_if.sv \
src/fpu/src/pkg/fpnew_pkg.vhd \
src/fpu/src/pkg/fpnew_fmts_pkg.vhd \
src/fpu/src/pkg/fpnew_comps_pkg.vhd \
@ -40,7 +46,7 @@ util := $(wildcard src/util/*.svh) \
test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
$(wildcard tb/test/*/*_pkg.sv*)
# DPI
dpi := $(patsubst tb/dpi/%.cc,work/%.o,$(wildcard tb/dpi/*.cc))
dpi := $(patsubst tb/dpi/%.cc,${dpi-library}/%.o,$(wildcard tb/dpi/*.cc))
dpi_hdr := $(wildcard tb/dpi/*.h)
# this list contains the standalone components
src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
@ -54,7 +60,7 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
$(wildcard bootrom/*.sv) \
$(wildcard src/axi_slice/*.sv) \
$(wildcard src/clint/*.sv) \
$(wildcard src/axi_node/*.sv) \
$(wildcard src/axi_node/src/*.sv) \
$(wildcard src/axi_mem_if/src/*.sv) \
$(filter-out src/debug/dm_pkg.sv, $(wildcard src/debug/*.sv)) \
$(wildcard src/debug/debug_rom/*.sv) \
@ -73,10 +79,12 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
tb/common/SimDTM.sv \
tb/common/SimJTAG.sv
# root path
root-dir := $(shell pwd)
# look for testbenches
tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
# RISCV asm tests and benchmark setup (used for CI)
# there is a defined test-list with selected CI tests
# there is a definesd test-list with selected CI tests
riscv-test-dir := tmp/riscv-tests/build/isa/
riscv-benchmarks-dir := tmp/riscv-tests/build/benchmarks/
riscv-asm-tests-list := ci/riscv-asm-tests.list
@ -85,26 +93,28 @@ riscv-asm-tests := $(shell xargs printf '\n%s' < $(riscv-asm-tests-list)
riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
# preset which runs a single test
riscv-test ?= rv64ui-p-add
# failed test directory
failed-tests := $(wildcard failedtests/*.S)
# Search here for include files (e.g.: non-standalone components)
incdir := ./includes
# Compile and sim flags
compile_flag += +cover=bcfst+/dut -quiet -incr -64 -nologo -suppress 13262 -permissive
compile_flag_vhd += -64 -nologo -quiet -2008
uvm-flags += +UVM_NO_RELNOTES
# Search here for include files (e.g.: non-standalone components)
incdir :=
# Compile and sim flags
compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)
compile_flag_vhd += -64 -nologo -quiet -2008
uvm-flags += +UVM_NO_RELNOTES
# Iterate over all include directories and write them with +incdir+ prefixed
# +incdir+ works for Verilator and QuestaSim
list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
# RISCV torture setup
riscv-torture-dir := tmp/riscv-torture/
riscv-torture-bin := java -Xmx1G -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
# Build the TB and module using QuestaSim
build: $(library) $(library)/.build-srcs $(library)/.build-tb $(library)/ariane_dpi.so
build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
# Optimize top level
vopt$(questa_version) $(compile_flag) -work $(library) $(test_top_level) -o $(test_top_level)_optimized +acc -check_synthesis
# src files
$(library)/.build-srcs: $(ariane_pkg) $(util) $(src)
$(library)/.build-srcs: $(ariane_pkg) $(util) $(src) $(library)
vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg))
vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
@ -119,70 +129,70 @@ $(library)/.build-tb: $(dpi) $(tbs)
vlog$(questa_version) -sv $(tbs) -work $(library)
touch $(library)/.build-tb
# compile DPIs
work/%.o: tb/dpi/%.cc $(dpi_hdr)
$(CXX) -shared -fPIC -std=c++0x -Bsymbolic -I$(QUESTASIM_HOME)/include -o $@ $<
$(library)/ariane_dpi.so: $(dpi)
# Compile C-code and generate .so file
g++ -shared -m64 -o $(library)/ariane_dpi.so $? -lfesvr
$(library):
# Create the library
vlib${questa_version} ${library}
# +jtag_rbb_enable=1
sim: build $(library)/ariane_dpi.so
vsim${questa_version} +permissive -noautoldlibpath -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do "do tb/wave/wave_core.do; set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all; exit" \
# compile DPIs
$(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr)
mkdir -p $(dpi-library)
$(CXX) -shared -fPIC -std=c++0x -Bsymbolic -I$(QUESTASIM_HOME)/include -o $@ $<
$(dpi-library)/ariane_dpi.so: $(dpi)
mkdir -p $(dpi-library)
# Compile C-code and generate .so file
$(CXX) -shared -m64 -o $(dpi-library)/ariane_dpi.so $? -lfesvr
sim: build
vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; do tb/wave/wave_core.do; run -all; exit" \
${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
simc: build $(library)/ariane_dpi.so
vsim${questa_version} +permissive -noautoldlibpath -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do "do tb/wave/wave_core.do; set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all; exit" \
simc: build
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi -do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all; exit" \
${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$(riscv-test) ++$(target-options)
$(riscv-asm-tests): build $(library)/ariane_dpi.so
vsim${questa_version} +permissive -noautoldlibpath -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
-do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
$(riscv-asm-tests): build
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
-do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
${top_level}_optimized +permissive-off ++$(riscv-test-dir)/$@ ++$(target-options) | tee tmp/riscv-asm-tests-$@.log
$(riscv-benchmarks): build $(library)/ariane_dpi.so
vsim${questa_version} +permissive -noautoldlibpath -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
$(riscv-benchmarks): build
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-benchmarks-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi \
-do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
-do " set StdArithNoWarnings 1; set NumericStdNoWarnings 1; coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
${top_level}_optimized +permissive-off ++$(riscv-benchmarks-dir)/$@ ++$(target-options) | tee tmp/riscv-benchmarks-$@.log
# can use -jX to run ci tests in parallel using X processes
run-asm-tests: $(riscv-asm-tests)
make check-asm-tests
check-asm-tests:
ci/check-tests.sh tmp/riscv-asm-tests- $(riscv-asm-tests-list)
ci/check-tests.sh tmp/riscv-asm-tests- $(shell wc -l $(riscv-asm-tests-list) | awk -F " " '{ print $1 }')
# can use -jX to run ci tests in parallel using X processes
run-benchmarks: $(riscv-benchmarks)
make check-benchmarks
check-benchmarks:
ci/check-tests.sh tmp/riscv-benchmarks- $(riscv-benchmarks-list)
ci/check-tests.sh tmp/riscv-benchmarks- $(shell wc -l $(riscv-benchmarks-list) | awk -F " " '{ print $1 }')
# verilator-specific
verilate_command := $(verilator) \
$(ariane_pkg) \
$(filter-out tb/ariane_bt.sv,$(src)) \
+define+$(defines) \
src/util/sram.sv \
+incdir+src/axi_node \
+incdir+src/axi_node \
--unroll-count 256 \
-Werror-PINMISSING \
-Werror-IMPLICIT \
@ -197,39 +207,72 @@ verilate_command := $(verilator)
$(if $(DEBUG),--trace-structs --trace,) \
-LDFLAGS "-lfesvr" -CFLAGS "-std=c++11 -I../tb/dpi" -Wall --cc --vpi \
$(list_incdir) --top-module ariane_testharness \
--Mdir build -O3 \
--Mdir $(ver-library) -O3 \
--exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc tb/dpi/remote_bitbang.cc
# User Verilator, at some point in the future this will be auto-generated
verilate:
$(verilate_command)
cd build && make -j${NUM_JOBS} -f Variane_testharness.mk
cd $(ver-library) && make -j${NUM_JOBS} -f Variane_testharness.mk
$(addsuffix -verilator,$(riscv-asm-tests)): verilate
build/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)
run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests))
# split into two halfs for travis jobs (otherwise they will time out)
run-asm-tests1-verilator: $(addsuffix -verilator, $(filter rv64ui-p-% ,$(riscv-asm-tests)))
run-asm-tests2-verilator: $(addsuffix -verilator, $(filter rv64ui-v-% ,$(riscv-asm-tests)))
run-asm-tests2-verilator: $(addsuffix -verilator, $(filter rv64ui-v-% rv64um-%,$(riscv-asm-tests)))
$(addsuffix -verilator,$(riscv-benchmarks)): verilate
build/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
$(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
run-benchmarks-verilator: $(addsuffix -verilator,$(riscv-benchmarks))
# torture-specific
torture-gen:
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'generator/run'
verify:
qverify vlog -sv src/csr_regfile.sv
torture-itest:
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -a output/test.S'
torture-rtest: build
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && make run-torture defines=$(defines)" > call.sh && chmod +x call.sh
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log
make check-torture
torture-rtest-verilator: verilate
cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && make run-torture-verilator defines=$(defines)" > call.sh && chmod +x call.sh
cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log
make check-torture
run-torture: build
vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles)+UVM_TESTNAME=${test_case} \
+BASEDIR=$(riscv-torture-dir) $(uvm-flags) "+UVM_VERBOSITY=LOW" -coverage -classdebug +jtag_rbb_enable=0 \
$(QUESTASIM_FLAGS) \
-gblso $(RISCV)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
-do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" \
${top_level}_optimized +permissive-off \
+signature=$(riscv-torture-dir)/output/test.rtlsim.sig ++$(riscv-torture-dir)/output/test ++$(target-options)
run-torture-verilator: verilate
$(ver-library)/Variane_testharness +max-cycles=$(max_cycles) +signature=$(riscv-torture-dir)/output/test.rtlsim.sig $(riscv-torture-dir)/output/test
check-torture:
grep 'All signatures match for output/test' $(riscv-torture-dir)/output/test.log
diff -s $(riscv-torture-dir)/output/test.spike.sig $(riscv-torture-dir)/output/test.rtlsim.sig
clean:
rm -rf work/ *.ucdb
rm -rf build
rm -f tmp/*.ucdb
rm -f tmp/*.log
rm -rf $(riscv-torture-dir)/output/test*
rm -rf $(library)/ $(dpi-library)/ $(ver-library)/
rm -f tmp/*.ucdb tmp/*.log *.wlf *vstf wlft* *.ucdb
.PHONY:
build lint build-moore $(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) $(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) check simc sim verilate clean verilate
build sim simc verilate clean \
$(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests)) \
$(riscv-benchmarks) $(addsuffix _verilator,$(riscv-benchmarks)) \
check-benchmarks check-asm-tests \
torture-gen torture-itest torture-rtest \
run-torture run-torture-verilator check-torture check-torture-verilator

30
README.md
View file

@ -26,10 +26,10 @@ Build the Verilator model of Ariane by using the Makefile:
$ make verilate
```
This will create a C++ model of the core including a SystemVerilog wrapper and link it against a C++ testbench (in the `tb` subfolder). The binary can be found in the `build` and accepts a RISC-V ELF binary as an argument, e.g.:
This will create a C++ model of the core including a SystemVerilog wrapper and link it against a C++ testbench (in the `tb` subfolder). The binary can be found in the `work-ver` and accepts a RISC-V ELF binary as an argument, e.g.:
```
$ build/Variane_testharness rv64um-v-divuw
$ work-ver/Variane_testharness rv64um-v-divuw
```
The Verilator testbench makes use of the `riscv-fesvr`. This means that you can use the `riscv-tests` repository as well as `riscv-pk` out-of-the-box. As a general rule of thumb the Verilator model will behave like Spike (exception for being orders of magnitudes slower).
@ -57,7 +57,7 @@ Then to run a RISC-V ELF using the Verilator model do:
```
$ make verilate
$ build/Variane_testharness /path/to/pk path/to/riscv.elf
$ work-ver/Variane_testharness /path/to/pk path/to/riscv.elf
```
If you want to use QuestaSim to run it you can use the following command:
@ -86,9 +86,29 @@ $ make sim riscv-test=tmp/risc-tests/build/isa/rv64ui-p-sraw
If you call `simc` instead of `sim` it will run without the GUI. QuestaSim uses `riscv-fesvr` for communication as well.
### Randomized Constrained Testing with Torture
### CI Testsuites and Randomized Constrained Testing with Torture
We provide two CI configuration files for Travis CI and GitLab CI that run the RISCV assembly tests, the RISCV benchmarks and a randomized RISCV Torture test. The difference between the two is that Travis CI runs these tests only on Verilator, whereas GitLab CI runs the same tests on QuestaSim and Verilator.
If you would like to run the CI test suites locally on your machine, follow any of the two scripts `ci.travis-ci-emul.sh` and `ci.travis-ci-emul.sh` (depending on whether you have QuestaSim or not). In particular, you have to get the required packages for your system, the paths in `ci/path-setup.sh` to match your setup, and run the installation and build scripts prior to running any of the tests suites.
Once everything is set up and installed, you can run the tests suites as follows (using Verilator):
```
$ make verilate
$ make run-asm-tests-verilator
$ make run-benchmarks-verilator
```
In order to run randomized Torture tests, you first have to generate the randomized program prior to running the simulation:
```
$ make torture-gen
$ make torture-rtest-verilator
```
This runs the randomized program on Spike and on the RTL target, and checks whether the two signatures match. The random instruction mix can be configured in the `./tmp/riscv-torture/config/default.config` file.
Currently not up-to-date.
# Contributing

7
ariane-run-torture
View file

@ -1,7 +0,0 @@
#!/bin/sh
# make the verilog first
cd output && make
cd ../..
# start the simulation
vsim-10.6b -c -lib work core_tb_optimized +UVM_TESTNAME=core_test $2 +BASEDIR=riscv-torture $1 +ASMTEST=$3 +UVM_VERBOSITY=LOW -coverage -classdebug -do "run -a"

3
ci/build-riscv-gcc.sh
View file

@ -1,6 +1,7 @@
#!/bin/bash
set -e
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
VERSION="691e4e826251c7ec59f883cab18440c87baf45e7"
cd $ROOT/tmp
if [ -z ${NUM_JOBS} ]; then
@ -10,7 +11,7 @@ fi
if ! [ -e $RISCV/bin ]; then
[ -d $ROOT/tmp/riscv-gnu-toolchain ] || git clone https://github.com/riscv/riscv-gnu-toolchain.git
cd riscv-gnu-toolchain
git checkout 691e4e826251c7ec59f883cab18440c87baf45e7
git checkout $VERSION
git submodule update --init --recursive
mkdir -p $RISCV

4
ci/build-riscv-tests.sh
View file

@ -1,6 +1,8 @@
#!/bin/bash
set -e
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
VERSION="294bfce8a1ca2fc501b8939292146e44f813a2b8"
cd $ROOT/tmp
if [ -z ${NUM_JOBS} ]; then
@ -9,7 +11,7 @@ fi
[ -d $ROOT/tmp/riscv-tests ] || git clone https://github.com/riscv/riscv-tests.git
cd riscv-tests
git checkout 294bfce8a1ca2fc501b8939292146e44f813a2b8
git checkout $VERSION
git submodule update --init --recursive
autoconf
mkdir -p build

14
ci/check-tests.sh
View file

@ -24,13 +24,9 @@ if [ ! -f "${1}"*.log ]; then
exit 1;
fi
if [ ! -f "$2" ]; then
echo -e "${RED}FAILED file $2 does not exist ${NC}"
exit 1;
fi
# get NUM_TOTAL number of tests
NUM_TOTAL=`wc -l $2 | awk -F " " '{ print $1 }'`
NUM_TOTAL=$2
echo "list containint tests: $2"
@ -38,10 +34,10 @@ echo "checking files:"
ls "${1}"*.log
# check for patterns
NUM_PASSED=`grep -s "SUCCESS" ${1}*.log | wc -l`
NUM_FAILED=`grep -s "FAILED" ${1}*.log | wc -l`
NUM_FATAL=`grep -s "Fatal:" ${1}*.log | wc -l`
NUM_ERROR=`grep -s "Error:" ${1}*.log | wc -l`
NUM_PASSED=`grep -i -s "SUCCESS" ${1}*.log | wc -l`
NUM_FAILED=`grep -i -s "FAILED" ${1}*.log | wc -l`
NUM_FATAL=`grep -i -s "Fatal:" ${1}*.log | wc -l`
NUM_ERROR=`grep -i -s "Error:" ${1}*.log | wc -l`
echo "NUM_TOTAL: $NUM_TOTAL"
echo "NUM_PASSED: $NUM_PASSED"

52
ci/default.config Normal file
View file

@ -0,0 +1,52 @@
torture.generator.nseqs 1000
torture.generator.memsize 1024
torture.generator.fprnd 0
torture.generator.amo false
torture.generator.mul true
torture.generator.divider true
torture.generator.segment true
torture.generator.loop true
torture.generator.loop_size 64
torture.generator.mix.xmem 15
torture.generator.mix.xbranch 25
torture.generator.mix.xalu 60
torture.generator.mix.fgen 0
torture.generator.mix.fpmem 0
torture.generator.mix.fax 0
torture.generator.mix.fdiv 0
torture.generator.mix.vec 0
torture.generator.vec.vf 1
torture.generator.vec.seq 20
torture.generator.vec.memsize 128
torture.generator.vec.numsregs 64
torture.generator.vec.mul false
torture.generator.vec.div false
torture.generator.vec.mix true
torture.generator.vec.fpu false
torture.generator.vec.fma false
torture.generator.vec.fcvt false
torture.generator.vec.fdiv false
torture.generator.vec.amo false
torture.generator.vec.seg false
torture.generator.vec.stride false
torture.generator.vec.pred_alu true
torture.generator.vec.pred_mem true
torture.generator.vec.mix.valu 20
torture.generator.vec.mix.vpop 60
torture.generator.vec.mix.vmem 20
torture.generator.vec.mix.vonly 0
torture.testrun.maxcycles 10000000
torture.testrun.virtual false
torture.testrun.seek true
torture.testrun.dump false
torture.testrun.vec false
torture.overnight.errors 1
torture.overnight.minutes 1
torture.overnight.outdir output/failedtests
torture.overnight.email your@email.address

21
ci/get-torture.sh Executable file
View file

@ -0,0 +1,21 @@
#!/bin/bash
set -e
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
VERSION="59b0f0f224ff4f1eb6ebb1b4dd7eaf1ab3fac2e5"
cd $ROOT/tmp
if [ -z ${NUM_JOBS} ]; then
NUM_JOBS=1
fi
[ -d $ROOT/tmp/riscv-torture ] || git clone https://github.com/ucb-bar/riscv-torture.git
cd riscv-torture
git checkout $VERSION
git submodule update --init --recursive
# copy ariane specific config
cp config/default.config config/default.config.bak
cp $ROOT/ci/default.config config/default.config
git apply $ROOT/ci/torture_make.patch

29
ci/gitlab-ci-emul.sh
View file

@ -1,10 +1,10 @@
# !/bin/bash
#!/bin/bash
# This script emulates what the gitlab ci config does (not on public server)
# source this with a bash shell in the project root
# comment out next command if you don't want to use sudo
sudo apt install \
gcc-4.8 \
g++-4.8 \
gcc-7 \
g++-7 \
gperf \
autoconf \
automake \
@ -19,25 +19,34 @@ sudo apt install \
texinfo \
python-pexpect \
libusb-1.0-0-dev \
device-tree-compiler
default-jdk
# customize your paths here
source ci/path-setup.sh
# install the required tools
git submodule update --init --recursive
ci/make-tmp.sh
ci/build-riscv-gcc.sh
ci/install-fesvr.sh
ci/install-verilator.sh
ci/build-riscv-tests.sh
ci/install-dtc.sh
ci/install-spike.sh
ci/get-torture.sh
# clean up and generate randomized test
make clean
make torture-gen
# run asm tests on verilator
make -j${NUM_JOBS} verilate verilator=$VERILATOR_ROOT/bin/verilator
make -j${NUM_JOBS} run-asm-tests-verilator verilator=$VERILATOR_ROOT/bin/verilator
make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
make -j${NUM_JOBS} verilate
make -j${NUM_JOBS} run-asm-tests-verilator
make -j${NUM_JOBS} run-benchmarks-verilator
make -j${NUM_JOBS} torture-rtest-verilator
# run asm tests on questa
make -j${NUM_JOBS} build questa_version=$QUESTASIM_VERSION
make -j${NUM_JOBS} run-asm-tests questa_version=$QUESTASIM_VERSION
make -j${NUM_JOBS} run-benchmarks questa_version=$QUESTASIM_VERSION
make -j${NUM_JOBS} build
make -j${NUM_JOBS} run-asm-tests
make -j${NUM_JOBS} run-benchmarks
make -j${NUM_JOBS} torture-rtest

22
ci/install-dtc.sh Executable file
View file

@ -0,0 +1,22 @@
#!/bin/bash
set -e
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
VERSION="b94c056b137e59deefc62fbfe0cd3a23edfcc07c"
cd $ROOT/tmp
if [ -z ${NUM_JOBS} ]; then
NUM_JOBS=1
fi
if [ ! -e "$RISCV/dtc/dtc" ]; then
echo "Installing DTC"
git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git
cd dtc
git checkout $VERSION
make -j${NUM_JOBS} PREFIX=$RISCV/ NO_PYTHON=1
make -j${NUM_JOBS} check NO_PYTHON=1
make -j${NUM_JOBS} install PREFIX=$RISCV/ NO_PYTHON=1
else
echo "Using DTC from cached directory."
fi

24
ci/install-fesvr.sh
View file

@ -1,19 +1,27 @@
#!/bin/bash
set -e
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
VERSION=30e85ce253788b29bd4ac0b5e5c23a077d96dc24
cd $ROOT/tmp
RELEASE=0.1.0
if [ -z ${NUM_JOBS} ]; then
NUM_JOBS=1
fi
if ! [ -e $ROOT/tmp/riscv-fesvr ]; then
if [ ! -e "${RISCV}/lib/libfesvr.so" ]; then
echo "Installing RISCV FESVR"
git clone https://github.com/riscv/riscv-fesvr.git
cd riscv-fesvr
git checkout $VERSION
mkdir -p build
cd build
../configure --prefix="$RISCV/"
make -j${NUM_JOBS}
make install
else
echo "Using RISCV FESVR from cached directory."
fi
cd $ROOT/tmp/riscv-fesvr
mkdir -p build
cd build
../configure --prefix="$ROOT/tmp"
make -j${NUM_JOBS}
make install

27
ci/install-spike.sh Executable file
View file

@ -0,0 +1,27 @@
#!/bin/bash
set -e
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
VERSION="def4c5b104efd382e633d5fdca49508757bb5e23"
cd $ROOT/tmp
if [ -z ${NUM_JOBS} ]; then
NUM_JOBS=1
fi
if [ ! -e "${RISCV}/bin/spike" ]; then
echo "Installing Spike"
git clone https://github.com/riscv/riscv-isa-sim.git
cd riscv-isa-sim
git checkout $VERSION
mkdir -p build
cd build
../configure --prefix="$RISCV/"
make -j${NUM_JOBS}
make install
else
echo "Using Spike from cached directory."
fi

11
ci/path-setup.sh
View file

@ -5,17 +5,18 @@ export CI_BUILD_DIR=$TOP/ariane-repo
#customize this to your setup
export QUESTASIM_HOME=
export QUESTASIM_VERSION=
export CXX=g++-4.8 CC=gcc-4.8
export QUESTASIM_FLAGS=
export CXX=g++-7 CC=gcc-7
# where to install the tools
export RISCV=$TOP/riscv_install
export VERILATOR_ROOT=$TOP/verilator-3.924/
export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
export LIBRARY_PATH=$CI_BUILD_DIR/tmp/lib
export LD_LIBRARY_PATH=$CI_BUILD_DIR/tmp/lib
export C_INCLUDE_PATH=$CI_BUILD_DIR/tmp/include:$VERILATOR_ROOT/include
export CPLUS_INCLUDE_PATH=$CI_BUILD_DIR/tmp/include:$VERILATOR_ROOT/include
export LIBRARY_PATH=$RISCV/lib
export LD_LIBRARY_PATH=$RISCV/lib
export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
# number of parallel jobs to use for make commands and simulation
export NUM_JOBS=8

41
ci/torture_make.patch Normal file
View file

@ -0,0 +1,41 @@
diff --git a/output/Makefile b/output/Makefile
index cf1214f..c81bccc 100644
--- a/output/Makefile
+++ b/output/Makefile
@@ -20,9 +20,9 @@ extra_files =
#--------------------------------------------------------------------
RISCV_GCC = riscv64-unknown-elf-gcc
-RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha
+RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=rv64imc
RISCV_OBJDUMP = riscv64-unknown-elf-objdump --disassemble-all --section=.text --section=.data --section=.bss
-RISCV_SIM = spike --extension=hwacha
+RISCV_SIM = spike
#------------------------------------------------------------
# Build assembly tests
@@ -38,9 +38,6 @@ $(asm_tests_dump): %.dump: %
$(asm_tests_bin): %: %.S $(extra_files)
$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../env/p -T../env/p/link.ld $< -o $@
-$(asm_tests_hex): %.hex: % $(extra_files)
- elf2hex 16 16384 $< > $@
-
$(asm_tests_sig): %.sig: %
$(RISCV_SIM) +signature=$@ $<
@@ -51,12 +48,12 @@ run: $(asm_tests_sig)
echo; perl -ne 'print " [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
$(asm_tests_sig); echo;
-junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig) $(asm_tests_hex)
+junk += $(asm_tests_bin) $(asm_tests_dump) $(asm_tests_sig)
#------------------------------------------------------------
# Default
-all: $(asm_tests_dump) $(asm_tests_hex)
+all: $(asm_tests_dump)
#------------------------------------------------------------
# Clean up

20
ci/travis-ci-emul.sh
View file

@ -3,8 +3,8 @@
# source this with a bash shell in the project root
# comment out next command if you don't want to use sudo
sudo apt install \
gcc-4.8 \
g++-4.8 \
gcc-7 \
g++-7 \
gperf \
autoconf \
automake \
@ -19,20 +19,28 @@ sudo apt install \
texinfo \
python-pexpect \
libusb-1.0-0-dev \
device-tree-compiler
default-jdk
# customize your paths here
source ci/path-setup.sh
# install the required tools
git submodule update --init --recursive
ci/make-tmp.sh
ci/build-riscv-gcc.sh
ci/install-fesvr.sh
ci/install-verilator.sh
ci/build-riscv-tests.sh
ci/install-dtc.sh
ci/install-spike.sh
ci/get-torture.sh
# clean up and generate randomized test
make clean
make torture-gen
# run asm tests on verilator
make -j${NUM_JOBS} verilate verilator=$VERILATOR_ROOT/bin/verilator
make -j${NUM_JOBS} run-asm-tests-verilator verilator=$VERILATOR_ROOT/bin/verilator
make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
make -j${NUM_JOBS} verilate
make -j${NUM_JOBS} run-asm-tests-verilator
make -j${NUM_JOBS} run-benchmarks-verilator
make -j${NUM_JOBS} torture-rtest-verilator

1
riscv-torture

@ -1 +0,0 @@
Subproject commit 4e1c13adc5c1bb1128c5c57349e7e2d78fafc139

1
src/axi Submodule

@ -0,0 +1 @@
Subproject commit 328cbe05a42a31aae6f57f780351a2ba22954fef

2
src/axi_node

@ -1 +1 @@
Subproject commit ec45a3d13a9b827f35aa76d19a8400e3ef6d13b6
Subproject commit 1f77f634b65fdee56dfc928cadadd66e9fafc485

151
src/cache_subsystem/std_icache.sv
View file

@ -50,13 +50,14 @@ module std_icache #(
logic flushing_d, flushing_q;
// signals
logic [ICACHE_SET_ASSOC-1:0] req; // request to memory array
logic [(ICACHE_LINE_WIDTH+7)/8-1:0] data_be; // byte enable for data array
logic [ICACHE_SET_ASSOC-1:0] req; // request to data memory
logic [ICACHE_SET_ASSOC-1:0] vld_req; // request to valid/tag memory
logic [(ICACHE_LINE_WIDTH+7)/8-1:0] data_be; // byte enable for data memory
logic [(2**NR_AXI_REFILLS-1):0][7:0] be; // byte enable
logic [$clog2(ICACHE_NUM_WORD)-1:0] addr; // this is a cache-line address, to memory array
logic we; // write enable to memory array
logic [ICACHE_SET_ASSOC-1:0] hit; // hit from tag compare
logic [ICACHE_BYTE_OFFSET-1:2] idx; // index in cache line
logic [$clog2(ICACHE_NUM_WORD)-1:0] idx; // index in cache line
logic update_lfsr; // shift the LFSR
logic [ICACHE_SET_ASSOC-1:0] random_way; // random way select from LFSR
logic [ICACHE_SET_ASSOC-1:0] way_valid; // bit string which contains the zapped valid bits
@ -84,7 +85,7 @@ module std_icache #(
) tag_sram (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req[i] ),
.req_i ( vld_req[i] ),
.we_i ( we ),
.addr_i ( addr ),
.wdata_i ( tag_wdata ),
@ -108,45 +109,31 @@ module std_icache #(
.rdata_o ( data_rdata[i] )
);
end
// --------------------
// Tag Comparison
// Tag Comparison and way select
// --------------------
for (genvar i = 0; i < ICACHE_SET_ASSOC; i++) begin
assign hit[i] = (tag_rdata[i].tag == tag) ? tag_rdata[i].valid : 1'b0;
end
`ifndef SYNTHESIS
`ifndef VERILATOR
// assert that cache only hits on one way
assert property (
@(posedge clk_i) $onehot0(hit)) else begin $error("[icache] Hit should be one-hot encoded"); $stop(); end
`endif
`endif
// ------------------
// Way Select
// ------------------
assign idx = vaddr_q[ICACHE_BYTE_OFFSET-1:2];
// cacheline selected by hit
logic [ICACHE_LINE_WIDTH/FETCH_WIDTH-1:0][FETCH_WIDTH-1:0] selected_cl;
logic [ICACHE_LINE_WIDTH-1:0] selected_cl_flat;
logic [ICACHE_SET_ASSOC-1:0][FETCH_WIDTH-1:0] cl_sel;
assign idx = vaddr_q[ICACHE_BYTE_OFFSET-1:2];
for (genvar i = 0; i < ICACHE_LINE_WIDTH; i++) begin
logic [ICACHE_SET_ASSOC-1:0] hit_masked_cl;
for (genvar j = 0; j < ICACHE_SET_ASSOC; j++)
assign hit_masked_cl[j] = data_rdata[j][i] & hit[j];
assign selected_cl_flat[i] = |hit_masked_cl;
generate
for (genvar i=0;i<ICACHE_SET_ASSOC;i++) begin : g_tag_cmpsel
assign hit[i] = (tag_rdata[i].tag == tag) ? tag_rdata[i].valid : 1'b0;
assign cl_sel[i] = (hit[i]) ? data_rdata[i][{idx,5'b0} +: FETCH_WIDTH] : '0;
assign way_valid[i] = tag_rdata[i].valid;
end
endgenerate
// OR reduction of selected cachelines
always_comb begin : p_reduction
dreq_o.data = cl_sel[0];
for(int i=1; i<ICACHE_SET_ASSOC;i++)
dreq_o.data |= cl_sel[i];
end
assign selected_cl = selected_cl_flat;
// maybe re-work if critical
assign dreq_o.data = selected_cl[idx];
for (genvar i = 0; i < ICACHE_SET_ASSOC; i++) begin
assign way_valid[i] = tag_rdata[i].valid;
end
// ------------------
// AXI Plumbing
@ -188,6 +175,10 @@ module std_icache #(
assign data_wdata = wdata;
assign dreq_o.ex = areq_i.fetch_exception;
assign addr = (state_q==FLUSH) ? cnt_q : vaddr_d[ICACHE_INDEX_WIDTH-1:ICACHE_BYTE_OFFSET];
// ------------------
// Cache Ctrl
// ------------------
@ -195,27 +186,27 @@ module std_icache #(
// but on every access we are re-fetching the cache-line
always_comb begin : cache_ctrl
// default assignments
state_d = state_q;
cnt_d = cnt_q;
vaddr_d = vaddr_q;
tag_d = tag_q;
evict_way_d = evict_way_q;
flushing_d = flushing_q;
burst_cnt_d = burst_cnt_q;
state_d = state_q;
cnt_d = cnt_q;
vaddr_d = vaddr_q;
tag_d = tag_q;
evict_way_d = evict_way_q;
flushing_d = flushing_q;
burst_cnt_d = burst_cnt_q;
dreq_o.vaddr = vaddr_q;
req = '0;
addr = dreq_i.vaddr[ICACHE_INDEX_WIDTH-1:ICACHE_BYTE_OFFSET];
we = 1'b0;
be = '0;
wdata = '0;
tag_wdata = '0;
dreq_o.ready = 1'b0;
tag = areq_i.fetch_paddr[ICACHE_TAG_WIDTH+ICACHE_INDEX_WIDTH-1:ICACHE_INDEX_WIDTH];
dreq_o.valid = 1'b0;
update_lfsr = 1'b0;
miss_o = 1'b0;
req = '0;
vld_req = '0;
we = 1'b0;
be = '0;
wdata = '0;
tag_wdata = '0;
dreq_o.ready = 1'b0;
tag = areq_i.fetch_paddr[ICACHE_TAG_WIDTH+ICACHE_INDEX_WIDTH-1:ICACHE_INDEX_WIDTH];
dreq_o.valid = 1'b0;
update_lfsr = 1'b0;
miss_o = 1'b0;
axi.ar_valid = 1'b0;
axi.ar_addr = '0;
@ -227,12 +218,14 @@ module std_icache #(
// ~> we are ready to receive a new request
IDLE: begin
dreq_o.ready = 1'b1;
vaddr_d = dreq_i.vaddr;
// we are getting a new request
if (dreq_i.req) begin
// request the content of all arrays
req = '1;
req = '1;
vld_req = '1;
// save the virtual address
vaddr_d = dreq_i.vaddr;
state_d = TAG_CMP;
end
@ -246,6 +239,11 @@ module std_icache #(
// ~> compare the tag
TAG_CMP, TAG_CMP_SAVED: begin
areq_o.fetch_req = 1'b1; // request address translation
// (speculatively) request the content of all arrays
req = '1;
vld_req = '1;
// use the saved tag
if (state_q == TAG_CMP_SAVED)
tag = tag_q;
@ -256,13 +254,11 @@ module std_icache #(
if (|hit && areq_i.fetch_valid && (en_i || (state_q != TAG_CMP))) begin
dreq_o.ready = 1'b1;
dreq_o.valid = 1'b1;
vaddr_d = dreq_i.vaddr;
// we've got another request
if (dreq_i.req) begin
// request the content of all arrays
req = '1;
// save the index and stay in compare mode
vaddr_d = dreq_i.vaddr;
state_d = TAG_CMP;
// no new request -> go back to idle
end else begin
@ -338,8 +334,8 @@ module std_icache #(
WAIT_AXI_R_RESP, WAIT_KILLED_AXI_R_RESP: begin
req = evict_way_q;
addr = vaddr_q[ICACHE_INDEX_WIDTH-1:ICACHE_BYTE_OFFSET];
vld_req = evict_way_q;
if (axi.r_valid) begin
we = 1'b1;
tag_wdata.tag = tag_q;
@ -363,16 +359,15 @@ module std_icache #(
end
// ~> redo the request,
REDO_REQ: begin
req = '1;
addr = vaddr_q[ICACHE_INDEX_WIDTH-1:ICACHE_BYTE_OFFSET];
tag = tag_q;
req = '1;
vld_req = '1;
tag = tag_q;
state_d = TAG_CMP_SAVED; // do tag comparison on the saved tag
end
// ~> we are coming here after reset or when a flush was requested
FLUSH: begin
addr = cnt_q;
cnt_d = cnt_q + 1;
req = '1;
vld_req = '1;
we = 1;
// we've finished flushing, go back to idle
if (cnt_q == ICACHE_NUM_WORD - 1) begin
@ -441,9 +436,21 @@ module std_icache #(
end
end
`ifndef SYNTHESIS
initial begin
assert ($bits(axi.aw_addr) == 64) else $fatal(1, "Ariane needs a 64-bit bus");
end
`endif
///////////////////////////////////////////////////////
// assertions
///////////////////////////////////////////////////////
//pragma translate_off
`ifndef VERILATOR
initial begin
assert ($bits(axi.aw_addr) == 64)
else $fatal(1, "[icache] Ariane needs a 64-bit bus");
end
// assert that cache only hits on one way
onehot: assert property (
@(posedge clk_i) disable iff (~rst_ni) $onehot0(hit))
else $fatal(1, "[icache] Hit should be one-hot encoded");
`endif
//pragma translate_on
endmodule

2
src/common_cells

@ -1 +1 @@
Subproject commit 4277217c9ae8b1228f801e5a67de9ecdce8d887f
Subproject commit 4ddb77914eed42f7980a45c16f58fd82dd8b2292

45
src/mult.sv
View file

@ -437,14 +437,15 @@ module mul (
// Pipeline register
logic [TRANS_ID_BITS-1:0] trans_id_q;
logic mult_valid_q;
logic [63:0] result_q;
fu_op operator_d, operator_q;
logic [127:0] mult_result_d, mult_result_q;
// control registers
logic sign_a, sign_b;
logic mult_valid;
// control signals
assign mult_valid_o = mult_valid_q;
assign result_o = result_q;
assign mult_trans_id_o = trans_id_q;
assign mult_ready_o = 1'b1;
@ -472,28 +473,38 @@ module mul (
end
end
// single stage version
assign mult_result_d = $signed({operand_a_i[63] & sign_a, operand_a_i}) *
$signed({operand_b_i[63] & sign_b, operand_b_i});
assign operator_d = operator_i;
always_comb begin : p_selmux
unique case (operator_q)
MULH, MULHU, MULHSU: result_o = mult_result_q[127:64];
MULW: result_o = sext32(mult_result_q[31:0]);
// MUL performs an XLEN-bit×XLEN-bit multiplication and places the lower XLEN bits in the destination register
default: result_o = mult_result_q[63:0];// including MUL
endcase
end
// -----------------------
// Output pipeline register
// -----------------------
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
mult_valid_q <= '0;
trans_id_q <= '0;
result_q <= '0;
end else begin
mult_valid_q <= '0;
trans_id_q <= '0;
operator_q <= MUL;
mult_result_q <= '0;
end else begin
// Input silencing
trans_id_q <= trans_id_i;
// Output Register
mult_valid_q <= mult_valid;
case (operator_i)
// MUL performs an XLEN-bit×XLEN-bit multiplication and places the lower XLEN bits in the destination register
MUL: result_q <= mult_result[63:0];
MULH: result_q <= mult_result[127:64];
MULHU: result_q <= mult_result[127:64];
MULHSU: result_q <= mult_result[127:64];
MULW: result_q <= sext32(mult_result[31:0]);
endcase
end
mult_valid_q <= mult_valid;
operator_q <= operator_d;
mult_result_q <= mult_result_d;
end
end
endmodule