mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-19 03:44:46 -04:00
verilator: Add memory preloading
Pre-load the Verilator memories through a side-band signal. We have sub-classed the dtm_t module to prevent the debugger from pre-loading. This commit also updates the stale bootrom. Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
This commit is contained in:
Florian Zaruba
Florian Zaruba
parent
c04a73ec9d
commit
3a13ae0333
8 changed files with 193 additions and 98 deletions
2
Makefile
2
Makefile
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@ -488,7 +488,7 @@ $(addsuffix -verilator,$(riscv-fp-tests)): verilate
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$(addsuffix -verilator,$(riscv-benchmarks)): verilate
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$(ver-library)/Variane_testharness $(riscv-benchmarks-dir)/$(subst -verilator,,$@)
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run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(riscv-fp-tests)) $(addsuffix -verilator, $(riscv-fp-tests))
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run-asm-tests-verilator: $(addsuffix -verilator, $(riscv-asm-tests)) $(addsuffix -verilator, $(riscv-amo-tests)) $(addsuffix -verilator, $(run-mul-verilator)) $(addsuffix -verilator, $(riscv-fp-tests))
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# split into smaller travis jobs (otherwise they will time out)
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riscv-asm-rv64ui-v := $(filter rv64ui-v-%, $(riscv-asm-tests))
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@ -1,9 +1,8 @@
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#define DRAM_BASE 0x80000000
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.section .text.start, "ax", @progbits
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.globl _start
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_start:
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li s0, DRAM_BASE
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li s0, 1
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slli s0, s0, 31
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csrr a0, mhartid
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la a1, _dtb
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jr s0
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@ -1,13 +1,12 @@
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// Auto-generated code
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const int reset_vec_size = 374;
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const int reset_vec_size = 402;
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uint32_t reset_vec[reset_vec_size] = {
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0x0010041b,
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0x01f41413,
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0x047e4405,
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0xf1402573,
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0x00000597,
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0x07458593,
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0x07858593,
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0x00008402,
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0x00000000,
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0x00000000,
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@ -19,6 +18,7 @@ uint32_t reset_vec[reset_vec_size] = {
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xf1402573,
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0x00000597,
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0x03c58593,
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@ -36,15 +36,15 @@ uint32_t reset_vec[reset_vec_size] = {
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0x00000000,
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0x00000000,
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0xedfe0dd0,
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0x58050000,
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0xc2050000,
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0x38000000,
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0x4c040000,
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0xbc040000,
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0x28000000,
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0x11000000,
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0x10000000,
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0x00000000,
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0x0c010000,
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0x14040000,
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0x06010000,
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0x84040000,
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0x00000000,
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0x00000000,
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0x00000000,
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@ -157,10 +157,6 @@ uint32_t reset_vec[reset_vec_size] = {
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0x04000000,
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0xa9000000,
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0x01000000,
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0x03000000,
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0x04000000,
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0xaf000000,
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0x01000000,
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0x02000000,
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0x02000000,
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0x02000000,
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@ -205,7 +201,7 @@ uint32_t reset_vec[reset_vec_size] = {
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0x00007375,
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0x03000000,
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0x00000000,
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0xb7000000,
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0xb1000000,
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0x01000000,
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0x6e696c63,
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0x30324074,
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@ -220,7 +216,7 @@ uint32_t reset_vec[reset_vec_size] = {
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0x00000000,
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0x03000000,
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0x10000000,
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0xbe000000,
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0xb8000000,
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0x01000000,
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0x03000000,
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0x01000000,
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@ -234,7 +230,7 @@ uint32_t reset_vec[reset_vec_size] = {
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0x00000c00,
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0x03000000,
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0x08000000,
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0xd2000000,
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0xcc000000,
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0x746e6f63,
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0x006c6f72,
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0x02000000,
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@ -253,7 +249,7 @@ uint32_t reset_vec[reset_vec_size] = {
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0x00333130,
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0x03000000,
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0x08000000,
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0xbe000000,
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0xb8000000,
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0x01000000,
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0xffff0000,
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0x03000000,
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@ -265,7 +261,7 @@ uint32_t reset_vec[reset_vec_size] = {
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0x00100000,
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0x03000000,
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0x08000000,
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0xd2000000,
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0xcc000000,
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0x746e6f63,
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0x006c6f72,
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0x02000000,
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@ -292,21 +288,53 @@ uint32_t reset_vec[reset_vec_size] = {
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0x80f0fa02,
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0x03000000,
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0x04000000,
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0xdc000000,
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0xd6000000,
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0x00c20100,
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0x03000000,
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0x04000000,
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0xea000000,
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0xe4000000,
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0x01000000,
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0x03000000,
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0x04000000,
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0xf5000000,
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0xef000000,
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0x02000000,
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0x03000000,
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0x04000000,
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0xff000000,
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0xf9000000,
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0x04000000,
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0x02000000,
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0x01000000,
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0x656d6974,
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0x38314072,
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0x30303030,
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0x00003030,
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0x03000000,
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0x0f000000,
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0x1b000000,
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0x706c7570,
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0x6270612c,
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0x6d69745f,
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0x00007265,
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0x03000000,
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0x10000000,
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0xe4000000,
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0x04000000,
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0x05000000,
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0x06000000,
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0x07000000,
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0x03000000,
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0x10000000,
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0x5b000000,
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0x00000000,
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0x00000018,
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0x00000000,
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0x00100000,
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0x03000000,
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0x08000000,
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0xcc000000,
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0x746e6f63,
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0x006c6f72,
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0x02000000,
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0x02000000,
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0x02000000,
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0x09000000,
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@ -352,29 +380,29 @@ uint32_t reset_vec[reset_vec_size] = {
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0x6f632d74,
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0x6f72746e,
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0x72656c6c,
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0x6e696c00,
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0x702c7875,
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0x646e6168,
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0x7200656c,
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0x65676e61,
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0x6e690073,
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0x72726574,
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0x73747075,
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0x7478652d,
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0x65646e65,
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0x65720064,
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0x616e2d67,
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0x0073656d,
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0x72727563,
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0x2d746e65,
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0x65657073,
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0x6e690064,
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0x72726574,
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0x73747075,
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0x61687000,
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0x656c646e,
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0x6e617200,
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0x00736567,
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0x65746e69,
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0x70757272,
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0x652d7374,
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0x6e657478,
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0x00646564,
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0x2d676572,
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0x656d616e,
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0x75630073,
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0x6e657272,
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0x70732d74,
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0x00646565,
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0x65746e69,
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0x70757272,
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0x72007374,
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0x732d6765,
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0x74666968,
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0x67657200,
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0x6968732d,
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0x72007466,
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0x692d6765,
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0x69772d6f,
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0x00687464
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0x2d6f692d,
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0x74646977,
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0x00000068,
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0x00000000
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};
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Binary file not shown.
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@ -20,22 +20,22 @@ module bootrom (
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input logic [63:0] addr_i,
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output logic [63:0] rdata_o
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);
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localparam int RomSize = 187;
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localparam int RomSize = 201;
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const logic [RomSize-1:0][63:0] mem = {
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64'h00687464_69772d6f,
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64'h692d6765_72007466,
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64'h6968732d_67657200,
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64'h73747075_72726574,
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64'h6e690064_65657073,
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64'h2d746e65_72727563,
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64'h0073656d_616e2d67,
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64'h65720064_65646e65,
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64'h7478652d_73747075,
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64'h72726574_6e690073,
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64'h65676e61_7200656c,
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64'h646e6168_702c7875,
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64'h6e696c00_72656c6c,
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64'h00000000_00000068,
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64'h74646977_2d6f692d,
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64'h67657200_74666968,
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64'h732d6765_72007374,
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64'h70757272_65746e69,
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64'h00646565_70732d74,
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64'h6e657272_75630073,
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64'h656d616e_2d676572,
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64'h00646564_6e657478,
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64'h652d7374_70757272,
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64'h65746e69_00736567,
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64'h6e617200_656c646e,
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64'h61687000_72656c6c,
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64'h6f72746e_6f632d74,
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64'h70757272_65746e69,
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64'h00736c6c_65632d74,
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@ -58,14 +58,30 @@ module bootrom (
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64'h6c65632d_73736572,
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64'h64646123_09000000,
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64'h02000000_02000000,
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64'h02000000_006c6f72,
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64'h746e6f63_cc000000,
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64'h08000000_03000000,
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64'h00100000_00000000,
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64'h00000018_00000000,
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64'h5b000000_10000000,
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64'h03000000_07000000,
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64'h06000000_05000000,
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64'h04000000_e4000000,
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64'h10000000_03000000,
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64'h00007265_6d69745f,
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64'h6270612c_706c7570,
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64'h1b000000_0f000000,
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64'h03000000_00003030,
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64'h30303030_38314072,
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64'h656d6974_01000000,
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64'h02000000_04000000,
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64'hff000000_04000000,
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64'hf9000000_04000000,
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64'h03000000_02000000,
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64'hf5000000_04000000,
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64'hef000000_04000000,
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64'h03000000_01000000,
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64'hea000000_04000000,
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64'he4000000_04000000,
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64'h03000000_00c20100,
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64'hdc000000_04000000,
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64'hd6000000_04000000,
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64'h03000000_80f0fa02,
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64'h3f000000_04000000,
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64'h03000000_00100000,
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@ -78,13 +94,13 @@ module bootrom (
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64'h30303030_30303140,
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64'h74726175_01000000,
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64'h02000000_006c6f72,
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64'h746e6f63_d2000000,
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64'h746e6f63_cc000000,
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64'h08000000_03000000,
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64'h00100000_00000000,
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64'h00000000_00000000,
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64'h5b000000_10000000,
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64'h03000000_ffff0000,
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64'h01000000_be000000,
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64'h01000000_b8000000,
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64'h08000000_03000000,
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64'h00333130_2d677562,
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64'h65642c76_63736972,
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@ -94,21 +110,21 @@ module bootrom (
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64'h6f632d67_75626564,
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64'h01000000_02000000,
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64'h006c6f72_746e6f63,
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64'hd2000000_08000000,
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64'hcc000000_08000000,
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64'h03000000_00000c00,
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64'h00000000_00000002,
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64'h00000000_5b000000,
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64'h10000000_03000000,
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64'h07000000_01000000,
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64'h03000000_01000000,
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64'hbe000000_10000000,
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64'hb8000000_10000000,
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64'h03000000_00000000,
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64'h30746e69_6c632c76,
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64'h63736972_1b000000,
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64'h0d000000_03000000,
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64'h00000030_30303030,
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64'h30324074_6e696c63,
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64'h01000000_b7000000,
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64'h01000000_b1000000,
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64'h00000000_03000000,
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64'h00007375_622d656c,
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64'h706d6973_00636f73,
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@ -131,8 +147,6 @@ module bootrom (
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64'h38407972_6f6d656d,
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64'h01000000_02000000,
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64'h02000000_02000000,
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64'h01000000_af000000,
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64'h04000000_03000000,
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64'h01000000_a9000000,
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64'h04000000_03000000,
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64'h00006374_6e692d75,
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@ -189,11 +203,11 @@ module bootrom (
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64'h00000000_01000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h14040000_0c010000,
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64'h84040000_06010000,
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64'h00000000_10000000,
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64'h11000000_28000000,
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64'h4c040000_38000000,
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64'h58050000_edfe0dd0,
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64'hbc040000_38000000,
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64'hc2050000_edfe0dd0,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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@ -207,9 +221,9 @@ module bootrom (
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00008402_07458593,
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64'h00000597_f1402573,
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64'h01f41413_0010041b
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64'h00000000_00008402,
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64'h07858593_00000597,
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64'hf1402573_047e4405
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};
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logic [$clog2(RomSize)-1:0] addr_q;
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@ -63,21 +63,49 @@ rv64ui-v-addi
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rv64ui-v-addiw
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rv64ui-v-addw
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rv64ui-v-and
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rv64ui-v-andi
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rv64ui-v-auipc
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rv64ui-v-beq
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rv64ui-v-bge
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rv64ui-v-bgeu
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rv64ui-v-andi
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rv64ui-v-blt
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rv64ui-v-bltu
|
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rv64ui-v-bne
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rv64ui-v-simple
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rv64ui-v-fence_i
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rv64ui-v-jal
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rv64ui-v-jalr
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rv64ui-v-lb
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rv64ui-v-lbu
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rv64ui-v-ld
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rv64ui-v-lh
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rv64ui-v-lhu
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rv64ui-v-lui
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rv64ui-v-lw
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rv64ui-v-lwu
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rv64ui-v-or
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rv64ui-v-ori
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rv64ui-v-sub
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rv64ui-v-subw
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rv64ui-v-sb
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rv64ui-v-sd
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rv64ui-v-sh
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rv64ui-v-simple
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rv64ui-v-sll
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rv64ui-v-slli
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rv64ui-v-lb
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rv64ui-v-slliw
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rv64ui-v-sllw
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rv64ui-v-slt
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rv64ui-v-slti
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rv64ui-v-sltiu
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rv64ui-v-sltu
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rv64ui-v-sra
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rv64ui-v-srai
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rv64ui-v-sraiw
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rv64ui-v-sraw
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rv64ui-v-srl
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rv64ui-v-srli
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rv64ui-v-srliw
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rv64ui-v-srlw
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rv64ui-v-sub
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rv64ui-v-subw
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rv64ui-v-sw
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rv64ui-v-xor
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rv64ui-v-xori
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|
|
@ -1,26 +1,26 @@
|
|||
rv64um-p-div
|
||||
rv64um-p-divu
|
||||
rv64um-p-divuw
|
||||
rv64um-p-divw
|
||||
rv64um-p-mul
|
||||
rv64um-p-mulh
|
||||
rv64um-p-mulhsu
|
||||
rv64um-p-mulhu
|
||||
rv64um-p-div
|
||||
rv64um-p-divu
|
||||
rv64um-p-mulw
|
||||
rv64um-p-rem
|
||||
rv64um-p-remu
|
||||
rv64um-p-mulw
|
||||
rv64um-p-divw
|
||||
rv64um-p-divuw
|
||||
rv64um-p-remw
|
||||
rv64um-p-remuw
|
||||
rv64um-p-remw
|
||||
rv64um-v-div
|
||||
rv64um-v-divu
|
||||
rv64um-v-divuw
|
||||
rv64um-v-divw
|
||||
rv64um-v-mul
|
||||
rv64um-v-mulh
|
||||
rv64um-v-mulhsu
|
||||
rv64um-v-mulhu
|
||||
rv64um-v-div
|
||||
rv64um-v-divu
|
||||
rv64um-v-mulw
|
||||
rv64um-v-rem
|
||||
rv64um-v-remu
|
||||
rv64um-v-mulw
|
||||
rv64um-v-divw
|
||||
rv64um-v-divuw
|
||||
rv64um-v-remw
|
||||
rv64um-v-remuw
|
||||
rv64um-v-remw
|
||||
|
|
|
|||
|
|
@ -32,7 +32,10 @@
|
|||
#include <unistd.h>
|
||||
|
||||
#include <fesvr/dtm.h>
|
||||
#include <fesvr/htif_hexwriter.h>
|
||||
#include <fesvr/elfloader.h>
|
||||
#include "remote_bitbang.h"
|
||||
|
||||
// This software is heavily based on Rocket Chip
|
||||
// Checkout this awesome project:
|
||||
// https://github.com/freechipsproject/rocket-chip/
|
||||
|
|
@ -102,6 +105,19 @@ EMULATOR DEBUG OPTIONS (only supported in debug build -- try `make debug`)\n",
|
|||
);
|
||||
}
|
||||
|
||||
// In case we use the DTM we do not want to use the JTAG
|
||||
// to preload the data but only use the DTM to host fesvr functionality.
|
||||
class preload_aware_dtm_t : public dtm_t {
|
||||
public:
|
||||
preload_aware_dtm_t(int argc, char **argv) : dtm_t(argc, argv) {}
|
||||
bool is_address_preloaded(addr_t taddr, size_t len) override { return true; }
|
||||
// We do not want to reset the hart here as the reset function in `dtm_t` seems to disregard
|
||||
// the privilege level and in general does not perform propper reset (despite the name).
|
||||
// As all our binaries in preloading will always start at the base of DRAM this should not
|
||||
// be such a big problem.
|
||||
void reset() {}
|
||||
};
|
||||
|
||||
int main(int argc, char **argv) {
|
||||
std::clock_t c_start = std::clock();
|
||||
auto t_start = std::chrono::high_resolution_clock::now();
|
||||
|
|
@ -263,12 +279,18 @@ done_processing:
|
|||
|
||||
#ifndef DROMAJO
|
||||
jtag = new remote_bitbang_t(rbb_port);
|
||||
dtm = new dtm_t(htif_argc, htif_argv);
|
||||
dtm = new preload_aware_dtm_t(htif_argc, htif_argv);
|
||||
signal(SIGTERM, handle_sigterm);
|
||||
#endif
|
||||
|
||||
std::unique_ptr<Variane_testharness> top(new Variane_testharness);
|
||||
|
||||
// Use an hitf hexwriter to read the binary data.
|
||||
htif_hexwriter_t htif(0x0, 1, -1);
|
||||
memif_t memif(&htif);
|
||||
reg_t entry;
|
||||
load_elf(htif_argv[1], &memif, &entry);
|
||||
|
||||
#if VM_TRACE
|
||||
Verilated::traceEverOn(true); // Verilator must compute traced signals
|
||||
std::unique_ptr<VerilatedVcdFILE> vcdfd(new VerilatedVcdFILE(vcdfile));
|
||||
|
|
@ -296,6 +318,10 @@ done_processing:
|
|||
}
|
||||
top->rst_ni = 1;
|
||||
|
||||
// Preload memory.
|
||||
size_t mem_size = 0x100000;
|
||||
memif.read(0x80000000, mem_size, (void *) top->ariane_testharness__DOT__i_sram__DOT__genblk1__BRA__0__KET____DOT__genblk2__DOT__i_ram__DOT__Mem_DP);
|
||||
|
||||
#ifndef DROMAJO
|
||||
while (!dtm->done() && !jtag->done()) {
|
||||
#else
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue