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Add missing instruction tracer file
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Michael Schaffner
Florian Zaruba
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c1fc73c326
commit
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1 changed files with 223 additions and 0 deletions
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src/util/instruction_tracer.sv
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src/util/instruction_tracer.sv
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// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba, ETH Zurich
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// Date: 16.05.2017
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// Description: Instruction Tracer Main Class
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import ariane_pkg::*;
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//pragma translate_off
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import uvm_pkg::*;
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`include "uvm_macros.svh"
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`include "instruction_tracer_defines.svh"
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`include "instruction_trace_item.svh"
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`include "exception_trace_item.svh"
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//pragma translate_on
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module instruction_tracer (
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instruction_tracer_if tracer_if,
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input logic[63:0] hart_id_i
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);
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// keep the decoded instructions in a queue
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logic [31:0] decode_queue [$];
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// keep the issued instructions in a queue
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logic [31:0] issue_queue [$];
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// issue scoreboard entries
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scoreboard_entry_t issue_sbe_queue [$];
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scoreboard_entry_t issue_sbe;
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// store resolved branches, get (mis-)predictions
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branchpredict_t bp [$];
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// shadow copy of the register files
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logic [63:0] gp_reg_file [32];
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logic [63:0] fp_reg_file [32];
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// 64 bit clock tick count
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longint unsigned clk_ticks;
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int f, commit_log;
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// address mapping
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// contains mappings of the form vaddr <-> paddr
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logic [63:0] store_mapping[$], load_mapping[$], address_mapping;
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// static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
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function void create_file(logic [63:0] hart_id);
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string fn, fn_commit_log;
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$sformat(fn, "trace_hart_%0.0f.log", hart_id);
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$sformat(fn_commit_log, "trace_hart_%0.0f_commit.log", hart_id);
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$display("[TRACER] Output filename is: %s", fn);
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f = $fopen(fn,"w");
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if (ENABLE_SPIKE_COMMIT_LOG) commit_log = $fopen(fn_commit_log, "w");
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endfunction : create_file
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task trace();
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automatic logic [31:0] decode_instruction, issue_instruction, issue_commit_instruction;
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automatic scoreboard_entry_t commit_instruction;
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// initialize register 0
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gp_reg_file = '{default:0};
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fp_reg_file = '{default:0};
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forever begin
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automatic branchpredict_t bp_instruction = '0;
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// new cycle, we are only interested if reset is de-asserted
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@(tracer_if.pck iff tracer_if.pck.rstn);
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// increment clock tick
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clk_ticks++;
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// -------------------
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// Instruction Decode
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// -------------------
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// we are decoding an instruction
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if (tracer_if.pck.fetch_valid && tracer_if.pck.fetch_ack) begin
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decode_instruction = tracer_if.pck.instruction;
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decode_queue.push_back(decode_instruction);
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end
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// -------------------
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// Instruction Issue
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// -------------------
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// we got a new issue ack, so put the element from the decode queue to
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// the issue queue
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if (tracer_if.pck.issue_ack && !tracer_if.pck.flush_unissued) begin
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issue_instruction = decode_queue.pop_front();
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issue_queue.push_back(issue_instruction);
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// also save the scoreboard entry to a separate issue queue
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issue_sbe_queue.push_back(scoreboard_entry_t'(tracer_if.pck.issue_sbe));
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end
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// --------------------
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// Address Translation
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// --------------------
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if (tracer_if.pck.st_valid) begin
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store_mapping.push_back(tracer_if.pck.st_paddr);
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end
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if (tracer_if.pck.ld_valid && !tracer_if.pck.ld_kill) begin
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load_mapping.push_back(tracer_if.pck.ld_paddr);
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end
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// ----------------------
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// Store predictions
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// ----------------------
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if (tracer_if.pck.resolve_branch.valid) begin
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bp.push_back(tracer_if.pck.resolve_branch);
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end
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// --------------
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// Commit
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// --------------
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// we are committing an instruction
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for (int i = 0; i < 2; i++) begin
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if (tracer_if.pck.commit_ack[i]) begin
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commit_instruction = scoreboard_entry_t'(tracer_if.pck.commit_instr[i]);
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issue_commit_instruction = issue_queue.pop_front();
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issue_sbe = issue_sbe_queue.pop_front();
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// check if the instruction retiring is a load or store, get the physical address accordingly
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if (tracer_if.pck.commit_instr[i].fu == LOAD)
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address_mapping = load_mapping.pop_front();
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else if (tracer_if.pck.commit_instr[i].fu == STORE)
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address_mapping = store_mapping.pop_front();
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if (tracer_if.pck.commit_instr[i].fu == CTRL_FLOW)
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bp_instruction = bp.pop_front();
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// the scoreboards issue entry still contains the immediate value as a result
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// check if the write back is valid, if not we need to source the result from the register file
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// as the most recent version of this register will be there.
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if (tracer_if.pck.we_gpr[i] || tracer_if.pck.we_fpr[i]) begin
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printInstr(issue_sbe, issue_commit_instruction, tracer_if.pck.wdata[i], address_mapping, tracer_if.pck.priv_lvl, tracer_if.pck.debug_mode, bp_instruction);
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end else if (is_rd_fpr(commit_instruction.op)) begin
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printInstr(issue_sbe, issue_commit_instruction, fp_reg_file[commit_instruction.rd], address_mapping, tracer_if.pck.priv_lvl, tracer_if.pck.debug_mode, bp_instruction);
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end else begin
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printInstr(issue_sbe, issue_commit_instruction, gp_reg_file[commit_instruction.rd], address_mapping, tracer_if.pck.priv_lvl, tracer_if.pck.debug_mode, bp_instruction);
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end
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end
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end
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// --------------
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// Exceptions
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// --------------
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if (tracer_if.pck.exception.valid && !(tracer_if.pck.debug_mode && tracer_if.pck.exception.cause == riscv::BREAKPOINT)) begin
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// print exception
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printException(tracer_if.pck.commit_instr[0].pc, tracer_if.pck.exception.cause, tracer_if.pck.exception.tval);
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end
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// ----------------------
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// Commit Registers
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// ----------------------
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// update shadow reg files here
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for (int i = 0; i < 2; i++) begin
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if (tracer_if.pck.we_gpr[i] && tracer_if.pck.waddr[i] != 5'b0) begin
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gp_reg_file[tracer_if.pck.waddr[i]] = tracer_if.pck.wdata[i];
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end else if (tracer_if.pck.we_fpr[i]) begin
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fp_reg_file[tracer_if.pck.waddr[i]] = tracer_if.pck.wdata[i];
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end
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end
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// --------------
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// Flush Signals
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// --------------
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// flush un-issued instructions
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if (tracer_if.pck.flush_unissued) begin
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flushDecode();
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end
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// flush whole pipeline
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if (tracer_if.pck.flush) begin
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flush();
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end
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end
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endtask
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// flush all decoded instructions
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function void flushDecode ();
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decode_queue = {};
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endfunction
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// flush everything, we took an exception/interrupt
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function void flush ();
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flushDecode();
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// clear all elements in the queue
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issue_queue = {};
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issue_sbe_queue = {};
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// also clear mappings
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store_mapping = {};
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load_mapping = {};
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bp = {};
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endfunction
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function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [63:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, branchpredict_t bp);
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automatic instruction_trace_item iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp);
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// print instruction to console
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automatic string print_instr = iti.printInstr();
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if (ENABLE_SPIKE_COMMIT_LOG && !debug_mode) begin
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$fwrite(commit_log, riscv::spikeCommitLog(sbe.pc, priv_lvl, instr, sbe.rd, result, is_rd_fpr(sbe.op)));
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end
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uvm_report_info( "Tracer", print_instr, UVM_HIGH);
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$fwrite(f, {print_instr, "\n"});
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endfunction
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function void printException(logic [63:0] pc, logic [63:0] cause, logic [63:0] tval);
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automatic exception_trace_item eti = new (pc, cause, tval);
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automatic string print_ex = eti.printException();
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uvm_report_info( "Tracer", print_ex, UVM_HIGH);
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$fwrite(f, {print_ex, "\n"});
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endfunction
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function void close();
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if (f) $fclose(f);
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if (ENABLE_SPIKE_COMMIT_LOG && commit_log) $fclose(commit_log);
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endfunction
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initial begin
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#15ns;
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create_file(hart_id_i);
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trace();
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end
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final begin
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close();
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end
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endmodule : instruction_tracer
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