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Florian Zaruba
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14
README.md
14
README.md
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@ -2,7 +2,7 @@
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# Ariane RISC-V CPU
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Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M and C extensions as specified in Volume I: User-Level ISA V 2.1 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore it is compliant to the draft external debug spec 0.13.
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Ariane is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.1 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore it is compliant to the draft external debug spec 0.13.
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It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.
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@ -92,16 +92,16 @@ If you call `simc` instead of `sim` it will run without the GUI. QuestaSim uses
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### CI Testsuites and Randomized Constrained Testing with Torture
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We provide two CI configuration files for Travis CI and GitLab CI that run the RISCV assembly tests, the RISCV benchmarks and a randomized RISCV Torture test. The difference between the two is that Travis CI runs these tests only on Verilator, whereas GitLab CI runs the same tests on QuestaSim and Verilator.
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We provide two CI configuration files for Travis CI and GitLab CI that run the RISCV assembly tests, the RISCV benchmarks and a randomized RISCV Torture test. The difference between the two is that Travis CI runs these tests only on Verilator, whereas GitLab CI runs the same tests on QuestaSim and Verilator.
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If you would like to run the CI test suites locally on your machine, follow any of the two scripts `ci.travis-ci-emul.sh` and `ci.travis-ci-emul.sh` (depending on whether you have QuestaSim or not). In particular, you have to get the required packages for your system, the paths in `ci/path-setup.sh` to match your setup, and run the installation and build scripts prior to running any of the tests suites.
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If you would like to run the CI test suites locally on your machine, follow any of the two scripts `ci.travis-ci-emul.sh` and `ci.travis-ci-emul.sh` (depending on whether you have QuestaSim or not). In particular, you have to get the required packages for your system, the paths in `ci/path-setup.sh` to match your setup, and run the installation and build scripts prior to running any of the tests suites.
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Once everything is set up and installed, you can run the tests suites as follows (using Verilator):
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```
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$ make verilate
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$ make run-asm-tests-verilator
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$ make run-benchmarks-verilator
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$ make verilate
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$ make run-asm-tests-verilator
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$ make run-benchmarks-verilator
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```
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In order to run randomized Torture tests, you first have to generate the randomized program prior to running the simulation:
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@ -111,7 +111,7 @@ $ make torture-gen
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$ make torture-rtest-verilator
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```
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This runs the randomized program on Spike and on the RTL target, and checks whether the two signatures match. The random instruction mix can be configured in the `./tmp/riscv-torture/config/default.config` file.
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This runs the randomized program on Spike and on the RTL target, and checks whether the two signatures match. The random instruction mix can be configured in the `./tmp/riscv-torture/config/default.config` file.
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# Contributing
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@ -32,7 +32,9 @@ package ariane_pkg;
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localparam BITS_SATURATION_COUNTER = 2;
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localparam NR_COMMIT_PORTS = 2;
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localparam logic [63:0] ISA_CODE = (1 << 2) // C - Compressed extension
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localparam logic [63:0] ISA_CODE =
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| (1 << 0) // A - Atomic extension
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| (1 << 2) // C - Compressed extension
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| (1 << 8) // I - RV32I/64I/128I base ISA
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| (1 << 12) // M - Integer Multiply/Divide extension
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| (0 << 13) // N - User level interrupts supported
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@ -218,7 +220,7 @@ package ariane_pkg;
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endcase
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endfunction
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function automatic logic is_amo_op (fu_op op);
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function automatic logic is_amo (fu_op op);
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case (op)
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AMO_LRD, AMO_SCD,
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AMO_SWAPD, AMO_ADDD,
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82
src/amo_buffer.sv
Normal file
82
src/amo_buffer.sv
Normal file
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@ -0,0 +1,82 @@
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// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba, ETH Zurich
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// Date: 20.09.2018
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// Description: Buffers AMO requests
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// This unit buffers an atomic memory operations for the cache subsyste.
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// Furthermore it handles interfacing with the commit stage
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module amo_buffer (
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic flush_i, // pipeline flush
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input logic valid_i, // AMO is valid
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output logic ready_o, // AMO unit is ready
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input ariane_pkg::amo_t amo_op_i, // AMO Operation
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input logic [63:0] paddr_i, // physical address of store which needs to be placed in the queue
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input logic [63:0] data_i, // data which is placed in the queue
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input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write)
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// D$
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output ariane_pkg::amo_req_t amo_req_o, // request to cache subsytem
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input ariane_pkg::amo_resp_t amo_resp_i, // response from cache subsystem
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// Auxiliary signals
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input logic amo_valid_commit_i, // We have a vaild AMO in the commit stage
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input logic no_st_pending_i // there is currently no store pending anymore
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);
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logic flush_amo_buffer;
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typedef struct packed {
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ariane_pkg::amo_t op;
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logic [63:0] paddr;
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logic [63:0] data;
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logic [1:0] size;
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} amo_op_t ;
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amo_op_t amo_data_in, amo_data_out;
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// validate this request as soon as all stores have drained and the AMO is in the commit stage
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assign amo_req_o.req = no_st_pending_i & amo_valid_commit_i;
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assign amo_req_o.amo_op = amo_data_out.op;
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assign amo_req_o.size = amo_data_out.size;
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assign amo_req_o.operand_a = amo_data_out.paddr;
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assign amo_req_o.operand_b = amo_data_out.data;
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assign amo_data_in.op = amo_op_i;
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assign amo_data_in.data = data_i;
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assign amo_data_in.paddr = paddr_i;
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assign amo_data_in.size = data_size_i;
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// only flush if we are currently not committing the AMO
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// e.g.: it is not speculative anymore
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assign flush_amo_buffer = flush_i & !amo_valid_commit_i;
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fifo_v2 #(
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.DEPTH ( 1 ),
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.ALM_EMPTY_TH ( 0 ),
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.ALM_FULL_TH ( 0 ),
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.dtype ( amo_op_t )
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) i_amo_fifo (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( flush_amo_buffer ),
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.testmode_i ( 1'b0 ),
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.full_o ( ), // not used as this FIFO has only a single element depth
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.empty_o ( ready_o ),
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.alm_full_o ( ), // left open
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.alm_empty_o ( ), // left open
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.data_i ( amo_data_in ),
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.push_i ( valid_i ),
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.data_o ( amo_data_out ),
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.pop_i ( amo_resp_i.ack )
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);
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endmodule
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@ -129,6 +129,7 @@ module ariane #(
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logic lsu_commit_commit_ex;
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logic lsu_commit_ready_ex_commit;
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logic no_st_pending_ex_commit;
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logic amo_valid_commit;
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// --------------
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// ID <-> COMMIT
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// --------------
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@ -196,6 +197,14 @@ module ariane #(
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icache_areq_o_t icache_areq_cache_ex;
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icache_dreq_i_t icache_dreq_if_cache;
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icache_dreq_o_t icache_dreq_cache_if;
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amo_req_t amo_req;
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amo_resp_t amo_resp;
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logic debug_req;
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// Disable debug during AMO commit
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assign debug_req = debug_req_i & ~amo_valid_commit;
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// ----------------
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// DCache <-> *
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// ----------------
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@ -344,6 +353,9 @@ module ariane #(
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.lsu_commit_ready_o ( lsu_commit_ready_ex_commit ), // to commit
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.lsu_exception_o ( lsu_exception_ex_id ),
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.no_st_pending_o ( no_st_pending_ex_commit ),
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.amo_valid_commit_i ( amo_valid_commit ),
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.amo_req_o ( amo_req ),
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.amo_resp_i ( amo_resp ),
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// CSR
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.csr_ready_o ( csr_ready_ex_id ),
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.csr_valid_i ( csr_valid_id_ex ),
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@ -389,7 +401,7 @@ module ariane #(
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.flush_dcache_i ( dcache_flush_ctrl_cache ),
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.exception_o ( ex_commit ),
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.debug_mode_i ( debug_mode_csr_id ),
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.debug_req_i ( debug_req_i ),
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.debug_req_i ( debug_req ),
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.single_step_i ( single_step_csr_commit ),
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.commit_instr_i ( commit_instr_id_commit ),
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.commit_ack_o ( commit_ack ),
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@ -397,11 +409,10 @@ module ariane #(
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.waddr_o ( waddr_commit_id ),
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.wdata_o ( wdata_commit_id ),
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.we_o ( we_commit_id ),
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.amo_commit_o ( ),
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.amo_valid_i ( ),
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.amo_sc_succ_i ( ),
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.commit_lsu_o ( lsu_commit_commit_ex ),
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.commit_lsu_ready_i ( lsu_commit_ready_ex_commit ),
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.amo_valid_commit_o ( amo_valid_commit ),
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.amo_resp_i ( amo_resp ),
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.commit_csr_o ( csr_commit_commit_ex ),
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.pc_o ( pc_commit ),
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.csr_op_o ( csr_op_commit_csr ),
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@ -422,8 +433,8 @@ module ariane #(
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) csr_regfile_i (
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.flush_o ( flush_csr_ctrl ),
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.halt_csr_o ( halt_csr_ctrl ),
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.commit_ack_i ( commit_ack ),
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.commit_instr_i ( commit_instr_id_commit ),
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.commit_ack_i ( commit_ack ),
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.ex_i ( ex_commit ),
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.csr_op_i ( csr_op_commit_csr ),
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.csr_addr_i ( csr_addr_ex_csr ),
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@ -454,6 +465,10 @@ module ariane #(
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.perf_data_o ( data_csr_perf ),
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.perf_data_i ( data_perf_csr ),
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.perf_we_o ( we_csr_perf ),
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.debug_req_i ( debug_req ),
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.ipi_i,
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.irq_i,
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.time_irq_i,
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.*
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);
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@ -531,10 +546,8 @@ module ariane #(
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.dcache_flush_i ( dcache_flush_ctrl_cache ),
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.dcache_flush_ack_o ( dcache_flush_ack_cache_ctrl ),
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// to commit stage
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.dcache_amo_commit_i ( amo_commit ),
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.dcache_amo_valid_o ( amo_valid ),
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.dcache_amo_sc_succ_o ( amo_sc_succ ),
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.dcache_amo_flush_i ( amo_flush ),
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.amo_req_i ( amo_req ),
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.amo_resp_o ( amo_resp ),
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.dcache_miss_o ( dcache_miss_cache_perf ),
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// from PTW, Load Unit and Store Unit
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.dcache_req_ports_i ( dcache_req_ports_ex_cache ),
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@ -36,6 +36,8 @@ module std_nbdcache #(
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AXI_BUS.Master bypass_if
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);
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assign amo_resp_o = '0;
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// -------------------------------
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// Controller <-> Arbiter
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// -------------------------------
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@ -45,6 +45,7 @@ module commit_stage #(
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// commit signals to ex
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output logic commit_lsu_o, // commit the pending store
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input logic commit_lsu_ready_i, // commit buffer of LSU is ready
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output logic amo_valid_commit_o, // valid AMO in commit stage
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input logic no_st_pending_i, // there is no store pending
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output logic commit_csr_o, // commit the pending CSR instruction
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output logic fence_i_o, // flush I$ and pipeline
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@ -52,6 +53,9 @@ module commit_stage #(
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output logic sfence_vma_o // flush TLBs and pipeline
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);
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assign waddr_o[0] = commit_instr_i[0].rd[4:0];
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assign waddr_o[1] = commit_instr_i[1].rd[4:0];
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assign pc_o = commit_instr_i[0].pc;
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// -------------------
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@ -63,6 +67,8 @@ module commit_stage #(
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commit_ack_o[0] = 1'b0;
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commit_ack_o[1] = 1'b0;
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amo_valid_commit_o = 1'b0;
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we_o[0] = 1'b0;
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we_o[1] = 1'b0;
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@ -145,6 +151,14 @@ module commit_stage #(
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// tell the controller to flush the D$
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fence_o = no_st_pending_i;
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end
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// ------------------
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// AMO
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// ------------------
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if (is_amo(commit_instr_i[0].op)) begin
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// TODO(zarubaf): Flush pipeline
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amo_valid_commit_o = 1'b1;
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commit_ack_o[0] = amo_resp_i.ack;
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end
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end
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// -----------------
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@ -210,8 +224,10 @@ module commit_stage #(
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exception_o.tval = commit_instr_i[0].ex.tval;
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end
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end
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// If we halted the processor don't take any exceptions
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if (halt_i) begin
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// Don't take any exceptions iff:
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// - If we halted the processor
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// - We are committing an AMO
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if (halt_i || amo_valid_commit_o) begin
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exception_o.valid = 1'b0;
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end
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end
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@ -126,7 +126,6 @@ module controller (
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flush_if_o = 1'b1;
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flush_unissued_instr_o = 1'b1;
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flush_id_o = 1'b1;
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flush_ex_o = 1'b1;
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end
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@ -105,9 +105,9 @@ module csr_regfile #(
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riscv::status_rv64_t mstatus_q, mstatus_d;
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riscv::satp_t satp_q, satp_d;
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riscv::dcsr_t dcsr_q, dcsr_d;
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logic mtvec_rst_load_q;// used to determine whether we came out of reset
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logic [63:0] dpc_q, dpc_d;
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logic [63:0] dscratch0_q, dscratch0_d;
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logic [63:0] mtvec_q, mtvec_d;
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@ -245,16 +245,16 @@ module csr_regfile #(
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dpc_d = dpc_q;
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dscratch0_d = dscratch0_q;
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mstatus_d = mstatus_q;
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// check whether we come out of reset
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// this is a workaround. some tools have issues
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// having boot_addr_i in the asynchronous
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// this is a workaround. some tools have issues
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// having boot_addr_i in the asynchronous
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// reset assignment to mtvec_d, even though
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// boot_addr_i will be assigned a constant
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// on the top-level.
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// on the top-level.
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if (mtvec_rst_load_q) begin
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mtvec_d = boot_addr_i + 'h40;
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end else begin
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end else begin
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mtvec_d = mtvec_q;
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end
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@ -525,6 +525,7 @@ module csr_regfile #(
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end
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// we've got a debug request (and we have an instruction which we can associate it to)
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// don't interrupt the AMO
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if (debug_req_i && commit_instr_i[0].valid) begin
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// save the PC
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dpc_d = pc_i;
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|
|
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|
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@ -58,6 +58,7 @@ module ex_stage #(
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output logic lsu_commit_ready_o, // commit queue is ready to accept another commit request
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output exception_t lsu_exception_o,
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output logic no_st_pending_o,
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input logic amo_valid_commit_i,
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// CSR
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output logic csr_ready_o,
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input logic csr_valid_i,
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@ -91,7 +92,8 @@ module ex_stage #(
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// interface to dcache
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input dcache_req_o_t [2:0] dcache_req_ports_i,
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output dcache_req_i_t [2:0] dcache_req_ports_o,
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output amo_req_t amo_req_o, // request to cache subsytem
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input amo_resp_t amo_resp_i, // response from cache subsystem
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// Performance counters
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output logic itlb_miss_o,
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output logic dtlb_miss_o
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@ -131,8 +133,10 @@ module ex_stage #(
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lsu lsu_i (
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.commit_i ( lsu_commit_i ),
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.commit_ready_o ( lsu_commit_ready_o ),
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.dcache_req_ports_i ( dcache_req_ports_i ),
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.dcache_req_ports_o ( dcache_req_ports_o ),
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.dcache_req_ports_i,
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.dcache_req_ports_o,
|
||||
.amo_req_o,
|
||||
.amo_resp_i,
|
||||
.*
|
||||
);
|
||||
|
||||
|
|
|
|||
35
src/lsu.sv
35
src/lsu.sv
|
|
@ -15,12 +15,13 @@
|
|||
import ariane_pkg::*;
|
||||
|
||||
module lsu #(
|
||||
parameter int unsigned ASID_WIDTH = 1
|
||||
parameter int unsigned ASID_WIDTH = 1
|
||||
)(
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic flush_i,
|
||||
output logic no_st_pending_o,
|
||||
input logic amo_valid_commit_i,
|
||||
|
||||
input fu_t fu_i,
|
||||
input fu_op operator_i,
|
||||
|
|
@ -59,6 +60,7 @@ module lsu #(
|
|||
output dcache_req_i_t [2:0] dcache_req_ports_o,
|
||||
// AMO interface
|
||||
output amo_req_t amo_req_o,
|
||||
input amo_resp_t amo_resp_i,
|
||||
output exception_t lsu_exception_o // to WB, signal exception status LD/ST exception
|
||||
|
||||
);
|
||||
|
|
@ -139,9 +141,17 @@ module lsu #(
|
|||
// Store Unit
|
||||
// ------------------
|
||||
store_unit i_store_unit (
|
||||
.clk_i,
|
||||
.rst_ni,
|
||||
.flush_i,
|
||||
.no_st_pending_o,
|
||||
|
||||
.valid_i ( st_valid_i ),
|
||||
.lsu_ctrl_i ( lsu_ctrl ),
|
||||
.pop_st_o ( pop_st ),
|
||||
.commit_i,
|
||||
.commit_ready_o,
|
||||
.amo_valid_commit_i,
|
||||
|
||||
.valid_o ( st_valid ),
|
||||
.trans_id_o ( st_trans_id ),
|
||||
|
|
@ -156,10 +166,12 @@ module lsu #(
|
|||
// Load Unit
|
||||
.page_offset_i ( page_offset ),
|
||||
.page_offset_matches_o ( page_offset_matches ),
|
||||
// AMOs
|
||||
.amo_req_o,
|
||||
.amo_resp_i,
|
||||
// to memory arbiter
|
||||
.req_port_i ( dcache_req_ports_i [2] ),
|
||||
.req_port_o ( dcache_req_ports_o [2] ),
|
||||
.*
|
||||
.req_port_o ( dcache_req_ports_o [2] )
|
||||
);
|
||||
|
||||
// ------------------
|
||||
|
|
@ -253,11 +265,7 @@ module lsu #(
|
|||
LD, SD: begin // double word
|
||||
be_i = 8'b1111_1111;
|
||||
end
|
||||
LW, LWU, SW,
|
||||
AMO_LRW, AMO_SCW,
|
||||
AMO_SWAPW, AMO_ADDW, AMO_ANDW, AMO_ORW,
|
||||
AMO_XORW, AMO_MAXW, AMO_MAXWU, AMO_MINW,
|
||||
AMO_MINWU: begin// word
|
||||
LW, LWU, SW: begin// word
|
||||
case (vaddr_i[2:0])
|
||||
3'b000: be_i = 8'b0000_1111;
|
||||
3'b001: be_i = 8'b0001_1110;
|
||||
|
|
@ -348,7 +356,7 @@ module lsu #(
|
|||
|
||||
if (data_misaligned) begin
|
||||
|
||||
if (lsu_ctrl.fu == LOAD || lsu_ctrl.fu == AMO) begin
|
||||
if (lsu_ctrl.fu == LOAD) begin
|
||||
misaligned_exception = {
|
||||
riscv::LD_ADDR_MISALIGNED,
|
||||
lsu_ctrl.vaddr,
|
||||
|
|
@ -402,15 +410,6 @@ module lsu #(
|
|||
.ready_o ( lsu_ready_o ),
|
||||
.*
|
||||
);
|
||||
// ------------
|
||||
// Assertions
|
||||
// ------------
|
||||
|
||||
`ifndef SYNTHESIS
|
||||
`ifndef VERILATOR
|
||||
// TODO
|
||||
`endif
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
// ------------------
|
||||
|
|
|
|||
|
|
@ -62,9 +62,11 @@ module store_unit (
|
|||
logic st_valid_without_flush;
|
||||
|
||||
// keep the data and the byte enable for the second cycle (after address translation)
|
||||
logic [63:0] st_data_n, st_data_q;
|
||||
logic [7:0] st_be_n, st_be_q;
|
||||
logic [1:0] st_data_size_n, st_data_size_q;
|
||||
logic [63:0] st_data_n, st_data_q;
|
||||
logic [7:0] st_be_n, st_be_q;
|
||||
logic [1:0] st_data_size_n, st_data_size_q;
|
||||
amo_t amo_op_d, amo_op_q;
|
||||
|
||||
logic [TRANS_ID_BITS-1:0] trans_id_n, trans_id_q;
|
||||
|
||||
// output assignments
|
||||
|
|
@ -193,11 +195,14 @@ module store_unit (
|
|||
end
|
||||
|
||||
logic store_buffer_valid, amo_buffer_valid;
|
||||
logic store_buffer_ready, amo_buffer_ready;
|
||||
|
||||
// multiplex between store unit and amo buffer
|
||||
assign store_buffer_valid = st_valid & (amo_op_q == AMO_NONE);
|
||||
assign amo_buffer_valid = st_valid & (amo_op_q != AMO_NONE);
|
||||
|
||||
assign st_ready = store_buffer_ready & amo_buffer_ready;
|
||||
|
||||
// ---------------
|
||||
// Store Queue
|
||||
// ---------------
|
||||
|
|
@ -210,7 +215,7 @@ module store_unit (
|
|||
.page_offset_matches_o,
|
||||
.commit_i,
|
||||
.commit_ready_o,
|
||||
.ready_o ( st_ready ),
|
||||
.ready_o ( store_buffer_ready ),
|
||||
.valid_i ( store_buffer_valid ),
|
||||
// the flush signal can be critical and we need this valid
|
||||
// signal to check whether the page_offset matches or not,
|
||||
|
|
@ -229,8 +234,6 @@ module store_unit (
|
|||
// ---------------
|
||||
// AMO Buffer
|
||||
// ---------------
|
||||
amo_t amo_op_q, amo_op_q;
|
||||
|
||||
always_comb begin
|
||||
amo_op_d = amo_op_q;
|
||||
|
||||
|
|
@ -250,11 +253,11 @@ module store_unit (
|
|||
end
|
||||
|
||||
amo_buffer i_amo_buffer (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( rst_ni ),
|
||||
.flush_i ( flush_i ),
|
||||
.clk_i,
|
||||
.rst_ni,
|
||||
.flush_i,
|
||||
.valid_i ( amo_buffer_valid ),
|
||||
.ready_o ( commit_ready_o ),
|
||||
.ready_o ( amo_buffer_ready ),
|
||||
.paddr_i ( paddr_i ),
|
||||
.amo_op_i ( amo_op_q ),
|
||||
.data_i ( st_data_q ),
|
||||
|
|
|
|||
|
|
@ -397,7 +397,7 @@ class instruction_trace_item;
|
|||
5'h14: mnemonic = "amomax.w";
|
||||
5'h18: mnemonic = "amominu.w";
|
||||
5'h1C: mnemonic = "amomax.w";
|
||||
default: printMnemonic("INVALID");
|
||||
default: return printMnemonic("INVALID");
|
||||
endcase
|
||||
end if (instr[14:12] == 3'h3) begin
|
||||
// doubles
|
||||
|
|
@ -413,7 +413,7 @@ class instruction_trace_item;
|
|||
5'h14: mnemonic = "amomax.d";
|
||||
5'h18: mnemonic = "amominu.d";
|
||||
5'h1C: mnemonic = "amomax.d";
|
||||
default: printMnemonic("INVALID");
|
||||
default: return printMnemonic("INVALID");
|
||||
endcase
|
||||
end else return printMnemonic("INVALID");
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue