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https://github.com/openhwgroup/cva6.git
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Modify AXI assertion and coverage model for easy utilization of WT and HPDcache (#2125)
This commit is contained in:
AEzzejjari
GitHub
parent
ca0cfbcb4e
commit
3cd458d03c
5 changed files with 28 additions and 30 deletions
28
verif/env/uvme/cov/uvme_axi_covg.sv
vendored
28
verif/env/uvme/cov/uvme_axi_covg.sv
vendored
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@ -67,15 +67,15 @@ covergroup cg_axi_w_channel(string name)
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endgroup : cg_axi_w_channel
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covergroup cg_axi_b_channel(string name)
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with function sample(uvma_axi_transaction_c item, bit RVA);
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with function sample(uvma_axi_transaction_c item, bit RVA, bit hpdcache);
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option.per_instance = 1;
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option.name = name;
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bid: coverpoint (item.b_id){
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bins one = {[1:3]};
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illegal_bins ILLEGAL_BINS = {2};
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ignore_bins IGN_EXID = {3} iff(!RVA);
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bins one = {[1:3]} iff(!hpdcache);
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illegal_bins ILLEGAL_BINS = {2} iff(!hpdcache);
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ignore_bins IGN_EXID = {3} iff(!RVA && !hpdcache);
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}
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bresp: coverpoint (item.b_resp){
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bins zero = {0};
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@ -88,13 +88,13 @@ covergroup cg_axi_b_channel(string name)
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endgroup : cg_axi_b_channel
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covergroup cg_axi_ar_channel(string name)
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with function sample(uvma_axi_transaction_c item, bit RVA);
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with function sample(uvma_axi_transaction_c item, bit RVA, bit hpdcache);
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option.per_instance = 1;
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option.name = name;
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arid: coverpoint (item.ar_id) {
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bins ID[] = {[0:1]};
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bins ID[] = {[0:1]} iff(!hpdcache);
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}
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arlen: coverpoint (item.ar_len) {
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@ -131,15 +131,15 @@ covergroup cg_axi_ar_channel(string name)
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endgroup : cg_axi_ar_channel
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covergroup cg_axi_r_channel(string name)
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with function sample(uvma_axi_transaction_c item, int index, bit RVA);
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with function sample(uvma_axi_transaction_c item, int index, bit RVA, bit hpdcache);
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option.per_instance = 1;
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option.name = name;
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rid: coverpoint (item.r_data_trs[index].r_id) {
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bins ID[] = {[0:3]};
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illegal_bins ILLEGAL_BINS = {2};
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ignore_bins IGN_EXID = {3} iff(!RVA);
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bins ID[] = {[0:3]} iff(!hpdcache);
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illegal_bins ILLEGAL_BINS = {2} iff(!hpdcache);
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ignore_bins IGN_EXID = {3} iff(!RVA && !hpdcache);
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}
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rlast: coverpoint (item.r_data_trs[index].r_last);
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@ -165,6 +165,7 @@ class uvme_axi_covg_c extends uvm_component;
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uvme_cva6_cntxt_c cntxt;
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uvme_cva6_cfg_c cfg;
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bit RVA;
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bit HPDCache;
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// TLM
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_resp_fifo;
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@ -226,6 +227,7 @@ function void uvme_axi_covg_c::build_phase(uvm_phase phase);
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end
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RVA = cfg.ext_a_supported;
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HPDCache = cfg.HPDCache_supported;
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uvme_axi_cov_resp_fifo = new("uvme_axi_cov_resp_fifo" , this);
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@ -249,14 +251,14 @@ task uvme_axi_covg_c::run_phase(uvm_phase phase);
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UVMA_AXI_ACCESS_WRITE : begin
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w_axi_cg.sample(resp_item, RVA);
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b_axi_cg.sample(resp_item, RVA);
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b_axi_cg.sample(resp_item, RVA, HPDCache);
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end
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UVMA_AXI_ACCESS_READ : begin
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ar_axi_cg.sample(resp_item, RVA);
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ar_axi_cg.sample(resp_item, RVA, HPDCache);
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for(int i = 0; i <= resp_item.ar_len; i++) begin
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r_axi_cg.sample(resp_item, i, RVA);
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r_axi_cg.sample(resp_item, i, RVA, HPDCache);
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end
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end
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3
verif/env/uvme/uvme_cva6_cfg.sv
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3
verif/env/uvme/uvme_cva6_cfg.sv
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@ -47,6 +47,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
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// Zicond extension
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rand bit ext_zicond_supported;
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rand bit HPDCache_supported;
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//pmp entries
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rand int nr_pmp_entries;
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@ -58,6 +59,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
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`uvm_field_int ( cov_model_enabled , UVM_DEFAULT )
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`uvm_field_int ( trn_log_enabled , UVM_DEFAULT )
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`uvm_field_int ( ext_zicond_supported , UVM_DEFAULT )
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`uvm_field_int ( HPDCache_supported , UVM_DEFAULT )
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`uvm_field_int ( nr_pmp_entries , UVM_DEFAULT )
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`uvm_field_int ( sys_clk_period , UVM_DEFAULT + UVM_DEC)
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@ -138,6 +140,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
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dm_halt_addr_valid == 1;
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dm_exception_addr_valid == 1;
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nmi_addr_valid == 1;
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HPDCache_supported == 1;
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}
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constraint ext_const {
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@ -7,7 +7,8 @@
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//
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// Original Author: Alae Eddine EZ ZEJJARI (alae-eddine.ez-zejjari@external.thalesgroup.com) – sub-contractor MU-Electronics for Thales group
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module uvmt_axi_assert (uvma_axi_intf axi_assert_if);
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module uvmt_axi_assert#(int HPDCache=2)
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(uvma_axi_intf axi_assert_if);
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import uvm_pkg::*;
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@ -25,7 +26,7 @@ module uvmt_axi_assert (uvma_axi_intf axi_assert_if);
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uvma_axi_amo_assert axi_amo_assert(.axi_assert(axi_assert_if));
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uvmt_cva6_axi_assert cva6_axi_assert(.axi_assert_if(axi_assert_if));
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uvmt_cva6_axi_assert#(HPDCache) cva6_axi_assert(.axi_assert_if(axi_assert_if));
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endmodule : uvmt_axi_assert
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@ -11,19 +11,19 @@
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`include "uvm_macros.svh"
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module uvmt_cva6_axi_assert (uvma_axi_intf axi_assert_if);
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module uvmt_cva6_axi_assert#(int HPDCache=2)
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(uvma_axi_intf axi_assert_if);
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import uvm_pkg::*;
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//check if the CVA6 identify read transaction with an ID equal to 0 or 1
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property AXI4_CVA6_ARID;
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@(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_id == 0 || axi_assert_if.ar_id == 1 || (axi_assert_if.ar_id == 3 && axi_assert_if.ar_lock == 1);
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@(posedge axi_assert_if.clk && (HPDCache != 2)) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_id == 0 || axi_assert_if.ar_id == 1 || (axi_assert_if.ar_id == 3 && axi_assert_if.ar_lock == 1);
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endproperty
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//check if the CVA6 identify write transaction with an ID equal to 0 or 1
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property AXI4_CVA6_AWID;
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@(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_id == 1 || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_atop != 0) || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_lock == 1);
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@(posedge axi_assert_if.clk && (HPDCache != 2)) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_id == 1 || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_atop != 0) || (axi_assert_if.aw_id == 3 && axi_assert_if.aw_lock == 1);
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endproperty
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//Check if user-defined extension for read address channel is equal to 0b00
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@ -58,12 +58,12 @@ module uvmt_cva6_axi_assert (uvma_axi_intf axi_assert_if);
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//Check if AWCACHE is always equal to 0b0000
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property AXI4_CVA6_AWCACHE;
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@(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_cache == 2;
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@(posedge axi_assert_if.clk && (HPDCache != 2)) disable iff (!axi_assert_if.rst_n) axi_assert_if.aw_valid |-> axi_assert_if.aw_cache == 2;
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endproperty
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//Check if ARCACHE is always equal to 0b0000
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property AXI4_CVA6_ARCACHE;
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@(posedge axi_assert_if.clk) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_cache == 2;
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@(posedge axi_assert_if.clk && (HPDCache != 2)) disable iff (!axi_assert_if.rst_n) axi_assert_if.ar_valid |-> axi_assert_if.ar_cache == 2;
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endproperty
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//Check if Protection attributes for write transaction always take the 0b000
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@ -103,14 +103,11 @@ module uvmt_cva6_axi_assert (uvma_axi_intf axi_assert_if);
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/********************************************** Assert Property ******************************************************/
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// TODO: commented when integrating HPDCache
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if (0) begin
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cva6_arid : assert property (AXI4_CVA6_ARID)
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else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARID");
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cva6_awid : assert property (AXI4_CVA6_AWID)
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else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWID");
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end
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cva6_aruser : assert property (AXI4_CVA6_ARUSER)
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else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARUSER");
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@ -130,14 +127,11 @@ module uvmt_cva6_axi_assert (uvma_axi_intf axi_assert_if);
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cva6_awregion : assert property (AXI4_CVA6_AWREGION)
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else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWREGION");
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// TODO: commented when integrating HPDCache
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if (0) begin
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cva6_arcache : assert property (AXI4_CVA6_ARCACHE)
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else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARCAHCE");
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cva6_awcache : assert property (AXI4_CVA6_AWCACHE)
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else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_AWCAHCE");
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end
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cva6_arprot : assert property (AXI4_CVA6_ARPROT)
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else `uvm_error (" AXI4 protocol checks assertion ", "Violation of AXI4_CVA6_ARPROT");
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@ -199,5 +193,3 @@ module uvmt_cva6_axi_assert (uvma_axi_intf axi_assert_if);
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endmodule : uvmt_cva6_axi_assert
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@ -86,7 +86,7 @@ module uvmt_cva6_tb;
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);
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//bind assertion module for axi interface
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bind uvmt_cva6_dut_wrap
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uvmt_axi_assert axi_assert(.axi_assert_if(axi_if));
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uvmt_axi_assert #(CVA6Cfg.DCacheType) axi_assert(.axi_assert_if(axi_if));
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// DUT Wrapper Interfaces
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uvmt_rvfi_if #(
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