mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-24 22:27:10 -04:00
Support Spike Parameters in cva6.py and bump core-v-verif (#1976)
This commit is contained in:
valentinThomazic
GitHub
parent
bcecaf1bdf
commit
3dc1f23a9d
5 changed files with 58 additions and 24 deletions
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@ -1 +1 @@
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Subproject commit 54c64747595d291f2b158ffcb5c8275f3db8828d
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Subproject commit 64f8dc104cf553476827faf8119e311a2899d495
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@ -121,7 +121,7 @@ endif
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###############################################################################
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spike:
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LD_LIBRARY_PATH="$$(realpath ../../tools/spike/lib):$$LD_LIBRARY_PATH" \
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$(tool_path)/spike $(spike_stepout) $(spike_extension) --log-commits --isa=$(variant) --priv=$(priv) -l $(elf)
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$(tool_path)/spike $(spike_stepout) $(spike_extension) --log-commits --isa=$(variant) --priv=$(priv) $(spike_params) -l $(elf)
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cp $(log).iss $(log)
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###############################################################################
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@ -114,7 +114,7 @@ def get_generator_cmd(simulator, simulator_yaml, cov, exp, debug_cmd):
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sys.exit(RET_FAIL)
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def parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv):
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def parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv, spike_params):
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"""Parse ISS YAML to get the simulation command
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Args:
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@ -145,6 +145,7 @@ def parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv):
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cmd = re.sub(r"\<isscomp_opts\>", isscomp_opts, cmd)
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cmd = re.sub(r"\<issrun_opts\>", issrun_opts, cmd)
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cmd = re.sub(r"\<isspostrun_opts\>", isspostrun_opts, cmd)
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cmd = re.sub(r"\<spike_params\>", spike_params, cmd)
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if m: cmd = re.sub(r"\<xlen\>", m.group('xlen'), cmd)
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if iss == "ovpsim":
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cmd = re.sub(r"\<cfg_path\>", setting_dir, cmd)
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@ -156,7 +157,6 @@ def parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv):
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else:
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cmd = re.sub(r"\<variant\>", isa, cmd)
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cmd = re.sub(r"\<priv\>", priv, cmd)
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return cmd
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logging.error("Cannot find ISS %0s" % iss)
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sys.exit(RET_FAIL)
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@ -411,7 +411,7 @@ def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd, linker):
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def run_assembly(asm_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
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setting_dir, debug_cmd, linker, priv):
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setting_dir, debug_cmd, linker, priv, spike_params):
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"""Run a directed assembly test with ISS
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Args:
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@ -462,7 +462,7 @@ def run_assembly(asm_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, outp
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else:
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log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, asm, target))
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log_list.append(log)
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base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv)
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base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv, spike_params)
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cmd = get_iss_cmd(base_cmd, elf, target, log)
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logging.info("[%0s] Running ISS simulation: %s" % (iss, cmd))
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run_cmd(cmd, 500, debug_cmd = debug_cmd)
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@ -502,7 +502,7 @@ def run_assembly_from_dir(asm_test_dir, iss_yaml, isa, mabi, gcc_opts, iss,
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# python3 run.py --target rv64gc --iss=spike,verilator --elf_tests bbl.o
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def run_elf(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
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setting_dir, debug_cmd):
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setting_dir, debug_cmd, priv, spike_params):
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"""Run a directed c test with ISS
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Args:
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@ -538,7 +538,7 @@ def run_elf(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
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run_cmd("mkdir -p %s/%s_sim" % (output_dir, iss))
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log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, c, target))
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log_list.append(log)
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base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv)
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base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv, spike_params)
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cmd = get_iss_cmd(base_cmd, elf, target, log)
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logging.info("[%0s] Running ISS simulation: %s" % (iss, cmd))
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if "veri" in iss: ratio = 35
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@ -550,7 +550,7 @@ def run_elf(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
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def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
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setting_dir, debug_cmd, linker, priv):
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setting_dir, debug_cmd, linker, priv, spike_params):
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"""Run a directed c test with ISS
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Args:
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@ -599,7 +599,7 @@ def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
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else:
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log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, c, target))
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log_list.append(log)
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base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv)
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base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv, spike_params)
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cmd = get_iss_cmd(base_cmd, elf, target, log)
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logging.info("[%0s] Running ISS simulation: %s" % (iss, cmd))
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run_cmd(cmd, 300, debug_cmd = debug_cmd)
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@ -639,7 +639,7 @@ def run_c_from_dir(c_test_dir, iss_yaml, isa, mabi, gcc_opts, iss,
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def iss_sim(test_list, output_dir, iss_list, iss_yaml, iss_opts,
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isa, target, setting_dir, timeout_s, debug_cmd, priv):
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isa, target, setting_dir, timeout_s, debug_cmd, priv, spike_params):
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"""Run ISS simulation with the generated test program
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Args:
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@ -655,7 +655,7 @@ def iss_sim(test_list, output_dir, iss_list, iss_yaml, iss_opts,
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"""
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for iss in iss_list.split(","):
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log_dir = ("%s/%s_sim" % (output_dir, iss))
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base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv)
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base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv, spike_params)
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logging.info("%s sim log dir: %s" % (iss, log_dir))
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run_cmd_output(["mkdir", "-p", log_dir])
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for test in test_list:
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@ -763,6 +763,7 @@ def read_seed(arg):
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'must be a non-negative integer.'
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.format(arg))
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def parse_args(cwd):
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"""Create a command line parser.
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@ -871,7 +872,8 @@ def parse_args(cwd):
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help="Run test with a specific seed")
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parser.add_argument("--isa_extension", type=str, default="",
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help="Choose additional z, s, x extensions")
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parser.add_argument("--spike_params", type=str, default="",
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help="Spike command line parameters, run spike --help and spike --print-params to see more")
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rsg = parser.add_argument_group('Random seeds',
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'To control random seeds, use at most one '
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'of the --start_seed, --seed or --seed_yaml '
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@ -907,12 +909,13 @@ def parse_args(cwd):
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'greater than 1.')
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sys.exit(RET_FAIL)
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# We've parsed all the arguments from the command line; default values
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# can be set in the config file. Read that here.
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load_config(args, cwd)
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return args
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def get_full_spike_param_args(spike_params: list[str]):
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return ' '.join(list(map(lambda s: "--param=" + s, spike_params.split(','))))
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def load_config(args, cwd):
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"""
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Load configuration from the command line and the configuration file.
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@ -1026,10 +1029,14 @@ def load_config(args, cwd):
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if not args.testlist:
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args.testlist = args.custom_target + "/testlist.yaml"
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args.spike_params = get_full_spike_param_args(args.spike_params)
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def incorrect_version_exit(tool, tool_version, required_version):
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logging.error(f"You are currently using version {tool_version} of {tool}, should be: {required_version}. Please install or reinstall it with the installation script." )
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sys.exit(RET_FAIL)
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def check_gcc_version():
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REQUIRED_GCC_VERSION = 11
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@ -1042,6 +1049,7 @@ def check_gcc_version():
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if int(gcc_version_number[0]) < REQUIRED_GCC_VERSION:
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incorrect_version_exit("GCC", gcc_version_string, f">={REQUIRED_GCC_VERSION}")
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def check_spike_version():
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# Get Spike hash from core-v-verif submodule
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spike_hash = subprocess.run('git log -1 --pretty=tformat:%h -- $SPIKE_SRC_DIR/..', capture_output=True, text=True, shell=True, cwd=os.environ.get("SPIKE_SRC_DIR"))
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@ -1060,6 +1068,7 @@ def check_spike_version():
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if user_spike_version_string != spike_version:
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incorrect_version_exit("Spike", user_spike_version_string, spike_version)
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def check_verilator_version():
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REQUIRED_VERILATOR_VERSION = "5.008"
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@ -1070,11 +1079,13 @@ def check_verilator_version():
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if REQUIRED_VERILATOR_VERSION != verilator_version:
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incorrect_version_exit("Verilator", verilator_version, REQUIRED_VERILATOR_VERSION)
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def check_tools_version():
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check_gcc_version()
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check_spike_version()
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check_verilator_version()
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def main():
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"""This is the main entry point."""
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try:
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@ -1085,6 +1096,10 @@ def main():
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os.environ["RISCV_DV_ROOT"] = cwd + "/dv"
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os.environ["CVA6_DV_ROOT"] = cwd + "/../env/corev-dv"
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args = parse_args(cwd)
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# We've parsed all the arguments from the command line; default values
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# can be set in the config file. Read that here.
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load_config(args, cwd)
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if args.axi_active == "yes":
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args.issrun_opts = args.issrun_opts + " +uvm_set_config_int=*uvm_test_top,force_axi_mode,1"
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elif args.axi_active == "no":
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@ -1154,7 +1169,8 @@ def main():
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# path_asm_test is an assembly file
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elif os.path.isfile(full_path) or args.debug:
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run_assembly(full_path, args.iss_yaml, args.isa, args.target, args.mabi, args.gcc_opts,
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args.iss, output_dir, args.core_setting_dir, args.debug, args.linker, args.priv)
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args.iss, output_dir, args.core_setting_dir, args.debug, args.linker,
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args.priv, args.spike_params)
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else:
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logging.error('%s does not exist' % full_path)
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sys.exit(RET_FAIL)
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@ -1173,7 +1189,8 @@ def main():
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# path_c_test is a c file
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elif os.path.isfile(full_path) or args.debug:
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run_c(full_path, args.iss_yaml, args.isa, args.target, args.mabi, args.gcc_opts,
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args.iss, output_dir, args.core_setting_dir, args.debug, args.linker, args.priv)
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args.iss, output_dir, args.core_setting_dir, args.debug, args.linker,
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args.priv, args.spike_params)
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else:
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logging.error('%s does not exist' % full_path)
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sys.exit(RET_FAIL)
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@ -1187,7 +1204,7 @@ def main():
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# path_elf_test is an elf file
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if os.path.isfile(full_path) or args.debug:
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run_elf(full_path, args.iss_yaml, args.isa, args.target, args.mabi, args.gcc_opts,
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args.iss, output_dir, args.core_setting_dir, args.debug)
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args.iss, output_dir, args.core_setting_dir, args.debug, args.spike_params)
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else:
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logging.error('%s does not exist' % full_path)
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sys.exit(RET_FAIL)
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@ -1266,7 +1283,8 @@ def main():
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# path_asm_test is an assembly file
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elif os.path.isfile(path_asm_test):
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run_assembly(path_asm_test, args.iss_yaml, args.isa, args.target, args.mabi, gcc_opts,
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args.iss, output_dir, args.core_setting_dir, args.debug, args.linker, args.priv)
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args.iss, output_dir, args.core_setting_dir, args.debug, args.linker,
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args.priv, args.spike_params)
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else:
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if not args.debug:
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logging.error('%s does not exist' % path_asm_test)
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@ -1295,7 +1313,8 @@ def main():
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# path_c_test is a C file
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elif os.path.isfile(path_c_test):
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run_c(path_c_test, args.iss_yaml, args.isa, args.target, args.mabi, gcc_opts,
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args.iss, output_dir, args.core_setting_dir, args.debug, args.linker, args.priv)
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args.iss, output_dir, args.core_setting_dir, args.debug, args.linker,
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args.priv, args.spike_params)
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else:
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if not args.debug:
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logging.error('%s does not exist' % path_c_test)
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@ -1313,7 +1332,8 @@ def main():
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# Run ISS simulation
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if args.steps == "all" or re.match(".*iss_sim.*", args.steps):
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iss_sim(matched_list, output_dir, args.iss, args.iss_yaml, args.iss_opts,
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args.isa, args.target, args.core_setting_dir, args.iss_timeout, args.debug, args.priv)
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args.isa, args.target, args.core_setting_dir, args.iss_timeout, args.debug,
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args.priv, args.spike_params)
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# Compare ISS simulation result
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if args.steps == "all" or re.match(".*iss_cmp.*", args.steps):
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@ -18,7 +18,7 @@
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# Always keep this value in sync with the settings of RTL simulators (cf.
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# <issrun_opts> values below).
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cmd: >
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make spike steps=2000000 variant=<variant> priv=<priv> elf=<elf> tool_path=<tool_path> log=<log>
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make spike steps=2000000 variant=<variant> priv=<priv> elf=<elf> tool_path=<tool_path> log=<log> spike_params='<spike_params>'
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###############################################################################
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# Verilator
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14
verif/tests/custom/spike_params/misa_csr_we.S
Normal file
14
verif/tests/custom/spike_params/misa_csr_we.S
Normal file
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@ -0,0 +1,14 @@
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.globl main
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main:
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# Disable extension C in MISA Extensions field
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li x1, 0x00141100
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csrw 0x301, x1
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# If misa_we=true, following code should provoke illegal instruction exceptions
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# And test should timeout
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c.li x2, 0
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c.addi x2, 2
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c.addi x2, -2
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li x1, 0
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slli x1, x1, 1
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addi x1, x1, 1
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sw x1, tohost, t5
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