mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-19 03:44:46 -04:00
Re-organize CVA6 and APU (#725)
* Initial repository re-organization (#662) Initial attempt to split core from APU. Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org> Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr> Compile `corev_apu` (#667) * Makefile verilates corev_apu * Cleanup README * Fix URL to repo * Cleaned-up Makefile verilates corev_apu Signed-off-by: Mike Thompson <mike@openhwgroup.org> Add extended verification support (#685) * Makefile, riscv_pkg.sv: Select C64A6 or CV32A6 according to variant variable Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com> * add RVFI tracer and debug support New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv - RVFI ports are added to ariane module - rvfi_tracer.sv is a module added in ariane-testharness.sv - RVFI_TRACE enables RVFI trace generation Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch> Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com> * Move example_tb from cva6 to core-v-verif project Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com> * Makefile: remove useless rule for vsim Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com> * Makefile: add timescale definition when vsim is used Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com> * Makefile: add vcs support (fix #570) Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com> * rvfi_tracer.sv: fix compilation error raised by vcs Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com> * Makefile: use only 2 threads for verilator when using 4 threads, tests from riscv-compliance and riscv-tests test suite are randomly stucked with rv32ima configuration Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com> * Flist.cva6: cleanup for synthesis workflow Thales synthesis workflow does not manage comments at end of lines Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com> * Support FPGA generation - ariane_xilinx.sv: fix AXI bus expansion - .gitignore, Makefile, run.tcl: fix paths Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com> * riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug) Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com> * Create cva6_config_pkg to setup 32- or 64-bit configuration According to selected configuration, Makefile calls cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com> * Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures needed for dc_shell Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com> * cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com> * riscv_pkg.sv: clean-up the cva6_config_pkg import Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com> * Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com> Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com> Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch> * Add lfsr.sv to manifest Signed-off-by: Mike Thompson <mike@openhwgroup.org> * Directory re-organzation * fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726) into the new file organisation Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com> * move mmu_sv32 and mmu_sv39, move bootrom, update path (#729) Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com> Co-authored-by: Mike Thompson <mike@openhwgroup.org> Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com> Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch> Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
This commit is contained in:
André Sintzoff
GitHub
parent
f5cbaa92e9
commit
3ddf797e95
913 changed files with 299651 additions and 205 deletions
2
.gitignore
vendored
2
.gitignore
vendored
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@ -26,7 +26,7 @@ build/
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*.o
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uart
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work-ver/*
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fpga/work-fpga
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corev_apu/fpga/work-fpga
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stdout/
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work-dpi/
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tb/riscv-isa-sim/
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|
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80
.gitmodules
vendored
80
.gitmodules
vendored
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@ -1,57 +1,57 @@
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[submodule "src/axi_mem_if"]
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path = src/axi_mem_if
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[submodule "corev_apu/axi_mem_if"]
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path = corev_apu/axi_mem_if
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url = https://github.com/pulp-platform/axi_mem_if.git
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[submodule "src/axi_node"]
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path = src/axi_node
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[submodule "corev_apu/axi_node"]
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path = corev_apu/axi_node
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url = https://github.com/pulp-platform/axi_node.git
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[submodule "src/fpga-support"]
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path = src/fpga-support
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[submodule "corev_apu/fpga-support"]
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path = corev_apu/fpga-support
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url = https://github.com/pulp-platform/fpga-support.git
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[submodule "src/common_cells"]
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path = src/common_cells
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[submodule "common/submodules/common_cells"]
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path = common/submodules/common_cells
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url = https://github.com/pulp-platform/common_cells.git
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[submodule "src/axi"]
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path = src/axi
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[submodule "corev_apu/axi"]
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path = corev_apu/axi
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url = https://github.com/pulp-platform/axi.git
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[submodule "src/register_interface"]
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path = src/register_interface
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[submodule "corev_apu/register_interface"]
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path = corev_apu/register_interface
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url = https://github.com/pulp-platform/register_interface.git
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[submodule "fpga/src/apb_uart"]
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path = fpga/src/apb_uart
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[submodule "corev_apu/fpga/src/apb_uart"]
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path = corev_apu/fpga/src/apb_uart
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url = https://github.com/pulp-platform/apb_uart.git
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[submodule "fpga/src/apb_node"]
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path = fpga/src/apb_node
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[submodule "corev_apu/fpga/src/apb_node"]
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path = corev_apu/fpga/src/apb_node
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url = https://github.com/pulp-platform/apb_node.git
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[submodule "fpga/src/axi2apb"]
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path = fpga/src/axi2apb
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url = https://github.com/pulp-platform/axi2apb.git
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[submodule "fpga/src/axi_slice"]
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path = fpga/src/axi_slice
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url = https://github.com/pulp-platform/axi_slice.git
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[submodule "src/tech_cells_generic"]
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path = src/tech_cells_generic
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[submodule "corev_apu/fpga/src/axi2apb"]
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path = corev_apu/fpga/src/axi2apb
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url = https://github.com/pulp-platform/axi2apb.git
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[submodule "corev_apu/fpga/src/axi_slice"]
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path = corev_apu/fpga/src/axi_slice
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url = https://github.com/pulp-platform/axi_slice.git
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[submodule "corev_apu/src/tech_cells_generic"]
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path = corev_apu/src/tech_cells_generic
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url = https://github.com/pulp-platform/tech_cells_generic.git
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[submodule "src/fpu"]
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path = src/fpu
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[submodule "core/fpu"]
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path = core/fpu
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url = https://github.com/pulp-platform/fpnew.git
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[submodule "fpga/src/ariane-ethernet"]
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path = fpga/src/ariane-ethernet
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[submodule "corev_apu/fpga/src/ariane-ethernet"]
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path = corev_apu/fpga/src/ariane-ethernet
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url = https://github.com/lowRISC/ariane-ethernet.git
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[submodule "src/axi_riscv_atomics"]
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path = src/axi_riscv_atomics
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[submodule "corev_apu/src/axi_riscv_atomics"]
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path = corev_apu/src/axi_riscv_atomics
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url = https://github.com/pulp-platform/axi_riscv_atomics.git
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[submodule "src/riscv-dbg"]
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path = src/riscv-dbg
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[submodule "corev_apu/riscv-dbg"]
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path = corev_apu/riscv-dbg
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url = https://github.com/pulp-platform/riscv-dbg.git
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[submodule "src/rv_plic"]
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path = src/rv_plic
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[submodule "corev_apu/rv_plic"]
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path = corev_apu/rv_plic
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url = https://github.com/pulp-platform/rv_plic.git
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[submodule "fpga/src/apb_timer"]
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path = fpga/src/apb_timer
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[submodule "corev_apu/fpga/src/apb_timer"]
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path = corev_apu/fpga/src/apb_timer
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url = https://github.com/pulp-platform/apb_timer.git
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[submodule "tb/dromajo"]
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path = tb/dromajo
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[submodule "corev_apu/tb/dromajo"]
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path = corev_apu/tb/dromajo
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url = https://github.com/kabylkas/dromajo.git
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[submodule "tb/common_verification"]
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path = tb/common_verification
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[submodule "corev_apu/tb/common_verification"]
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path = corev_apu/tb/common_verification
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url = https://github.com/pulp-platform/common_verification.git
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91
CHANGELOG.md
91
CHANGELOG.md
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@ -12,6 +12,97 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
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- Fix non-setable MEIE bit in MIE CSR
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- Bump `fpnew` to `v0.6.2`
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- Restructured directories to separate CVA6 core from CVA6-APU (FPGA emulation platform for the core). See the [README](README.md#new-directory-structure) for details.
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#### Moved Package files
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```
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include/riscv_pkg.sv ==> core/include/riscv_pkg.sv
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src/riscv-dbg/src/dm_pkg.sv ==> corev_apu/riscv-dbg/src/dm_pkg.sv
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include/ariane_pkg.sv ==> core/include/ariane_pkg.sv
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include/std_cache_pkg.sv ==> core/include/std_cache_pkg.sv
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include/wt_cache_pkg.sv ==> core/include/wt_cache_pkg.sv
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src/axi/src/axi_pkg.sv ==> corev_apu/axi/src/axi_pkg.sv
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src/register_interface/src/reg_intf.sv ==> corev_apu/register_interface/src/reg_intf.sv
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src/register_interface/src/reg_intf_pkg.sv ==> corev_apu/register_interface/src/reg_intf_pkg.sv
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include/axi_intf.sv ==> core/include/axi_intf.sv
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tb/ariane_soc_pkg.sv ==> corev_apu/tb/ariane_soc_pkg.sv
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tb/ariane_axi_soc_pkg.sv ==> corev_apu/tb/ariane_axi_soc_pkg.sv
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include/ariane_axi_pkg.sv ==> core/include/ariane_axi_pkg.sv
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src/fpu/src/fpnew_pkg.sv ==> core/fpu/src/fpnew_pkg.sv
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src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ==> core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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```
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#### Moved standalone components
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```
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src/frontend/*.sv ==> core/frontend/*.sv
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src/cache_subsystem/*.sv ==> core/cache_subsystem/*.sv (excluding std_no_dcache.sv)
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bootrom/*.sv ==> corev_apu/bootrom/*.sv
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src/clint/*.sv ==> corev_apu/clint/*.sv
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fpga/src/axi2apb/src/*.sv ==> corev_apu/fpga/src/axi2apb/src/*.sv
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fpga/src/apb_timer/*.sv ==> corev_apu/fpga/src/apb_timer/*.sv
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fpga/src/axi_slice/src/*.sv ==> corev_apu/fpga/src/axi_slice/src/*.sv
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src/axi_node/src/*.sv ==> corev_apu/axi_node/src/*.sv
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src/axi_riscv_atomics/src/*.sv ==> corev_apu/src/axi_riscv_atomics/src/*.sv
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src/axi_mem_if/src/*.sv ==> corev_apu/axi_mem_if/src/*.sv
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src/pmp/src/*.sv ==> core/pmp/src/*.sv
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src/rv_plic/rtl/rv_plic_target.sv ==> corev_apu/rv_plic/rtl/rv_plic_target.sv
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src/rv_plic/rtl/rv_plic_gateway.sv ==> corev_apu/rv_plic/rtl/rv_plic_gateway.sv
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src/rv_plic/rtl/plic_regmap.sv ==> corev_apu/rv_plic/rtl/plic_regmap.sv
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src/rv_plic/rtl/plic_top.sv ==> corev_apu/rv_plic/rtl/plic_top.sv
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src/riscv-dbg/src/dmi_cdc.sv ==> corev_apu/riscv-dbg/src/dmi_cdc.sv
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src/riscv-dbg/src/dmi_jtag.sv ==> corev_apu/riscv-dbg/src/dmi_jtag.sv
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src/riscv-dbg/src/dmi_jtag_tap.sv ==> corev_apu/riscv-dbg/src/dmi_jtag_tap.sv
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src/riscv-dbg/src/dm_csrs.sv ==> corev_apu/riscv-dbg/src/dm_csrs.sv
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src/riscv-dbg/src/dm_mem.sv ==> corev_apu/riscv-dbg/src/dm_mem.sv
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src/riscv-dbg/src/dm_sba.sv ==> corev_apu/riscv-dbg/src/dm_sba.sv
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src/riscv-dbg/src/dm_top.sv ==> corev_apu/riscv-dbg/src/dm_top.sv
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src/riscv-dbg/debug_rom/debug_rom.sv ==> corev_apu/riscv-dbg/debug_rom/debug_rom.sv
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src/register_interface/src/apb_to_reg.sv ==> corev_apu/register_interface/src/apb_to_reg.sv
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src/axi/src/axi_multicut.sv ==> corev_apu/axi/src/axi_multicut.sv
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src/common_cells/src/deprecated/generic_fifo.sv ==> common/submodules/common_cells/src/deprecated/generic_fifo.sv
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src/common_cells/src/deprecated/pulp_sync.sv ==> common/submodules/common_cells/src/deprecated/pulp_sync.sv
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src/common_cells/src/deprecated/find_first_one.sv ==> common/submodules/common_cells/src/deprecated/find_first_one.sv
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src/common_cells/src/rstgen_bypass.sv ==> common/submodules/common_cells/src/rstgen_bypass.sv
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src/common_cells/src/rstgen.sv ==> common/submodules/common_cells/src/rstgen.sv
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src/common_cells/src/stream_mux.sv ==> common/submodules/common_cells/src/stream_mux.sv
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src/common_cells/src/stream_demux.sv ==> common/submodules/common_cells/src/stream_demux.sv
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src/common_cells/src/exp_backoff.sv ==> common/submodules/common_cells/src/exp_backoff.sv
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src/util/axi_master_connect.sv ==> common/local/util/axi_master_connect.sv
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src/util/axi_slave_connect.sv ==> common/local/util/axi_slave_connect.sv
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src/util/axi_master_connect_rev.sv ==> common/local/util/axi_master_connect_rev.sv
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src/util/axi_slave_connect_rev.sv ==> common/local/util/axi_slave_connect_rev.sv
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src/axi/src/axi_cut.sv ==> corev_apu/axi/src/axi_cut.sv
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src/axi/src/axi_join.sv ==> corev_apu/axi/src/axi_join.sv
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src/axi/src/axi_delayer.sv ==> corev_apu/axi/src/axi_delayer.sv
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src/axi/src/axi_to_axi_lite.sv ==> corev_apu/axi/src/axi_to_axi_lite.sv
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src/common_cells/src/unread.sv ==> common/submodules/common_cells/src/unread.sv
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src/common_cells/src/sync.sv ==> common/submodules/common_cells/src/sync.sv
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src/common_cells/src/cdc_2phase.sv ==> common/submodules/common_cells/src/cdc_2phase.sv
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src/common_cells/src/spill_register.sv ==> common/submodules/common_cells/src/spill_register.sv
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src/common_cells/src/sync_wedge.sv ==> common/submodules/common_cells/src/sync_wedge.sv
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src/common_cells/src/edge_detect.sv ==> common/submodules/common_cells/src/edge_detect.sv
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src/common_cells/src/stream_arbiter.sv ==> common/submodules/common_cells/src/stream_arbiter.sv
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src/common_cells/src/stream_arbiter_flushable.sv ==> common/submodules/common_cells/src/stream_arbiter_flushable.sv
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src/common_cells/src/deprecated/fifo_v1.sv ==> common/submodules/common_cells/src/deprecated/fifo_v1.sv
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src/common_cells/src/deprecated/fifo_v2.sv ==> common/submodules/common_cells/src/deprecated/fifo_v2.sv
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src/common_cells/src/fifo_v3.sv ==> common/submodules/common_cells/src/fifo_v3.sv
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src/common_cells/src/rr_arb_tree.sv ==> common/submodules/common_cells/src/rr_arb_tree.sv
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src/common_cells/src/deprecated/rrarbiter.sv ==> common/submodules/common_cells/src/deprecated/rrarbiter.sv
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src/common_cells/src/stream_delay.sv ==> common/submodules/common_cells/src/stream_delay.sv
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src/common_cells/src/lfsr_8bit.sv ==> common/submodules/common_cells/src/lfsr_8bit.sv
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src/common_cells/src/lfsr_16bit.sv ==> common/submodules/common_cells/src/lfsr_16bit.sv
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src/common_cells/src/delta_counter.sv ==> common/submodules/common_cells/src/delta_counter.sv
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src/common_cells/src/counter.sv ==> common/submodules/common_cells/src/counter.sv
|
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src/common_cells/src/shift_reg.sv ==> common/submodules/common_cells/src/shift_reg.sv
|
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src/tech_cells_generic/src/pulp_clock_gating.sv ==> corev_apu/src/tech_cells_generic/src/pulp_clock_gating.sv
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src/tech_cells_generic/src/cluster_clock_inverter.sv ==> corev_apu/src/tech_cells_generic/src/cluster_clock_inverter.sv
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src/tech_cells_generic/src/pulp_clock_mux2.sv ==> corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv
|
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tb/ariane_testharness.sv ==> corev_apu/tb/ariane_testharness.sv
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tb/ariane_peripherals.sv ==> corev_apu/tb/ariane_peripherals.sv
|
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tb/common/uart.sv ==> corev_apu/tb/common/uart.sv
|
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tb/common/SimDTM.sv ==> corev_apu/tb/common/SimDTM.sv
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tb/common/SimJTAG.sv ==> corev_apu/tb/common/SimJTAG.sv
|
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```
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|
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### 4.2.0 - 2019-06-04
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|
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286
Makefile
286
Makefile
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@ -36,6 +36,7 @@ root-dir := $(dir $(mkfile_path))
|
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|
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support_verilator_4 := $(shell ($(verilator) --version | grep '4\.') > /dev/null 2>&1 ; echo $$?)
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ifeq ($(support_verilator_4), 0)
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verilator_threads := 2
|
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endif
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|
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ifndef RISCV
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@ -72,29 +73,36 @@ endif
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|
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# Sources
|
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# Package files -> compile first
|
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ariane_pkg := include/riscv_pkg.sv \
|
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src/riscv-dbg/src/dm_pkg.sv \
|
||||
include/ariane_pkg.sv \
|
||||
include/std_cache_pkg.sv \
|
||||
include/wt_cache_pkg.sv \
|
||||
src/axi/src/axi_pkg.sv \
|
||||
src/register_interface/src/reg_intf.sv \
|
||||
src/register_interface/src/reg_intf_pkg.sv \
|
||||
include/axi_intf.sv \
|
||||
tb/ariane_soc_pkg.sv \
|
||||
tb/ariane_axi_soc_pkg.sv \
|
||||
include/ariane_axi_pkg.sv \
|
||||
src/fpu/src/fpnew_pkg.sv \
|
||||
src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
|
||||
ifeq ($(findstring 32, $(variant)),32)
|
||||
ariane_pkg := core/include/cv32a6_imac_sv0_config_pkg.sv
|
||||
else
|
||||
ariane_pkg := core/include/cv64a6_imacfd_sv39_config_pkg.sv
|
||||
endif
|
||||
ariane_pkg += core/include/riscv_pkg.sv \
|
||||
corev_apu/riscv-dbg/src/dm_pkg.sv \
|
||||
core/include/ariane_pkg.sv \
|
||||
core/include/ariane_rvfi_pkg.sv \
|
||||
core/include/std_cache_pkg.sv \
|
||||
core/include/wt_cache_pkg.sv \
|
||||
corev_apu/axi/src/axi_pkg.sv \
|
||||
corev_apu/register_interface/src/reg_intf.sv \
|
||||
corev_apu/register_interface/src/reg_intf_pkg.sv \
|
||||
core/include/axi_intf.sv \
|
||||
corev_apu/tb/rvfi_pkg.sv \
|
||||
corev_apu/tb/ariane_soc_pkg.sv \
|
||||
corev_apu/tb/ariane_axi_soc_pkg.sv \
|
||||
core/include/ariane_axi_pkg.sv \
|
||||
core/fpu/src/fpnew_pkg.sv \
|
||||
core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
|
||||
ariane_pkg := $(addprefix $(root-dir), $(ariane_pkg))
|
||||
|
||||
# utility modules
|
||||
util := include/instr_tracer_pkg.sv \
|
||||
src/util/instr_tracer_if.sv \
|
||||
src/util/instr_tracer.sv \
|
||||
src/tech_cells_generic/src/cluster_clock_gating.sv \
|
||||
tb/common/mock_uart.sv \
|
||||
src/util/sram.sv
|
||||
util := core/include/instr_tracer_pkg.sv \
|
||||
common/local/util/instr_tracer_if.sv \
|
||||
common/local/util/instr_tracer.sv \
|
||||
corev_apu/src/tech_cells_generic/src/cluster_clock_gating.sv \
|
||||
corev_apu/tb/common/mock_uart.sv \
|
||||
common/local/util/sram.sv
|
||||
|
||||
ifdef spike-tandem
|
||||
util += tb/common/spike.sv
|
||||
|
|
@ -106,7 +114,7 @@ test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) \
|
|||
$(wildcard tb/test/*/*_pkg.sv*)
|
||||
|
||||
# DPI
|
||||
dpi := $(patsubst tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard tb/dpi/*.cc))
|
||||
dpi := $(patsubst corev_apu/tb/dpi/%.cc, ${dpi-library}/%.o, $(wildcard corev_apu/tb/dpi/*.cc))
|
||||
|
||||
# filter spike stuff if tandem is not activated
|
||||
ifndef spike-tandem
|
||||
|
|
@ -118,13 +126,14 @@ ifndef DROMAJO
|
|||
dpi := $(filter-out ${dpi-library}/dromajo_cosim_dpi.o, $(dpi))
|
||||
endif
|
||||
|
||||
dpi_hdr := $(wildcard tb/dpi/*.h)
|
||||
dpi_hdr := $(wildcard corev_apu/tb/dpi/*.h)
|
||||
dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr))
|
||||
CFLAGS := -I$(QUESTASIM_HOME)/include \
|
||||
-I$(VCS_HOME)/include \
|
||||
-I$(RISCV)/include \
|
||||
-I$(SPIKE_ROOT)/include \
|
||||
$(if $(DROMAJO), -I../tb/dromajo/src,) \
|
||||
-std=c++11 -I../tb/dpi -O3
|
||||
$(if $(DROMAJO), -I../corev_apu/tb/dromajo/src,) \
|
||||
-std=c++11 -I../corev_apu/tb/dpi -O3
|
||||
|
||||
ifdef XCELIUM_HOME
|
||||
CFLAGS += -I$(XCELIUM_HOME)/tools/include
|
||||
|
|
@ -136,97 +145,99 @@ ifdef spike-tandem
|
|||
CFLAGS += -Itb/riscv-isa-sim/install/include/spike
|
||||
endif
|
||||
|
||||
|
||||
# this list contains the standalone components
|
||||
src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
|
||||
$(filter-out src/fpu/src/fpnew_pkg.sv, $(wildcard src/fpu/src/*.sv)) \
|
||||
$(filter-out src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \
|
||||
$(wildcard src/fpu/src/fpu_div_sqrt_mvp/hdl/*.sv)) \
|
||||
$(wildcard src/frontend/*.sv) \
|
||||
$(filter-out src/cache_subsystem/std_no_dcache.sv, \
|
||||
$(wildcard src/cache_subsystem/*.sv)) \
|
||||
$(wildcard bootrom/*.sv) \
|
||||
$(wildcard src/clint/*.sv) \
|
||||
$(wildcard fpga/src/axi2apb/src/*.sv) \
|
||||
$(wildcard fpga/src/apb_timer/*.sv) \
|
||||
$(wildcard fpga/src/axi_slice/src/*.sv) \
|
||||
$(wildcard src/axi_node/src/*.sv) \
|
||||
$(wildcard src/axi_riscv_atomics/src/*.sv) \
|
||||
$(wildcard src/axi_mem_if/src/*.sv) \
|
||||
$(wildcard src/pmp/src/*.sv) \
|
||||
$(wildcard src/mmu_sv32/*.sv) \
|
||||
$(wildcard src/mmu_sv39/*.sv) \
|
||||
src/rv_plic/rtl/rv_plic_target.sv \
|
||||
src/rv_plic/rtl/rv_plic_gateway.sv \
|
||||
src/rv_plic/rtl/plic_regmap.sv \
|
||||
src/rv_plic/rtl/plic_top.sv \
|
||||
src/riscv-dbg/src/dmi_cdc.sv \
|
||||
src/riscv-dbg/src/dmi_jtag.sv \
|
||||
src/riscv-dbg/src/dmi_jtag_tap.sv \
|
||||
src/riscv-dbg/src/dm_csrs.sv \
|
||||
src/riscv-dbg/src/dm_mem.sv \
|
||||
src/riscv-dbg/src/dm_sba.sv \
|
||||
src/riscv-dbg/src/dm_top.sv \
|
||||
src/riscv-dbg/debug_rom/debug_rom.sv \
|
||||
src/register_interface/src/apb_to_reg.sv \
|
||||
src/axi/src/axi_multicut.sv \
|
||||
src/common_cells/src/deprecated/generic_fifo.sv \
|
||||
src/common_cells/src/deprecated/pulp_sync.sv \
|
||||
src/common_cells/src/deprecated/find_first_one.sv \
|
||||
src/common_cells/src/rstgen_bypass.sv \
|
||||
src/common_cells/src/rstgen.sv \
|
||||
src/common_cells/src/stream_mux.sv \
|
||||
src/common_cells/src/stream_demux.sv \
|
||||
src/common_cells/src/exp_backoff.sv \
|
||||
src/util/axi_master_connect.sv \
|
||||
src/util/axi_slave_connect.sv \
|
||||
src/util/axi_master_connect_rev.sv \
|
||||
src/util/axi_slave_connect_rev.sv \
|
||||
src/axi/src/axi_cut.sv \
|
||||
src/axi/src/axi_join.sv \
|
||||
src/axi/src/axi_delayer.sv \
|
||||
src/axi/src/axi_to_axi_lite.sv \
|
||||
src/fpga-support/rtl/SyncSpRamBeNx64.sv \
|
||||
src/common_cells/src/unread.sv \
|
||||
src/common_cells/src/sync.sv \
|
||||
src/common_cells/src/cdc_2phase.sv \
|
||||
src/common_cells/src/spill_register.sv \
|
||||
src/common_cells/src/sync_wedge.sv \
|
||||
src/common_cells/src/edge_detect.sv \
|
||||
src/common_cells/src/stream_arbiter.sv \
|
||||
src/common_cells/src/stream_arbiter_flushable.sv \
|
||||
src/common_cells/src/deprecated/fifo_v1.sv \
|
||||
src/common_cells/src/deprecated/fifo_v2.sv \
|
||||
src/common_cells/src/fifo_v3.sv \
|
||||
src/common_cells/src/lzc.sv \
|
||||
src/common_cells/src/popcount.sv \
|
||||
src/common_cells/src/rr_arb_tree.sv \
|
||||
src/common_cells/src/deprecated/rrarbiter.sv \
|
||||
src/common_cells/src/stream_delay.sv \
|
||||
src/common_cells/src/lfsr.sv \
|
||||
src/common_cells/src/lfsr_8bit.sv \
|
||||
src/common_cells/src/lfsr_16bit.sv \
|
||||
src/common_cells/src/delta_counter.sv \
|
||||
src/common_cells/src/counter.sv \
|
||||
src/common_cells/src/shift_reg.sv \
|
||||
src/tech_cells_generic/src/pulp_clock_gating.sv \
|
||||
src/tech_cells_generic/src/cluster_clock_inverter.sv \
|
||||
src/tech_cells_generic/src/pulp_clock_mux2.sv \
|
||||
tb/ariane_testharness.sv \
|
||||
tb/ariane_peripherals.sv \
|
||||
tb/common/uart.sv \
|
||||
tb/common/SimDTM.sv \
|
||||
tb/common/SimJTAG.sv
|
||||
src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) \
|
||||
$(filter-out core/fpu/src/fpnew_pkg.sv, $(wildcard core/fpu/src/*.sv)) \
|
||||
$(filter-out core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv, \
|
||||
$(wildcard core/fpu/src/fpu_div_sqrt_mvp/hdl/*.sv)) \
|
||||
$(wildcard core/frontend/*.sv) \
|
||||
$(wildcard core/mmu_sv32/*.sv) \
|
||||
$(wildcard core/mmu_sv39/*.sv) \
|
||||
$(filter-out core/cache_subsystem/std_no_dcache.sv, \
|
||||
$(wildcard core/cache_subsystem/*.sv)) \
|
||||
$(wildcard corev_apu/bootrom/*.sv) \
|
||||
$(wildcard corev_apu/clint/*.sv) \
|
||||
$(wildcard corev_apu/fpga/src/axi2apb/src/*.sv) \
|
||||
$(wildcard corev_apu/fpga/src/apb_timer/*.sv) \
|
||||
$(wildcard corev_apu/fpga/src/axi_slice/src/*.sv) \
|
||||
$(wildcard corev_apu/axi_node/src/*.sv) \
|
||||
$(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv) \
|
||||
$(wildcard corev_apu/axi_mem_if/src/*.sv) \
|
||||
$(wildcard core/pmp/src/*.sv) \
|
||||
corev_apu/rv_plic/rtl/rv_plic_target.sv \
|
||||
corev_apu/rv_plic/rtl/rv_plic_gateway.sv \
|
||||
corev_apu/rv_plic/rtl/plic_regmap.sv \
|
||||
corev_apu/rv_plic/rtl/plic_top.sv \
|
||||
corev_apu/riscv-dbg/src/dmi_cdc.sv \
|
||||
corev_apu/riscv-dbg/src/dmi_jtag.sv \
|
||||
corev_apu/riscv-dbg/src/dmi_jtag_tap.sv \
|
||||
corev_apu/riscv-dbg/src/dm_csrs.sv \
|
||||
corev_apu/riscv-dbg/src/dm_mem.sv \
|
||||
corev_apu/riscv-dbg/src/dm_sba.sv \
|
||||
corev_apu/riscv-dbg/src/dm_top.sv \
|
||||
corev_apu/riscv-dbg/debug_rom/debug_rom.sv \
|
||||
corev_apu/register_interface/src/apb_to_reg.sv \
|
||||
corev_apu/axi/src/axi_multicut.sv \
|
||||
common/submodules/common_cells/src/deprecated/generic_fifo.sv \
|
||||
common/submodules/common_cells/src/deprecated/pulp_sync.sv \
|
||||
common/submodules/common_cells/src/deprecated/find_first_one.sv \
|
||||
common/submodules/common_cells/src/rstgen_bypass.sv \
|
||||
common/submodules/common_cells/src/rstgen.sv \
|
||||
common/submodules/common_cells/src/stream_mux.sv \
|
||||
common/submodules/common_cells/src/stream_demux.sv \
|
||||
common/submodules/common_cells/src/exp_backoff.sv \
|
||||
common/local/util/axi_master_connect.sv \
|
||||
common/local/util/axi_slave_connect.sv \
|
||||
common/local/util/axi_master_connect_rev.sv \
|
||||
common/local/util/axi_slave_connect_rev.sv \
|
||||
corev_apu/axi/src/axi_cut.sv \
|
||||
corev_apu/axi/src/axi_join.sv \
|
||||
corev_apu/axi/src/axi_delayer.sv \
|
||||
corev_apu/axi/src/axi_to_axi_lite.sv \
|
||||
corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv \
|
||||
common/submodules/common_cells/src/unread.sv \
|
||||
common/submodules/common_cells/src/sync.sv \
|
||||
common/submodules/common_cells/src/cdc_2phase.sv \
|
||||
common/submodules/common_cells/src/spill_register.sv \
|
||||
common/submodules/common_cells/src/sync_wedge.sv \
|
||||
common/submodules/common_cells/src/edge_detect.sv \
|
||||
common/submodules/common_cells/src/stream_arbiter.sv \
|
||||
common/submodules/common_cells/src/stream_arbiter_flushable.sv \
|
||||
common/submodules/common_cells/src/deprecated/fifo_v1.sv \
|
||||
common/submodules/common_cells/src/deprecated/fifo_v2.sv \
|
||||
common/submodules/common_cells/src/fifo_v3.sv \
|
||||
common/submodules/common_cells/src/lzc.sv \
|
||||
common/submodules/common_cells/src/popcount.sv \
|
||||
common/submodules/common_cells/src/rr_arb_tree.sv \
|
||||
common/submodules/common_cells/src/deprecated/rrarbiter.sv \
|
||||
common/submodules/common_cells/src/stream_delay.sv \
|
||||
common/submodules/common_cells/src/lfsr.sv \
|
||||
common/submodules/common_cells/src/lfsr_8bit.sv \
|
||||
common/submodules/common_cells/src/lfsr_16bit.sv \
|
||||
common/submodules/common_cells/src/delta_counter.sv \
|
||||
common/submodules/common_cells/src/counter.sv \
|
||||
common/submodules/common_cells/src/shift_reg.sv \
|
||||
corev_apu/src/tech_cells_generic/src/pulp_clock_gating.sv \
|
||||
corev_apu/src/tech_cells_generic/src/cluster_clock_inverter.sv \
|
||||
corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv \
|
||||
corev_apu/tb/ariane_testharness.sv \
|
||||
corev_apu/tb/ariane_peripherals.sv \
|
||||
corev_apu/tb/rvfi_tracer.sv \
|
||||
corev_apu/tb/common/uart.sv \
|
||||
corev_apu/tb/common/SimDTM.sv \
|
||||
corev_apu/tb/common/SimJTAG.sv
|
||||
|
||||
src := $(addprefix $(root-dir), $(src))
|
||||
|
||||
uart_src := $(wildcard fpga/src/apb_uart/src/*.vhd)
|
||||
uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/*.vhd)
|
||||
uart_src := $(addprefix $(root-dir), $(uart_src))
|
||||
|
||||
fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildcard fpga/src/ariane-ethernet/*.sv)
|
||||
fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv)
|
||||
fpga_src := $(addprefix $(root-dir), $(fpga_src))
|
||||
|
||||
# look for testbenches
|
||||
tbs := tb/ariane_tb.sv tb/ariane_testharness.sv
|
||||
tbs := corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv
|
||||
# RISCV asm tests and benchmark setup (used for CI)
|
||||
# there is a definesd test-list with selected CI tests
|
||||
riscv-test-dir := tmp/riscv-tests/build/isa/
|
||||
|
|
@ -243,7 +254,8 @@ riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list
|
|||
riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)
|
||||
|
||||
# Search here for include files (e.g.: non-standalone components)
|
||||
incdir := src/common_cells/include/
|
||||
incdir := common/submodules/common_cells/include/
|
||||
|
||||
# Compile and sim flags
|
||||
compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+$(defines)
|
||||
uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=LOW
|
||||
|
|
@ -285,6 +297,18 @@ else
|
|||
questa-cmd += +jtag_rbb_enable=0
|
||||
endif
|
||||
|
||||
vcs_build: $(dpi-library)/ariane_dpi.so
|
||||
vlogan -full64 -nc -sverilog -ntb_opts uvm-1.2
|
||||
vlogan -full64 -nc -sverilog -ntb_opts uvm-1.2 +define+WT_CACHE +define+RVFI_TRACE $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi
|
||||
vlogan -full64 -nc -sverilog -ntb_opts uvm-1.2 +define+WT_CACHE +define+RVFI_TRACE $(filter %.sv,$(util)) +incdir+common/local/util+core/include/+src/util/+$(VCS_HOME)/etc/uvm-1.2/dpi
|
||||
vhdlan -full64 $(filter %.vhd,$(uart_src))
|
||||
vlogan -full64 -nc -sverilog -ntb_opts uvm-1.2 -assert svaext +define+WT_CACHE +define+RVFI_TRACE $(filter %.sv,$(src)) +incdir+core/include/+common/submodules/common_cells/include/+common/local/util/+$(VCS_HOME)/etc/uvm-1.2/dpi
|
||||
vlogan -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+RVFI_TRACE
|
||||
vcs -full64 -timescale=1ns/1ns -ntb_opts uvm-1.2 work.ariane_tb
|
||||
|
||||
vcs: vcs_build
|
||||
./simv +permissive -sv_lib work-dpi/ariane_dpi +permissive-off ++$(elf-bin) | tee vcs.log
|
||||
|
||||
# Build the TB and module using QuestaSim
|
||||
build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
|
||||
# Optimize top level
|
||||
|
|
@ -294,24 +318,24 @@ build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ari
|
|||
$(library)/.build-srcs: $(util) $(library)
|
||||
vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(ariane_pkg)) $(list_incdir) -suppress 2583
|
||||
# vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(ariane_pkg))
|
||||
vlog$(questa_version) $(compile_flag) -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
|
||||
vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -work $(library) $(filter %.sv,$(util)) $(list_incdir) -suppress 2583
|
||||
# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
|
||||
vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src))
|
||||
# vcom$(questa_version) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(src))
|
||||
vlog$(questa_version) $(compile_flag) -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
|
||||
vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
|
||||
touch $(library)/.build-srcs
|
||||
|
||||
# build TBs
|
||||
$(library)/.build-tb: $(dpi)
|
||||
# Compile top level
|
||||
vlog$(questa_version) $(compile_flag) -sv $(tbs) -work $(library)
|
||||
vlog$(questa_version) $(compile_flag) -timescale "1ns / 1ns" -sv $(tbs) -work $(library)
|
||||
touch $(library)/.build-tb
|
||||
|
||||
$(library):
|
||||
vlib${questa_version} $(library)
|
||||
|
||||
# compile DPIs
|
||||
$(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr)
|
||||
$(dpi-library)/%.o: corev_apu/tb/dpi/%.cc $(dpi_hdr)
|
||||
mkdir -p $(dpi-library)
|
||||
$(CXX) -shared -fPIC -std=c++0x -Bsymbolic $(CFLAGS) -c $< -o $@
|
||||
|
||||
|
|
@ -324,7 +348,6 @@ $(dpi-library)/ariane_dpi.so: $(dpi)
|
|||
# the test names are defined in ci/riscv-asm-tests.list, and in ci/riscv-benchmarks.list
|
||||
# if you want to run in batch mode, use make <testname> batch-mode=1
|
||||
# alternatively you can call make sim elf-bin=<path/to/elf-bin> in order to load an arbitrary binary
|
||||
|
||||
generate-trace-vsim:
|
||||
make sim preload=$(preload) elf-bin= batch-mode=1
|
||||
make generate-trace
|
||||
|
|
@ -404,7 +427,7 @@ CVA6_HOME ?= $(realpath -s $(root-dir))
|
|||
XRUN_INCDIR :=+incdir+$(CVA6_HOME)/src/axi_node \
|
||||
+incdir+$(CVA6_HOME)/src/common_cells/include \
|
||||
+incdir+$(CVA6_HOME)/src/util
|
||||
XRUN_TB := $(addprefix $(CVA6_HOME)/, tb/ariane_tb.sv)
|
||||
XRUN_TB := $(addprefix $(CVA6_HOME)/, corev_apu/tb/ariane_tb.sv)
|
||||
|
||||
XRUN_COMP_FLAGS ?= -64bit -disable_sem2009 -access +rwc \
|
||||
-sv -v93 -uvm -uvmhome $(XRUN_UVMHOME_ARG) \
|
||||
|
|
@ -535,11 +558,11 @@ xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchma
|
|||
# verilator-specific
|
||||
verilate_command := $(verilator) \
|
||||
$(filter-out %.vhd, $(ariane_pkg)) \
|
||||
$(filter-out src/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
|
||||
+define+$(defines) \
|
||||
src/util/sram.sv \
|
||||
tb/common/mock_uart.sv \
|
||||
+incdir+src/axi_node \
|
||||
$(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
|
||||
+define+$(defines) -DRVFI_TRACE=1 \
|
||||
common/local/util/sram.sv \
|
||||
corev_apu/tb/common/mock_uart.sv \
|
||||
+incdir+corev_apu/axi_node \
|
||||
$(if $(verilator_threads), --threads $(verilator_threads)) \
|
||||
--unroll-count 256 \
|
||||
-Werror-PINMISSING \
|
||||
|
|
@ -552,17 +575,18 @@ verilate_command := $(verilator)
|
|||
-Wno-UNOPTFLAT \
|
||||
-Wno-BLKANDNBLK \
|
||||
-Wno-style \
|
||||
$(if ($(PRELOAD)!=""), -DPRELOAD=1,) \
|
||||
$(if $(DROMAJO), -DDROMAJO=1,) \
|
||||
$(if $(PROFILE),--stats --stats-vars --profile-cfuncs,) \
|
||||
$(if $(DEBUG),--trace --trace-structs,) \
|
||||
-LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -L../tb/dromajo/src -ldromajo_cosim,) -lpthread" \
|
||||
-LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -L../corev_apu/tb/dromajo/src -ldromajo_cosim,) -lpthread" \
|
||||
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -DDROMAJO=1,) -DVL_DEBUG" \
|
||||
-Wall --cc --vpi \
|
||||
$(list_incdir) --top-module ariane_testharness \
|
||||
--threads-dpi none \
|
||||
--Mdir $(ver-library) -O3 \
|
||||
--exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc \
|
||||
tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc $(if $(DROMAJO), tb/dpi/dromajo_cosim_dpi.cc,)
|
||||
--exe corev_apu/tb/ariane_tb.cpp corev_apu/tb/dpi/SimDTM.cc corev_apu/tb/dpi/SimJTAG.cc \
|
||||
corev_apu/tb/dpi/remote_bitbang.cc corev_apu/tb/dpi/msim_helper.cc $(if $(DROMAJO), corev_apu/tb/dpi/dromajo_cosim_dpi.cc,)
|
||||
|
||||
dromajo:
|
||||
cd ./tb/dromajo/src && make
|
||||
|
|
@ -710,22 +734,22 @@ check-torture:
|
|||
grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log
|
||||
diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig
|
||||
|
||||
fpga_filter := $(addprefix $(root-dir), bootrom/bootrom.sv)
|
||||
fpga_filter += $(addprefix $(root-dir), include/instr_tracer_pkg.sv)
|
||||
fpga_filter := $(addprefix $(root-dir), corev_apu/bootrom/bootrom.sv)
|
||||
fpga_filter += $(addprefix $(root-dir), core/include/instr_tracer_pkg.sv)
|
||||
fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv)
|
||||
fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv)
|
||||
fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer_if.sv)
|
||||
fpga_filter += $(addprefix $(root-dir), src/util/instr_tracer.sv)
|
||||
fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer_if.sv)
|
||||
fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer.sv)
|
||||
|
||||
fpga: $(ariane_pkg) $(util) $(src) $(fpga_src) $(uart_src)
|
||||
@echo "[FPGA] Generate sources"
|
||||
@echo read_vhdl {$(uart_src)} > fpga/scripts/add_sources.tcl
|
||||
@echo read_verilog -sv {$(ariane_pkg)} >> fpga/scripts/add_sources.tcl
|
||||
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> fpga/scripts/add_sources.tcl
|
||||
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> fpga/scripts/add_sources.tcl
|
||||
@echo read_verilog -sv {$(fpga_src)} >> fpga/scripts/add_sources.tcl
|
||||
@echo read_vhdl {$(uart_src)} > corev_apu/fpga/scripts/add_sources.tcl
|
||||
@echo read_verilog -sv {$(ariane_pkg)} >> corev_apu/fpga/scripts/add_sources.tcl
|
||||
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(util))} >> corev_apu/fpga/scripts/add_sources.tcl
|
||||
@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} >> corev_apu/fpga/scripts/add_sources.tcl
|
||||
@echo read_verilog -sv {$(fpga_src)} >> corev_apu/fpga/scripts/add_sources.tcl
|
||||
@echo "[FPGA] Generate Bitstream"
|
||||
cd fpga && make BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
|
||||
cd corev_apu/fpga && make BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
|
||||
|
||||
.PHONY: fpga
|
||||
|
||||
|
|
|
|||
62
README.md
62
README.md
|
|
@ -8,6 +8,33 @@ It has configurable size, separate TLBs, a hardware PTW and branch-prediction (b
|
|||
|
||||
|
||||
|
||||
## New Directory Structure:
|
||||
The directory structure has been changed to cleanly separate the [CVA6 RISC-V CPU](#cva6-risc-v-cpu) core from the COREV-APU [FPGA Emulation](#corev-apu-fpga-emulation).
|
||||
Files, directories and submodules under `cva6` are for the core _only_ and should not have any dependencies on the APU.
|
||||
Files, directories and submodules under `corev_apu` are for the FPGA Emulation platform.
|
||||
The CVA6 core can be compiled stand-alone, and obviously the APU is dependent on the core.
|
||||
|
||||
#### ci
|
||||
Scriptware for CI (unchanged).
|
||||
|
||||
#### common
|
||||
Source code used by both the CVA6 Core and the COREV APU.
|
||||
Subdirectories from here are `local` for common files that are hosted in this repo and `submodules` that are hosted in other repos.
|
||||
|
||||
#### core
|
||||
Source code for the CVA6 Core only.
|
||||
There should be no sources in this directory used to build anything other than the CVA6 core.
|
||||
|
||||
#### corev_apu
|
||||
Source code for the CVA6 APU, exclusive of the CVA6 core.
|
||||
There should be no sources in this directory used to build the CVA6 core.
|
||||
|
||||
#### docs
|
||||
Documentation (unchanged).
|
||||
|
||||
#### scripts
|
||||
General scriptware (unchanged).
|
||||
|
||||
## Publication
|
||||
|
||||
If you use CVA6 in your academic work you can cite us:
|
||||
|
|
@ -59,15 +86,17 @@ Created by [gh-md-toc](https://github.com/ekalinin/github-markdown-toc)
|
|||
|
||||
## Getting Started
|
||||
|
||||
Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools). Make sure that your `RISCV` environment variable points to your RISC-V installation (see the RISC-V tools and related projects for further information).
|
||||
|
||||
Checkout the repository and initialize all submodules
|
||||
Go and get the [RISC-V tools](https://github.com/riscv/riscv-tools).
|
||||
Make sure that your `RISCV` environment variable points to your RISC-V installation (see the RISC-V tools and related projects for further information).
|
||||
<br><br>
|
||||
Checkout the repository and initialize all submodules:
|
||||
```
|
||||
$ git clone https://github.com/openhwgroup/cva6.git
|
||||
$ git clone -b cva6_reorg https://github.com/openhwgroup/cva6.git cva6_reorg
|
||||
$ cd cva6_reorg
|
||||
$ git submodule update --init --recursive
|
||||
```
|
||||
|
||||
Build the Verilator model of CVA6 by using the Makefile:
|
||||
Build the Verilator model of the COREV-APU by using the Makefile:
|
||||
```
|
||||
$ make verilate
|
||||
```
|
||||
|
|
@ -77,20 +106,33 @@ To build the verilator model with support for vcd files run
|
|||
$ make verilate DEBUG=1
|
||||
```
|
||||
|
||||
This will create a C++ model of the core including a SystemVerilog wrapper and link it against a C++ testbench (in the `tb` subfolder). The binary can be found in the `work-ver` and accepts a RISC-V ELF binary as an argument, e.g.:
|
||||
This will create a C++ model of the core including a SystemVerilog wrapper and link it against a C++ testbench (in the `tb` subfolder).
|
||||
The binary can be found in the `work-ver` and accepts a RISC-V ELF binary as an argument, e.g.:
|
||||
|
||||
```
|
||||
$ work-ver/Variane_testharness rv64um-v-divuw
|
||||
```
|
||||
|
||||
The Verilator testbench makes use of the `riscv-fesvr`. This means that you can use the `riscv-tests` repository as well as `riscv-pk` out-of-the-box. As a general rule of thumb the Verilator model will behave like Spike (exception for being orders of magnitudes slower).
|
||||
The Verilator testbench makes use of the `riscv-fesvr`.
|
||||
This means that you can use the `riscv-tests` repository as well as `riscv-pk` out-of-the-box.
|
||||
As a general rule of thumb the Verilator model will behave like Spike (exception for being orders of magnitudes slower).
|
||||
|
||||
Both, the Verilator model as well as the Questa simulation will produce trace logs. The Verilator trace is more basic but you can feed the log to `spike-dasm` to resolve instructions to mnemonics. Unfortunately value inspection is currently not possible for the Verilator trace file.
|
||||
Both the Verilator model as well as the Questa simulation will produce trace logs.
|
||||
The Verilator trace is more basic but you can feed the log to `spike-dasm` to resolve instructions to mnemonics.
|
||||
Unfortunately value inspection is currently not possible for the Verilator trace file.
|
||||
|
||||
```
|
||||
$ spike-dasm < trace_hart_00.dasm > logfile.txt
|
||||
```
|
||||
|
||||
To build, compile and run the CVA6 core-only in its example testbench using Verilator (known to work with V4.108):
|
||||
```
|
||||
$ cd core/example_tb
|
||||
$ make veri_run
|
||||
```
|
||||
`make help` will print all supported targets.
|
||||
|
||||
|
||||
### Running User-Space Applications
|
||||
|
||||
It is possible to run user-space binaries on CVA6 with `riscv-pk` ([link](https://github.com/riscv/riscv-pk)).
|
||||
|
|
@ -128,11 +170,11 @@ $ make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf b
|
|||
|
||||
> Be patient! RTL simulation is way slower than Spike. If you think that you ran into problems you can inspect the trace files.
|
||||
|
||||
## FPGA Emulation
|
||||
## COREV-APU FPGA Emulation
|
||||
|
||||
We currently only provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual). We provide pre-build bitstream and memory configuration files for the Genesys 2 [here](https://github.com/openhwgroup/cva6/releases).
|
||||
|
||||
Tested on Vivado 2018.2. The FPGA SoC currently contains the following peripherals:
|
||||
Tested on Vivado 2018.2. The FPGA currently contains the following peripherals:
|
||||
|
||||
- DDR3 memory controller
|
||||
- SPI controller to conncet to an SDCard
|
||||
|
|
|
|||
Binary file not shown.
158
core/Flist.cv32a6_imac_sv0
Normal file
158
core/Flist.cv32a6_imac_sv0
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
//////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright 2021 OpenHW Group
|
||||
//
|
||||
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Manifest for the CVA6 CORE RTL model.
|
||||
// - This is a CORE-ONLY manifest.
|
||||
// - Relevent synthesis and simulation scripts/Makefiles must set the shell
|
||||
// ENV variable CVA6_REPO_DIR.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
+define+WT_DCACHE
|
||||
|
||||
+incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/include/
|
||||
+incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/src/
|
||||
+incdir+${CVA6_REPO_DIR}/common/local/util/
|
||||
|
||||
${CVA6_REPO_DIR}/core/include/cv32a6_imac_sv0_config_pkg.sv
|
||||
// Broken (?) dependencies in packages:
|
||||
// - include/ariane_pkg.sv is dependent on src/riscv-dbg/src/dm_pkg.sv
|
||||
// (ariane should not depend on debug-module)
|
||||
// - The core RTL is dependent on tb/ariane_soc_pkg.sv
|
||||
// (RTL should not depend on TB code)
|
||||
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
|
||||
// TODO: should not be needed.
|
||||
${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
|
||||
// TODO: should not be needed.
|
||||
${CVA6_REPO_DIR}/corev_apu/tb/ariane_soc_pkg.sv
|
||||
// TODO: ariane_axi_pkg is dependent on this.
|
||||
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
|
||||
${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
|
||||
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
|
||||
|
||||
// Packages
|
||||
${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/include/axi_intf.sv
|
||||
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
|
||||
|
||||
// Common Cells
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/fifo_v3.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/lfsr_8bit.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/lzc.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/rr_arb_tree.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/shift_reg.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/unread.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/popcount.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/exp_backoff.sv
|
||||
|
||||
// Floating point unit
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_cast_multi.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_classifier.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_divsqrt_multi.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma_multi.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_noncomp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_block.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_fmt_slice.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_multifmt_slice.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_rounding.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_top.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
|
||||
|
||||
// Top-level source files (not necessarily instantiated at the top of the cva6).
|
||||
${CVA6_REPO_DIR}/core/ariane_wrapper.sv
|
||||
${CVA6_REPO_DIR}/core/ariane.sv
|
||||
${CVA6_REPO_DIR}/core/alu.sv
|
||||
// Note: depends on fpnew_pkg, above
|
||||
${CVA6_REPO_DIR}/core/fpu_wrap.sv
|
||||
${CVA6_REPO_DIR}/core/branch_unit.sv
|
||||
${CVA6_REPO_DIR}/core/compressed_decoder.sv
|
||||
${CVA6_REPO_DIR}/core/controller.sv
|
||||
${CVA6_REPO_DIR}/core/csr_buffer.sv
|
||||
${CVA6_REPO_DIR}/core/csr_regfile.sv
|
||||
${CVA6_REPO_DIR}/core/decoder.sv
|
||||
${CVA6_REPO_DIR}/core/ex_stage.sv
|
||||
${CVA6_REPO_DIR}/core/instr_realign.sv
|
||||
${CVA6_REPO_DIR}/core/id_stage.sv
|
||||
${CVA6_REPO_DIR}/core/issue_read_operands.sv
|
||||
${CVA6_REPO_DIR}/core/issue_stage.sv
|
||||
${CVA6_REPO_DIR}/core/load_unit.sv
|
||||
${CVA6_REPO_DIR}/core/load_store_unit.sv
|
||||
//${CVA6_REPO_DIR}/core/mmu.sv
|
||||
${CVA6_REPO_DIR}/core/mult.sv
|
||||
${CVA6_REPO_DIR}/core/multiplier.sv
|
||||
${CVA6_REPO_DIR}/core/serdiv.sv
|
||||
${CVA6_REPO_DIR}/core/perf_counters.sv
|
||||
//${CVA6_REPO_DIR}/core/ptw.sv
|
||||
${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
|
||||
${CVA6_REPO_DIR}/core/re_name.sv
|
||||
// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
|
||||
${CVA6_REPO_DIR}/core/scoreboard.sv
|
||||
${CVA6_REPO_DIR}/core/store_buffer.sv
|
||||
${CVA6_REPO_DIR}/core/amo_buffer.sv
|
||||
${CVA6_REPO_DIR}/core/store_unit.sv
|
||||
//${CVA6_REPO_DIR}/core/tlb.sv
|
||||
${CVA6_REPO_DIR}/core/commit_stage.sv
|
||||
${CVA6_REPO_DIR}/core/axi_shim.sv
|
||||
|
||||
// What is "frontend"?
|
||||
${CVA6_REPO_DIR}/core/frontend/btb.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/bht.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/ras.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/frontend.sv
|
||||
|
||||
// Cache subsystem
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
|
||||
|
||||
// Physical Memory Protection
|
||||
// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
|
||||
${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
|
||||
${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
|
||||
|
||||
// Tracer (behavioral code, not RTL)
|
||||
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
|
||||
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
|
||||
${CVA6_REPO_DIR}/common/local/util/sram.sv
|
||||
|
||||
// MMU Sv32
|
||||
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
|
||||
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
|
||||
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
|
||||
|
||||
// end of manifest
|
||||
158
core/Flist.cv64a6_imafdc_sv39
Normal file
158
core/Flist.cv64a6_imafdc_sv39
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
//////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright 2021 OpenHW Group
|
||||
//
|
||||
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Manifest for the CVA6 CORE RTL model.
|
||||
// - This is a CORE-ONLY manifest.
|
||||
// - Relevent synthesis and simulation scripts/Makefiles must set the shell
|
||||
// ENV variable CVA6_REPO_DIR.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
+define+WT_DCACHE
|
||||
|
||||
+incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/include/
|
||||
+incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/src/
|
||||
+incdir+${CVA6_REPO_DIR}/common/local/util/
|
||||
|
||||
${CVA6_REPO_DIR}/core/include/cv64a6_imacfd_sv39_config_pkg.sv
|
||||
// Broken (?) dependencies in packages:
|
||||
// - include/ariane_pkg.sv is dependent on src/riscv-dbg/src/dm_pkg.sv
|
||||
// (ariane should not depend on debug-module)
|
||||
// - The core RTL is dependent on tb/ariane_soc_pkg.sv
|
||||
// (RTL should not depend on TB code)
|
||||
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
|
||||
// TODO: should not be needed.
|
||||
${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
|
||||
// TODO: should not be needed.
|
||||
${CVA6_REPO_DIR}/corev_apu/tb/ariane_soc_pkg.sv
|
||||
// TODO: ariane_axi_pkg is dependent on this.
|
||||
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
|
||||
${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
|
||||
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
|
||||
|
||||
// Packages
|
||||
${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/include/axi_intf.sv
|
||||
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
|
||||
|
||||
// Common Cells
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/fifo_v3.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/lfsr_8bit.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/lzc.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/rr_arb_tree.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/shift_reg.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/unread.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/popcount.sv
|
||||
${CVA6_REPO_DIR}/common/submodules/common_cells/src/exp_backoff.sv
|
||||
|
||||
// Floating point unit
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_cast_multi.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_classifier.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_divsqrt_multi.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma_multi.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_noncomp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_block.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_fmt_slice.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_multifmt_slice.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_rounding.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpnew_top.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
|
||||
${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
|
||||
|
||||
// Top-level source files (not necessarily instantiated at the top of the cva6).
|
||||
${CVA6_REPO_DIR}/core/ariane_wrapper.sv
|
||||
${CVA6_REPO_DIR}/core/ariane.sv
|
||||
${CVA6_REPO_DIR}/core/alu.sv
|
||||
// Note: depends on fpnew_pkg, above
|
||||
${CVA6_REPO_DIR}/core/fpu_wrap.sv
|
||||
${CVA6_REPO_DIR}/core/branch_unit.sv
|
||||
${CVA6_REPO_DIR}/core/compressed_decoder.sv
|
||||
${CVA6_REPO_DIR}/core/controller.sv
|
||||
${CVA6_REPO_DIR}/core/csr_buffer.sv
|
||||
${CVA6_REPO_DIR}/core/csr_regfile.sv
|
||||
${CVA6_REPO_DIR}/core/decoder.sv
|
||||
${CVA6_REPO_DIR}/core/ex_stage.sv
|
||||
${CVA6_REPO_DIR}/core/instr_realign.sv
|
||||
${CVA6_REPO_DIR}/core/id_stage.sv
|
||||
${CVA6_REPO_DIR}/core/issue_read_operands.sv
|
||||
${CVA6_REPO_DIR}/core/issue_stage.sv
|
||||
${CVA6_REPO_DIR}/core/load_unit.sv
|
||||
${CVA6_REPO_DIR}/core/load_store_unit.sv
|
||||
${CVA6_REPO_DIR}/core/mmu.sv
|
||||
${CVA6_REPO_DIR}/core/mult.sv
|
||||
${CVA6_REPO_DIR}/core/multiplier.sv
|
||||
${CVA6_REPO_DIR}/core/serdiv.sv
|
||||
${CVA6_REPO_DIR}/core/perf_counters.sv
|
||||
${CVA6_REPO_DIR}/core/ptw.sv
|
||||
${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
|
||||
${CVA6_REPO_DIR}/core/re_name.sv
|
||||
// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
|
||||
${CVA6_REPO_DIR}/core/scoreboard.sv
|
||||
${CVA6_REPO_DIR}/core/store_buffer.sv
|
||||
${CVA6_REPO_DIR}/core/amo_buffer.sv
|
||||
${CVA6_REPO_DIR}/core/store_unit.sv
|
||||
${CVA6_REPO_DIR}/core/tlb.sv
|
||||
${CVA6_REPO_DIR}/core/commit_stage.sv
|
||||
${CVA6_REPO_DIR}/core/axi_shim.sv
|
||||
|
||||
// What is "frontend"?
|
||||
${CVA6_REPO_DIR}/core/frontend/btb.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/bht.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/ras.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/frontend.sv
|
||||
|
||||
// Cache subsystem
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
|
||||
|
||||
// Physical Memory Protection
|
||||
// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
|
||||
${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
|
||||
${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
|
||||
|
||||
// Tracer (behavioral code, not RTL)
|
||||
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
|
||||
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
|
||||
${CVA6_REPO_DIR}/common/local/util/sram.sv
|
||||
|
||||
// MMU Sv39
|
||||
${CVA6_REPO_DIR}/core/mmu_sv39/mmu.sv
|
||||
${CVA6_REPO_DIR}/core/mmu_sv39/ptw.sv
|
||||
${CVA6_REPO_DIR}/core/mmu_sv39/tlb.sv
|
||||
|
||||
// end of manifest
|
||||
|
|
@ -42,6 +42,11 @@ module ariane import ariane_pkg::*; #(
|
|||
// firesim trace port
|
||||
output traced_instr_pkg::trace_port_t trace_o,
|
||||
`endif
|
||||
`ifdef RVFI_TRACE
|
||||
// RISC-V formal interface port (`rvfi`):
|
||||
// Can be left open when formal tracing is not needed.
|
||||
output ariane_rvfi_pkg::rvfi_port_t rvfi_o,
|
||||
`endif
|
||||
`ifdef PITON_ARIANE
|
||||
// L15 (memory side)
|
||||
output wt_cache_pkg::l15_req_t l15_req_o,
|
||||
|
|
@ -894,4 +899,38 @@ module ariane import ariane_pkg::*; #(
|
|||
`endif // VERILATOR
|
||||
//pragma translate_on
|
||||
|
||||
`ifdef RVFI_TRACE
|
||||
always_comb
|
||||
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
|
||||
logic exception, mem_exception;
|
||||
exception = commit_instr_id_commit[i].valid && commit_instr_id_commit[i].ex.valid && ex_commit.valid;
|
||||
mem_exception = exception &&
|
||||
(commit_instr_id_commit[i].ex.cause == riscv::INSTR_ADDR_MISALIGNED ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::INSTR_ACCESS_FAULT ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::ILLEGAL_INSTR ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::LD_ADDR_MISALIGNED ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::LD_ACCESS_FAULT ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::ST_ADDR_MISALIGNED ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::ST_ACCESS_FAULT ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::INSTR_PAGE_FAULT ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::LOAD_PAGE_FAULT ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::STORE_PAGE_FAULT);
|
||||
// when rvfi_valid, the instruction is executed
|
||||
rvfi_o[i].valid = (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) ||
|
||||
(exception && (commit_instr_id_commit[i].ex.cause == riscv::ENV_CALL_MMODE ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::ENV_CALL_SMODE ||
|
||||
commit_instr_id_commit[i].ex.cause == riscv::ENV_CALL_UMODE));
|
||||
rvfi_o[i].insn = commit_instr_id_commit[i].ex.tval[31:0];
|
||||
// when trap, the instruction is not executed
|
||||
rvfi_o[i].trap = mem_exception;
|
||||
rvfi_o[i].mode = debug_mode ? 2'b10 : priv_lvl;
|
||||
rvfi_o[i].ixl = riscv::XLEN == 64 ? 2 : 1;
|
||||
rvfi_o[i].rs1_addr = commit_instr_id_commit[i].rs1;
|
||||
rvfi_o[i].rs2_addr = commit_instr_id_commit[i].rs2;
|
||||
rvfi_o[i].rd_addr = commit_instr_id_commit[i].rd;
|
||||
rvfi_o[i].rd_wdata = ariane_pkg::is_rd_fpr(commit_instr_id_commit[i].op) == 0 ? wdata_commit_id[i] : commit_instr_id_commit[i].result;
|
||||
rvfi_o[i].pc_rdata = commit_instr_id_commit[i].pc;
|
||||
end
|
||||
`endif
|
||||
|
||||
endmodule // ariane
|
||||
237
core/ariane_wrapper.sv
Normal file
237
core/ariane_wrapper.sv
Normal file
|
|
@ -0,0 +1,237 @@
|
|||
// Copyright 2021 Thales DIS design services SAS
|
||||
//
|
||||
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
|
||||
// You may obtain a copy of the License at https://solderpad.org/licenses/
|
||||
//
|
||||
// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
|
||||
|
||||
module ariane_wrapper import ariane_pkg::*; #(
|
||||
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
// Core ID, Cluster ID and boot address are considered more or less static
|
||||
input logic [63:0] boot_addr_i, // reset boot address
|
||||
input logic [63:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR)
|
||||
|
||||
// Interrupt inputs
|
||||
input logic [1:0] irq_i, // level sensitive IR lines, mip & sip (async)
|
||||
input logic ipi_i, // inter-processor interrupts (async)
|
||||
// Timer facilities
|
||||
input logic time_irq_i, // timer interrupt in (async)
|
||||
input logic debug_req_i, // debug request (async)
|
||||
`ifdef FIRESIM_TRACE
|
||||
// firesim trace port
|
||||
output traced_instr_pkg::trace_port_t trace_o,
|
||||
`endif
|
||||
// RISC-V formal interface port (`rvfi`):
|
||||
// Can be left open when formal tracing is not needed.
|
||||
output logic rvfi_valid_1,
|
||||
output logic[63:0] rvfi_order_1,
|
||||
output logic[31:0] rvfi_insn_1,
|
||||
output logic rvfi_trap_1,
|
||||
output logic rvfi_halt_1,
|
||||
output logic rvfi_intr_1,
|
||||
output logic[2:0] rvfi_mode_1,
|
||||
output logic[2:0] rvfi_ixl_1,
|
||||
output logic[4:0] rvfi_rs1_addr_1,
|
||||
output logic[4:0] rvfi_rs2_addr_1,
|
||||
output logic[riscv::XLEN-1:0] rvfi_rs1_rdata_1,
|
||||
output logic[riscv::XLEN-1:0] rvfi_rs2_rdata_1,
|
||||
output logic[4:0] rvfi_rd_addr_1,
|
||||
output logic[riscv::XLEN-1:0] rvfi_rd_wdata_1,
|
||||
output logic[riscv::XLEN-1:0] rvfi_pc_rdata_1,
|
||||
output logic[riscv::XLEN-1:0] rvfi_pc_wdata_1,
|
||||
output logic[riscv::XLEN-1:0] rvfi_mem_addr_1,
|
||||
output logic[(riscv::XLEN)/8-1:0] rvfi_mem_rmask_1,
|
||||
output logic[(riscv::XLEN)/8-1:0] rvfi_mem_wmask_1,
|
||||
output logic[riscv::XLEN-1:0] rvfi_mem_rdata_1,
|
||||
output logic[riscv::XLEN-1:0] rvfi_mem_wdata_1,
|
||||
output logic rvfi_valid_0,
|
||||
output logic[63:0] rvfi_order_0,
|
||||
output logic[31:0] rvfi_insn_0,
|
||||
output logic rvfi_trap_0,
|
||||
output logic rvfi_halt_0,
|
||||
output logic rvfi_intr_0,
|
||||
output logic[2:0] rvfi_mode_0,
|
||||
output logic[2:0] rvfi_ixl_0,
|
||||
output logic[4:0] rvfi_rs1_addr_0,
|
||||
output logic[4:0] rvfi_rs2_addr_0,
|
||||
output logic[riscv::XLEN-1:0] rvfi_rs1_rdata_0,
|
||||
output logic[riscv::XLEN-1:0] rvfi_rs2_rdata_0,
|
||||
output logic[4:0] rvfi_rd_addr_0,
|
||||
output logic[riscv::XLEN-1:0] rvfi_rd_wdata_0,
|
||||
output logic[riscv::XLEN-1:0] rvfi_pc_rdata_0,
|
||||
output logic[riscv::XLEN-1:0] rvfi_pc_wdata_0,
|
||||
output logic[riscv::XLEN-1:0] rvfi_mem_addr_0,
|
||||
output logic[(riscv::XLEN)/8-1:0] rvfi_mem_rmask_0,
|
||||
output logic[(riscv::XLEN)/8-1:0] rvfi_mem_wmask_0,
|
||||
output logic[riscv::XLEN-1:0] rvfi_mem_rdata_0,
|
||||
output logic[riscv::XLEN-1:0] rvfi_mem_wdata_0,
|
||||
`ifdef PITON_ARIANE
|
||||
// L15 (memory side)
|
||||
output wt_cache_pkg::l15_req_t l15_req_o,
|
||||
input wt_cache_pkg::l15_rtrn_t l15_rtrn_i
|
||||
`else
|
||||
// memory side, AXI Master
|
||||
output ariane_axi::id_t aw_id_o,
|
||||
output ariane_axi::addr_t aw_addr_o,
|
||||
output axi_pkg::len_t aw_len_o,
|
||||
output axi_pkg::size_t aw_size_o,
|
||||
output axi_pkg::burst_t aw_burst_o,
|
||||
output logic aw_lock_o,
|
||||
output axi_pkg::cache_t aw_cache_o,
|
||||
output axi_pkg::prot_t aw_prot_o,
|
||||
output axi_pkg::qos_t aw_qos_o,
|
||||
output axi_pkg::region_t aw_region_o,
|
||||
output axi_pkg::atop_t aw_atop_o,
|
||||
output ariane_axi::user_t aw_user_o,
|
||||
output logic aw_valid_o,
|
||||
output ariane_axi::data_t w_data_o,
|
||||
output ariane_axi::strb_t w_strb_o,
|
||||
output logic w_last_o,
|
||||
output ariane_axi::user_t w_user_o,
|
||||
output logic w_valid_o,
|
||||
output logic b_ready_o,
|
||||
output ariane_axi::id_t ar_id_o,
|
||||
output ariane_axi::addr_t ar_addr_o,
|
||||
output axi_pkg::len_t ar_len_o,
|
||||
output axi_pkg::size_t ar_size_o,
|
||||
output axi_pkg::burst_t ar_burst_o,
|
||||
output logic ar_lock_o,
|
||||
output axi_pkg::cache_t ar_cache_o,
|
||||
output axi_pkg::prot_t ar_prot_o,
|
||||
output axi_pkg::qos_t ar_qos_o,
|
||||
output axi_pkg::region_t ar_region_o,
|
||||
output ariane_axi::user_t ar_user_o,
|
||||
output logic ar_valid_o,
|
||||
output logic r_ready_o,
|
||||
input logic aw_ready_i,
|
||||
input logic ar_ready_i,
|
||||
input logic w_ready_i,
|
||||
input logic b_valid_i,
|
||||
input ariane_axi::id_t b_id_i,
|
||||
input axi_pkg::resp_t b_resp_i,
|
||||
input ariane_axi::user_t b_user_i,
|
||||
input logic r_valid_i,
|
||||
input ariane_axi::id_t r_id_i,
|
||||
input ariane_axi::data_t r_data_i,
|
||||
input axi_pkg::resp_t r_resp_i,
|
||||
input logic r_last_i,
|
||||
input ariane_axi::user_t r_user_i
|
||||
`endif
|
||||
);
|
||||
|
||||
ariane_axi::req_t axi_ariane_req;
|
||||
ariane_axi::resp_t axi_ariane_resp;
|
||||
ariane_rvfi_pkg::rvfi_port_t rvfi;
|
||||
|
||||
assign aw_id_o = axi_ariane_req.aw.id;
|
||||
assign aw_addr_o = axi_ariane_req.aw.addr;
|
||||
assign aw_len_o = axi_ariane_req.aw.len;
|
||||
assign aw_size_o = axi_ariane_req.aw.size;
|
||||
assign aw_burst_o = axi_ariane_req.aw.burst;
|
||||
assign aw_lock_o = axi_ariane_req.aw.lock;
|
||||
assign aw_cache_o = axi_ariane_req.aw.cache;
|
||||
assign aw_prot_o = axi_ariane_req.aw.prot;
|
||||
assign aw_qos_o = axi_ariane_req.aw.qos;
|
||||
assign aw_region_o = axi_ariane_req.aw.region;
|
||||
assign aw_atop_o = axi_ariane_req.aw.atop;
|
||||
assign aw_user_o = axi_ariane_req.aw.user;
|
||||
assign aw_valid_o = axi_ariane_req.aw_valid;
|
||||
assign w_data_o = axi_ariane_req.w.data;
|
||||
assign w_strb_o = axi_ariane_req.w.strb;
|
||||
assign w_last_o = axi_ariane_req.w.last;
|
||||
assign w_user_o = axi_ariane_req.w.user;
|
||||
assign w_valid_o = axi_ariane_req.w_valid;
|
||||
assign b_ready_o = axi_ariane_req.b_ready;
|
||||
assign ar_id_o = axi_ariane_req.ar.id;
|
||||
assign ar_addr_o = axi_ariane_req.ar.addr;
|
||||
assign ar_len_o = axi_ariane_req.ar.len;
|
||||
assign ar_size_o = axi_ariane_req.ar.size;
|
||||
assign ar_burst_o = axi_ariane_req.ar.burst;
|
||||
assign ar_lock_o = axi_ariane_req.ar.lock;
|
||||
assign ar_cache_o = axi_ariane_req.ar.cache;
|
||||
assign ar_prot_o = axi_ariane_req.ar.prot;
|
||||
assign ar_qos_o = axi_ariane_req.ar.qos;
|
||||
assign ar_region_o = axi_ariane_req.ar.region;
|
||||
assign ar_user_o = axi_ariane_req.ar.user;
|
||||
assign ar_valid_o = axi_ariane_req.ar_valid;
|
||||
assign r_ready_o = axi_ariane_req.r_ready;
|
||||
|
||||
assign axi_ariane_resp.aw_ready = aw_ready_i;
|
||||
assign axi_ariane_resp.ar_ready = ar_ready_i;
|
||||
assign axi_ariane_resp.w_ready = w_ready_i;
|
||||
assign axi_ariane_resp.b_valid = b_valid_i;
|
||||
assign axi_ariane_resp.b.id = b_id_i;
|
||||
assign axi_ariane_resp.b.resp = b_resp_i;
|
||||
assign axi_ariane_resp.b.user = b_user_i;
|
||||
assign axi_ariane_resp.r_valid = r_valid_i;
|
||||
assign axi_ariane_resp.r.id = r_id_i;
|
||||
assign axi_ariane_resp.r.data = r_data_i;
|
||||
assign axi_ariane_resp.r.resp = r_resp_i;
|
||||
assign axi_ariane_resp.r.last = r_last_i;
|
||||
assign axi_ariane_resp.r.user = r_user_i;
|
||||
|
||||
assign rvfi_valid_1 = rvfi[1].valid;
|
||||
assign rvfi_order_1 = rvfi[1].order;
|
||||
assign rvfi_insn_1 = rvfi[1].insn;
|
||||
assign rvfi_trap_1 = rvfi[1].trap;
|
||||
assign rvfi_halt_1 = rvfi[1].halt;
|
||||
assign rvfi_intr_1 = rvfi[1].intr;
|
||||
assign rvfi_mode_1 = rvfi[1].mode;
|
||||
assign rvfi_ixl_1 = rvfi[1].ixl;
|
||||
assign rvfi_rs1_addr_1 = rvfi[1].rs1_addr;
|
||||
assign rvfi_rs2_addr_1 = rvfi[1].rs2_addr;
|
||||
assign rvfi_rs1_rdata_1 = rvfi[1].rs1_rdata;
|
||||
assign rvfi_rs2_rdata_1 = rvfi[1].rs2_rdata;
|
||||
assign rvfi_rd_addr_1 = rvfi[1].rd_addr;
|
||||
assign rvfi_rd_wdata_1 = rvfi[1].rd_wdata;
|
||||
assign rvfi_pc_rdata_1 = rvfi[1].pc_rdata;
|
||||
assign rvfi_pc_wdata_1 = rvfi[1].pc_wdata;
|
||||
assign rvfi_mem_addr_1 = rvfi[1].mem_addr;
|
||||
assign rvfi_mem_rmask_1 = rvfi[1].mem_rmask;
|
||||
assign rvfi_mem_wmask_1 = rvfi[1].mem_wmask;
|
||||
assign rvfi_mem_rdata_1 = rvfi[1].mem_rdata;
|
||||
assign rvfi_mem_wdata_1 = rvfi[1].mem_wdata;
|
||||
assign rvfi_valid_0 = rvfi[0].valid;
|
||||
assign rvfi_order_0 = rvfi[0].order;
|
||||
assign rvfi_insn_0 = rvfi[0].insn;
|
||||
assign rvfi_trap_0 = rvfi[0].trap;
|
||||
assign rvfi_halt_0 = rvfi[0].halt;
|
||||
assign rvfi_intr_0 = rvfi[0].intr;
|
||||
assign rvfi_mode_0 = rvfi[0].mode;
|
||||
assign rvfi_ixl_0 = rvfi[0].ixl;
|
||||
assign rvfi_rs1_addr_0 = rvfi[0].rs1_addr;
|
||||
assign rvfi_rs2_addr_0 = rvfi[0].rs2_addr;
|
||||
assign rvfi_rs1_rdata_0 = rvfi[0].rs1_rdata;
|
||||
assign rvfi_rs2_rdata_0 = rvfi[0].rs2_rdata;
|
||||
assign rvfi_rd_addr_0 = rvfi[0].rd_addr;
|
||||
assign rvfi_rd_wdata_0 = rvfi[0].rd_wdata;
|
||||
assign rvfi_pc_rdata_0 = rvfi[0].pc_rdata;
|
||||
assign rvfi_pc_wdata_0 = rvfi[0].pc_wdata;
|
||||
assign rvfi_mem_addr_0 = rvfi[0].mem_addr;
|
||||
assign rvfi_mem_rmask_0 = rvfi[0].mem_rmask;
|
||||
assign rvfi_mem_wmask_0 = rvfi[0].mem_wmask;
|
||||
assign rvfi_mem_rdata_0 = rvfi[0].mem_rdata;
|
||||
assign rvfi_mem_wdata_0 = rvfi[0].mem_wdata;
|
||||
|
||||
ariane #(
|
||||
.ArianeCfg ( ariane_soc::ArianeSocCfg )
|
||||
) i_ariane (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( rst_ni ),
|
||||
.boot_addr_i ( boot_addr_i ),
|
||||
.hart_id_i ( hart_id_i ),
|
||||
.irq_i ( irq_i ),
|
||||
.ipi_i ( ipi_i ),
|
||||
.time_irq_i ( time_irq_i ),
|
||||
.rvfi_o ( rvfi ),
|
||||
.debug_req_i ( debug_req_i ),
|
||||
.axi_req_o ( axi_ariane_req ),
|
||||
.axi_resp_i ( axi_ariane_resp )
|
||||
);
|
||||
|
||||
endmodule // ariane_wrapper
|
||||
BIN
core/example_tb/verilator_results/Vcva6_core_only_tb
Executable file
BIN
core/example_tb/verilator_results/Vcva6_core_only_tb
Executable file
Binary file not shown.
BIN
core/example_tb/verilator_work/Vcva6_core_only_tb
Executable file
BIN
core/example_tb/verilator_work/Vcva6_core_only_tb
Executable file
Binary file not shown.
7664
core/example_tb/verilator_work/Vcva6_core_only_tb.cpp
Normal file
7664
core/example_tb/verilator_work/Vcva6_core_only_tb.cpp
Normal file
File diff suppressed because it is too large
Load diff
6
core/example_tb/verilator_work/Vcva6_core_only_tb.d
Normal file
6
core/example_tb/verilator_work/Vcva6_core_only_tb.d
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
Vcva6_core_only_tb.o: Vcva6_core_only_tb.cpp Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
3227
core/example_tb/verilator_work/Vcva6_core_only_tb.h
Normal file
3227
core/example_tb/verilator_work/Vcva6_core_only_tb.h
Normal file
File diff suppressed because it is too large
Load diff
66
core/example_tb/verilator_work/Vcva6_core_only_tb.mk
Normal file
66
core/example_tb/verilator_work/Vcva6_core_only_tb.mk
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
# Verilated -*- Makefile -*-
|
||||
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
|
||||
#
|
||||
# Execute this makefile from the object directory:
|
||||
# make -f Vcva6_core_only_tb.mk
|
||||
|
||||
default: Vcva6_core_only_tb
|
||||
|
||||
### Constants...
|
||||
# Perl executable (from $PERL)
|
||||
PERL = perl
|
||||
# Path to Verilator kit (from $VERILATOR_ROOT)
|
||||
VERILATOR_ROOT = /usr/local/share/verilator
|
||||
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
|
||||
SYSTEMC_INCLUDE ?=
|
||||
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
|
||||
SYSTEMC_LIBDIR ?=
|
||||
|
||||
### Switches...
|
||||
# SystemC output mode? 0/1 (from --sc)
|
||||
VM_SC = 0
|
||||
# Legacy or SystemC output mode? 0/1 (from --sc)
|
||||
VM_SP_OR_SC = $(VM_SC)
|
||||
# Deprecated
|
||||
VM_PCLI = 1
|
||||
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
|
||||
VM_SC_TARGET_ARCH = linux
|
||||
|
||||
### Vars...
|
||||
# Design prefix (from --prefix)
|
||||
VM_PREFIX = Vcva6_core_only_tb
|
||||
# Module prefix (from --prefix)
|
||||
VM_MODPREFIX = Vcva6_core_only_tb
|
||||
# User CFLAGS (from -CFLAGS on Verilator command line)
|
||||
VM_USER_CFLAGS = \
|
||||
|
||||
# User LDLIBS (from -LDFLAGS on Verilator command line)
|
||||
VM_USER_LDLIBS = \
|
||||
|
||||
# User .cpp files (from .cpp's on Verilator command line)
|
||||
VM_USER_CLASSES = \
|
||||
cva6_tb_verilator \
|
||||
|
||||
# User .cpp directories (from .cpp's on Verilator command line)
|
||||
VM_USER_DIR = \
|
||||
/home/mike/GitHubRepos/openhwgroup/cva6/cva6_reorg/core/example_tb/ \
|
||||
|
||||
|
||||
### Default rules...
|
||||
# Include list of all generated classes
|
||||
include Vcva6_core_only_tb_classes.mk
|
||||
# Include global rules
|
||||
include $(VERILATOR_ROOT)/include/verilated.mk
|
||||
|
||||
### Executable rules... (from --exe)
|
||||
VPATH += $(VM_USER_DIR)
|
||||
|
||||
cva6_tb_verilator.o: /home/mike/GitHubRepos/openhwgroup/cva6/cva6_reorg/core/example_tb//cva6_tb_verilator.cpp
|
||||
$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
|
||||
|
||||
### Link rules... (from --exe)
|
||||
Vcva6_core_only_tb: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS)
|
||||
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@
|
||||
|
||||
|
||||
# Verilated -*- Makefile -*-
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See Vcva6_core_only_tb.h for the primary calling header
|
||||
|
||||
#include "Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h"
|
||||
#include "Vcva6_core_only_tb__Syms.h"
|
||||
|
||||
//==========
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.o: \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.cpp \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb.h \
|
||||
Vcva6_core_only_tb___024unit.h
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design internal header
|
||||
// See Vcva6_core_only_tb.h for the primary calling header
|
||||
|
||||
#ifndef _VCVA6_CORE_ONLY_TB_AXI_BUS__A40_AB40_AC5_AD1_H_
|
||||
#define _VCVA6_CORE_ONLY_TB_AXI_BUS__A40_AB40_AC5_AD1_H_ // guard
|
||||
|
||||
#include "verilated_heavy.h"
|
||||
|
||||
//==========
|
||||
|
||||
class Vcva6_core_only_tb__Syms;
|
||||
|
||||
//----------
|
||||
|
||||
VL_MODULE(Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1) {
|
||||
public:
|
||||
|
||||
// LOCAL SIGNALS
|
||||
CData/*0:0*/ aw_ready;
|
||||
CData/*0:0*/ w_ready;
|
||||
CData/*4:0*/ b_id;
|
||||
CData/*0:0*/ b_valid;
|
||||
CData/*0:0*/ ar_ready;
|
||||
CData/*4:0*/ r_id;
|
||||
CData/*0:0*/ r_last;
|
||||
CData/*0:0*/ r_valid;
|
||||
QData/*63:0*/ r_data;
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
private:
|
||||
Vcva6_core_only_tb__Syms* __VlSymsp; // Symbol table
|
||||
public:
|
||||
|
||||
// CONSTRUCTORS
|
||||
private:
|
||||
VL_UNCOPYABLE(Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1); ///< Copying not allowed
|
||||
public:
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1(const char* name = "TOP");
|
||||
~Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1();
|
||||
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(Vcva6_core_only_tb__Syms* symsp, bool first);
|
||||
private:
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
|
||||
|
||||
//----------
|
||||
|
||||
|
||||
#endif // guard
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See Vcva6_core_only_tb.h for the primary calling header
|
||||
|
||||
#include "Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h"
|
||||
#include "Vcva6_core_only_tb__Syms.h"
|
||||
|
||||
//==========
|
||||
|
||||
VL_CTOR_IMP(Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1) {
|
||||
// Reset internal values
|
||||
// Reset structure values
|
||||
_ctor_var_reset();
|
||||
}
|
||||
|
||||
void Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1::__Vconfigure(Vcva6_core_only_tb__Syms* vlSymsp, bool first) {
|
||||
if (false && first) {} // Prevent unused
|
||||
this->__VlSymsp = vlSymsp;
|
||||
if (false && this->__VlSymsp) {} // Prevent unused
|
||||
}
|
||||
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1::~Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1() {
|
||||
}
|
||||
|
||||
void Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1::_ctor_var_reset() {
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1::_ctor_var_reset\n"); );
|
||||
// Body
|
||||
aw_ready = VL_RAND_RESET_I(1);
|
||||
w_ready = VL_RAND_RESET_I(1);
|
||||
b_id = VL_RAND_RESET_I(5);
|
||||
b_valid = VL_RAND_RESET_I(1);
|
||||
ar_ready = VL_RAND_RESET_I(1);
|
||||
r_id = VL_RAND_RESET_I(5);
|
||||
r_data = VL_RAND_RESET_Q(64);
|
||||
r_last = VL_RAND_RESET_I(1);
|
||||
r_valid = VL_RAND_RESET_I(1);
|
||||
}
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1__Slow.o: \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1__Slow.cpp \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb.h \
|
||||
Vcva6_core_only_tb___024unit.h
|
||||
21631
core/example_tb/verilator_work/Vcva6_core_only_tb__1.cpp
Normal file
21631
core/example_tb/verilator_work/Vcva6_core_only_tb__1.cpp
Normal file
File diff suppressed because it is too large
Load diff
6
core/example_tb/verilator_work/Vcva6_core_only_tb__1.d
Normal file
6
core/example_tb/verilator_work/Vcva6_core_only_tb__1.d
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
Vcva6_core_only_tb__1.o: Vcva6_core_only_tb__1.cpp Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
12483
core/example_tb/verilator_work/Vcva6_core_only_tb__10.cpp
Normal file
12483
core/example_tb/verilator_work/Vcva6_core_only_tb__10.cpp
Normal file
File diff suppressed because it is too large
Load diff
6
core/example_tb/verilator_work/Vcva6_core_only_tb__10.d
Normal file
6
core/example_tb/verilator_work/Vcva6_core_only_tb__10.d
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
Vcva6_core_only_tb__10.o: Vcva6_core_only_tb__10.cpp Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
11670
core/example_tb/verilator_work/Vcva6_core_only_tb__10__Slow.cpp
Normal file
11670
core/example_tb/verilator_work/Vcva6_core_only_tb__10__Slow.cpp
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,7 @@
|
|||
Vcva6_core_only_tb__10__Slow.o: Vcva6_core_only_tb__10__Slow.cpp \
|
||||
Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
9605
core/example_tb/verilator_work/Vcva6_core_only_tb__11.cpp
Normal file
9605
core/example_tb/verilator_work/Vcva6_core_only_tb__11.cpp
Normal file
File diff suppressed because it is too large
Load diff
6
core/example_tb/verilator_work/Vcva6_core_only_tb__11.d
Normal file
6
core/example_tb/verilator_work/Vcva6_core_only_tb__11.d
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
Vcva6_core_only_tb__11.o: Vcva6_core_only_tb__11.cpp Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
9538
core/example_tb/verilator_work/Vcva6_core_only_tb__11__Slow.cpp
Normal file
9538
core/example_tb/verilator_work/Vcva6_core_only_tb__11__Slow.cpp
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,7 @@
|
|||
Vcva6_core_only_tb__11__Slow.o: Vcva6_core_only_tb__11__Slow.cpp \
|
||||
Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
2708
core/example_tb/verilator_work/Vcva6_core_only_tb__12.cpp
Normal file
2708
core/example_tb/verilator_work/Vcva6_core_only_tb__12.cpp
Normal file
File diff suppressed because one or more lines are too long
6
core/example_tb/verilator_work/Vcva6_core_only_tb__12.d
Normal file
6
core/example_tb/verilator_work/Vcva6_core_only_tb__12.d
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
Vcva6_core_only_tb__12.o: Vcva6_core_only_tb__12.cpp Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
3240
core/example_tb/verilator_work/Vcva6_core_only_tb__12__Slow.cpp
Normal file
3240
core/example_tb/verilator_work/Vcva6_core_only_tb__12__Slow.cpp
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,7 @@
|
|||
Vcva6_core_only_tb__12__Slow.o: Vcva6_core_only_tb__12__Slow.cpp \
|
||||
Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
17141
core/example_tb/verilator_work/Vcva6_core_only_tb__1__Slow.cpp
Normal file
17141
core/example_tb/verilator_work/Vcva6_core_only_tb__1__Slow.cpp
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,7 @@
|
|||
Vcva6_core_only_tb__1__Slow.o: Vcva6_core_only_tb__1__Slow.cpp \
|
||||
Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
16855
core/example_tb/verilator_work/Vcva6_core_only_tb__2.cpp
Normal file
16855
core/example_tb/verilator_work/Vcva6_core_only_tb__2.cpp
Normal file
File diff suppressed because it is too large
Load diff
6
core/example_tb/verilator_work/Vcva6_core_only_tb__2.d
Normal file
6
core/example_tb/verilator_work/Vcva6_core_only_tb__2.d
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
Vcva6_core_only_tb__2.o: Vcva6_core_only_tb__2.cpp Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
13697
core/example_tb/verilator_work/Vcva6_core_only_tb__2__Slow.cpp
Normal file
13697
core/example_tb/verilator_work/Vcva6_core_only_tb__2__Slow.cpp
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,7 @@
|
|||
Vcva6_core_only_tb__2__Slow.o: Vcva6_core_only_tb__2__Slow.cpp \
|
||||
Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
10616
core/example_tb/verilator_work/Vcva6_core_only_tb__3.cpp
Normal file
10616
core/example_tb/verilator_work/Vcva6_core_only_tb__3.cpp
Normal file
File diff suppressed because it is too large
Load diff
6
core/example_tb/verilator_work/Vcva6_core_only_tb__3.d
Normal file
6
core/example_tb/verilator_work/Vcva6_core_only_tb__3.d
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
Vcva6_core_only_tb__3.o: Vcva6_core_only_tb__3.cpp Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
9211
core/example_tb/verilator_work/Vcva6_core_only_tb__3__Slow.cpp
Normal file
9211
core/example_tb/verilator_work/Vcva6_core_only_tb__3__Slow.cpp
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,7 @@
|
|||
Vcva6_core_only_tb__3__Slow.o: Vcva6_core_only_tb__3__Slow.cpp \
|
||||
Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
9746
core/example_tb/verilator_work/Vcva6_core_only_tb__4.cpp
Normal file
9746
core/example_tb/verilator_work/Vcva6_core_only_tb__4.cpp
Normal file
File diff suppressed because it is too large
Load diff
6
core/example_tb/verilator_work/Vcva6_core_only_tb__4.d
Normal file
6
core/example_tb/verilator_work/Vcva6_core_only_tb__4.d
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
Vcva6_core_only_tb__4.o: Vcva6_core_only_tb__4.cpp Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
11764
core/example_tb/verilator_work/Vcva6_core_only_tb__4__Slow.cpp
Normal file
11764
core/example_tb/verilator_work/Vcva6_core_only_tb__4__Slow.cpp
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,7 @@
|
|||
Vcva6_core_only_tb__4__Slow.o: Vcva6_core_only_tb__4__Slow.cpp \
|
||||
Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
13209
core/example_tb/verilator_work/Vcva6_core_only_tb__5.cpp
Normal file
13209
core/example_tb/verilator_work/Vcva6_core_only_tb__5.cpp
Normal file
File diff suppressed because it is too large
Load diff
6
core/example_tb/verilator_work/Vcva6_core_only_tb__5.d
Normal file
6
core/example_tb/verilator_work/Vcva6_core_only_tb__5.d
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
Vcva6_core_only_tb__5.o: Vcva6_core_only_tb__5.cpp Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
10865
core/example_tb/verilator_work/Vcva6_core_only_tb__5__Slow.cpp
Normal file
10865
core/example_tb/verilator_work/Vcva6_core_only_tb__5__Slow.cpp
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,7 @@
|
|||
Vcva6_core_only_tb__5__Slow.o: Vcva6_core_only_tb__5__Slow.cpp \
|
||||
Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
13370
core/example_tb/verilator_work/Vcva6_core_only_tb__6.cpp
Normal file
13370
core/example_tb/verilator_work/Vcva6_core_only_tb__6.cpp
Normal file
File diff suppressed because it is too large
Load diff
6
core/example_tb/verilator_work/Vcva6_core_only_tb__6.d
Normal file
6
core/example_tb/verilator_work/Vcva6_core_only_tb__6.d
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
Vcva6_core_only_tb__6.o: Vcva6_core_only_tb__6.cpp Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
8647
core/example_tb/verilator_work/Vcva6_core_only_tb__6__Slow.cpp
Normal file
8647
core/example_tb/verilator_work/Vcva6_core_only_tb__6__Slow.cpp
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,7 @@
|
|||
Vcva6_core_only_tb__6__Slow.o: Vcva6_core_only_tb__6__Slow.cpp \
|
||||
Vcva6_core_only_tb.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
Vcva6_core_only_tb__Syms.h Vcva6_core_only_tb___024unit.h \
|
||||
Vcva6_core_only_tb_AXI_BUS__A40_AB40_AC5_AD1.h
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue