Fix issue #49

riscv-torture

@@ -1 +1 @@
-Subproject commit 4757b31e4572af920b0a397d0ef97e45dc35e799
+Subproject commit c061486b69ac83c0c24b2b451d2d8e1d83d1ca77

src/lsu.sv

@@ -400,12 +400,12 @@ module lsu #(
             case (operator_i)
                 // double word
                 LD, SD: begin
-                    if (vaddr_i[2:0] != 3'b000)
+                    if (lsu_ctrl.vaddr[2:0] != 3'b000)
                         data_misaligned = 1'b1;
                 end
                 // word
                 LW, LWU, SW: begin
-                    if (vaddr_i[1:0] != 2'b00)
+                    if (lsu_ctrl.vaddr[1:0] != 2'b00)
                         data_misaligned = 1'b1;
                 end
 
@@ -436,6 +436,25 @@ module lsu #(
                 };
             end
         end
+
+        // check that all bits in the address >= 39 are equal
+        if (!((&lsu_ctrl.vaddr[63:39]) == 1'b1 || (|lsu_ctrl.vaddr[63:39]) == 1'b0)) begin
+
+            if (lsu_ctrl.fu == LOAD) begin
+                misaligned_exception = {
+                    LOAD_PAGE_FAULT,
+                    lsu_ctrl.vaddr,
+                    1'b1
+                };
+
+            end else if (lsu_ctrl.fu == STORE) begin
+                misaligned_exception = {
+                    STORE_PAGE_FAULT,
+                    lsu_ctrl.vaddr,
+                    1'b1
+                };
+            end
+        end
     end
 
     // ------------------

src/mmu.sv

@@ -216,6 +216,9 @@ module mmu #(
         iaccess_err   = fetch_req_i && (((priv_lvl_i == PRIV_LVL_U) && ~itlb_content.u)
                                      || ((priv_lvl_i == PRIV_LVL_S) && itlb_content.u));
 
+        if (!((&fetch_vaddr_i[63:39]) == 1'b1 || (|fetch_vaddr_i[63:39]) == 1'b0)) begin
+            fetch_ex_n = {INSTR_PAGE_FAULT, fetch_vaddr_i, 1'b1};
+        end
         // MMU enabled: address from TLB, request delayed until hit. Error when TLB
         // hit and no access right or TLB hit and translated address not valid (e.g.
         // AXI decode error), or when PTW performs walk due to ITLB miss and raises