mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-22 21:27:10 -04:00
Fix CSR coverage model & HVP (#1751)
This commit is contained in:
Jalali
GitHub
parent
59177e37d3
commit
4279cc0f6e
4 changed files with 38 additions and 12 deletions
4
verif/env/uvme/cov/uvme_cva6_config_covg.sv
vendored
4
verif/env/uvme/cov/uvme_cva6_config_covg.sv
vendored
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@ -121,7 +121,7 @@ covergroup cg_cva6_config(string name) with function sample();
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bins NrStorePipeRegs ={0};
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}
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cp_NrLoadBufEntries : coverpoint cva6_config_pkg::CVA6ConfigNrLoadBufEntries {
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bins NrLoadBufEntries ={2};
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bins NrLoadBufEntries ={1};
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}
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cp_InstrTlbEntries : coverpoint cva6_config_pkg::CVA6ConfigInstrTlbEntries {
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bins InstrTlbEntries ={2};
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@ -130,7 +130,7 @@ covergroup cg_cva6_config(string name) with function sample();
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bins DataTlbEntries ={2};
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}
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cp_RASDepth : coverpoint cva6_config_pkg::CVA6ConfigRASDepth {
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bins RASDepth ={0};
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bins RASDepth ={2};
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}
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cp_BTBEntries : coverpoint cva6_config_pkg::CVA6ConfigBTBEntries {
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bins BTBEntries ={0};
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19
verif/env/uvme/reg/cva6_csr_reg_file.sv
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19
verif/env/uvme/reg/cva6_csr_reg_file.sv
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@ -96,22 +96,22 @@ class reg_mstatus extends csr_reg;
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MPRV: coverpoint data[17:17];
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XS: coverpoint data[16:15] {
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bins legal_values[] = {0};
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//GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
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illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
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}
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FS: coverpoint data[14:13] {
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bins legal_values[] = {0};
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//GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
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illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
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}
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MPP: coverpoint data[12:11];
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VS: coverpoint data[10:9] {
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bins legal_values[] = {0};
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//GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
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illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
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}
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SPP: coverpoint data[8:8];
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MPIE: coverpoint data[7:7];
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UBE: coverpoint data[6:6] {
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bins legal_values[] = {0};
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//GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
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illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
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}
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SPIE: coverpoint data[5:5];
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MIE: coverpoint data[3:3];
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@ -256,8 +256,9 @@ class reg_misa extends csr_reg;
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illegal_bins illegal_values = {[0:$]} with (!(item inside {1}));
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}
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Extensions: coverpoint data[25:0] {
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bins legal_values[] = {26'h0001104};
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illegal_bins illegal_values = {[0:$]} with (!(item inside {26'h0001104}));
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bins legal_values[] = {26'h0001106};
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//TODO : Fix issue#1734
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//illegal_bins illegal_values = {[0:$]} with (!(item inside {26'h0001106}));
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}
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endgroup
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@ -269,8 +270,8 @@ class reg_misa extends csr_reg;
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bins illegal_values[] = {[0:$]} with (!(item inside {1}));
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}
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Extensions: coverpoint data[25:0] {
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bins legal_values[] = {26'h0001104};
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bins illegal_values[3] = {[0:$]} with (!(item inside {26'h0001104}));
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bins legal_values[] = {26'h0001106};
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bins illegal_values[3] = {[0:$]} with (!(item inside {26'h0001106}));
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}
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endgroup
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@ -297,7 +298,7 @@ class reg_misa extends csr_reg;
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MXL.configure(.parent(this), .size(2), .lsb_pos(30), .access("RW"), .volatile(0), .reset(0), .has_reset(1), .is_rand(1), .individually_accessible(0));
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Extensions = uvm_reg_field::type_id::create("Extensions");
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Extensions.configure(.parent(this), .size(26), .lsb_pos(0), .access("RW"), .volatile(0), .reset(37782532), .has_reset(1), .is_rand(1), .individually_accessible(0));
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Extensions.configure(.parent(this), .size(26), .lsb_pos(0), .access("RW"), .volatile(0), .reset(26'h0001106), .has_reset(1), .is_rand(1), .individually_accessible(0));
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endfunction
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virtual function void sample(uvm_reg_data_t data, uvm_reg_data_t byte_en,bit is_read, uvm_reg_map map);
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@ -253,7 +253,7 @@ vcs-uvm:
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$(tool_path)/spike-dasm --isa=$(variant) < ./vcs_results/default/vcs.d/trace_rvfi_hart_00.dasm > $(log)
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generate_cov_dash:
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urg -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes description -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp -tgl portsonly
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urg -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes weight+description+Comment -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -tgl portsonly
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vcs_clean_all:
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@echo "[VCS] Cleanup (entire vcs_work dir)"
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@ -1,6 +1,7 @@
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plan "CVA6 Verification Master Plan";
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attribute string Comment = "";
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description = "CVA6 Verification Master Plan";
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feature "Programmer view level";
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@ -9,7 +10,10 @@ plan "CVA6 Verification Master Plan";
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description = "Instruction Set Architecture\nSpecification: Done, Dvplan: Done, Verification execution: Done";
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feature RV32I;
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description = "I extension";
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Comment = "";
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feature ADD;
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Comment = "Issue in Spike-dasm decoder
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Waiting for ISA_DECODER to be merge on master";
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measure Group ADD;
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source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_add_cg";
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endmeasure
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@ -65,16 +69,19 @@ plan "CVA6 Verification Master Plan";
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endmeasure
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endfeature
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feature DRET;
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Comment = "RVFI limitation issue(#1338)";
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measure Group DRET;
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source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_dret_cg";
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endmeasure
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endfeature
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feature EBREAK;
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Comment = "RVFI limitation issue(#1338)";
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measure Group EBREAK;
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source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_ebreak_cg";
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endmeasure
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endfeature
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feature ECALL;
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Comment = "RVFI limitation issue(#1338)";
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measure Group ECALL;
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source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_ecall_cg";
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endmeasure
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@ -331,6 +338,7 @@ plan "CVA6 Verification Master Plan";
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endmeasure
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endfeature
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feature EBREAK;
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Comment = "RVFI limitation issue(#1338)";
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measure Group EBREAK;
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source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32c_ebreak_cg";
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endmeasure
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@ -461,6 +469,7 @@ plan "CVA6 Verification Master Plan";
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endfeature
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feature RV32ZIFENCEI;
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description = "ZIFENCE.I extension";
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Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master";
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measure Group FEINCE_I;
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source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32zifencei_fence_i_cg";
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endmeasure
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@ -478,6 +487,7 @@ plan "CVA6 Verification Master Plan";
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feature RV32ZCB;
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weight = 0;
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description = "ZCB extension";
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Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master";
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measure Group C_MUL;
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endmeasure
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measure Group C_ZEXT_B;
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@ -495,6 +505,7 @@ plan "CVA6 Verification Master Plan";
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endfeature
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feature RV32ZB;
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description = "Bitmanip extension";
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Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master";
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feature RV32ZBA;
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measure Group SH1ADD;
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source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32zba_sh1add_cg";
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@ -608,12 +619,14 @@ plan "CVA6 Verification Master Plan";
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endfeature
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feature "Illegal instructions";
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weight = 0;
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Comment = "RVFI limitation issue(#1338)";
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measure Group illegal_instructions;
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endmeasure
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endfeature
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endfeature
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feature "CSR access";
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description = "CSR registers access.\nSpecification: Done, Dvplan: Done, Verification execution: Done";
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Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master";
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feature "CSR CODE COVERAGE";
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measure Line, Cond, Toggle CSR_code_cov;
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source = "tree: uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.csr_regfile_i";
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@ -1272,6 +1285,7 @@ plan "CVA6 Verification Master Plan";
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endfeature
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feature TRAPs;
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description = "Interrupts and Exceptions.\nSpecification: Done, Dvplan: Done, Verification execution: No.";
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Comment = "RVFI limitation issue(#1338)";
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feature Interrupts;
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measure Group Interrupts;
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endmeasure
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@ -1288,6 +1302,7 @@ plan "CVA6 Verification Master Plan";
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endfeature
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feature PMP;
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description = "Physical Memory Protection suppor.t\nSpecification: No, Dvplan: No, Verification execution: No.";
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Comment = "Need to separate PMP from MMU";
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measure Group PMP;
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endmeasure
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endfeature
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@ -1343,6 +1358,11 @@ plan "CVA6 Verification Master Plan";
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measure Group Features;
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endmeasure
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endfeature
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feature "Code Coverage";
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measure Line, Cond, Toggle, Assert, SnpsAvg AXI;
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source = "tree: uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.gen_cache_wt.i_cache_subsystem.i_adapter.i_axi_shim";
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endmeasure
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endfeature
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feature Assertions;
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measure Assert axi_protocol_assertion;
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source = "property: **.axi_ar_assert.*", "property: **.axi_aw_assert.*", "property: **.axi_b_assert.*", "property: **.axi_r_assert.*", "property: **.axi_w_assert.*";
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@ -1363,6 +1383,11 @@ plan "CVA6 Verification Master Plan";
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source = "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_after_n_cycle", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_kill", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_same_cycle", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_valid_pulse", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_issue_multic", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_issue_resp_null_when_n_accept", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_res_multic", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_res_multic_we", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_result_dualwrite", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_sync_exc";
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endmeasure
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endfeature
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feature "Code Coverage";
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measure Line, Cond, Toggle, Assert, SnpsAvg CVXIF;
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source = "tree: uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.ex_stage_i.gen_cvxif.cvxif_fu_i";
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endmeasure
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endfeature
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feature "Extended instructions";
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description = "XIF extended instructions";
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feature Instructions;
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