[DOCS] Add Zcb Instructions in CVA6 user guide and requirement specification (#1536)

docs/01_cva6_user/Programmer_View.rst

@@ -33,6 +33,7 @@ RISC-V Extensions
    "A - Atomic Instructions",                                           "Yes","✓","✓"
    "Zb* - Bit-Manipulation",                                            "Yes","✓","✓"
    "C - Compressed Instructions ",                                      "Yes","✓","✓"
+   "Zcb - Code Size Reduction",                                         "Yes","✓","✓"
    "D - Double precsision floating-point",                              "Yes","✗ ","✓"
    "F - Single precsision floating-point",                              "Yes","✓","✓"
    "M - Integer Multiply/Divide",                                       "No","✓","✓"

docs/01_cva6_user/RISCV_Instructions.rst

@@ -29,6 +29,7 @@ In this document, we present ISA (Instruction Set Architecture) for C32VA6_v5.0.
 * RV32M        – Standard Extension for Integer Multiplication and Division Instructions
 * RV32A        – Standard Extension for Atomic Instructions
 * RV32C        – Standard Extension for Compressed Instructions
+* RV32Zcb      – Standard Extension for Code Size Reduction
 * RV32Zicsr    – Standard Extension for CSR Instructions
 * RV32Zifencei – Standard Extension for Instruction-Fetch Fence
 * RV32Zicond   – Standard Extension for Integer Conditional Operations
@@ -916,7 +917,7 @@ Atomic Memory Operations
     **Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated.
 
 RV32C Compressed Instructions
---------------------------------
+----------------------------------
 
 RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V
 instructions when:
@@ -1252,6 +1253,156 @@ Load and Store Instructions
 
     **Exception raised**: an exception raised if the memory address isn't aligned (4-byte boundary).
 
+RV32ZCB Code Size Reduction Instructions
+-----------------------------------------
+
+Zcb belongs to group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of Standard C extension adding more 16-bit insturctions to the ISA. Zcb includes 16-bit version of additional Integer (I), Multiply (M) and Bit-Manipulation (Zbb) Instructions. 
+All the Zcb instructions require at least standard C extension support as pre-requisite, along with M and Zbb extensions for 16-bit version of the respective instructions.
+
+- **C.ZEXT.B**: Compressed Zero Extend Byte
+
+    **Format**: c.zext.b rd'
+
+    **Description**: This instruction takes a single source/destination operand. It zero-extends the least-significant byte of the operand by inserting zeros into all of the bits more significant than 7.
+
+    **Pseudocode**: x[8 + rd'] = zext(x[8 + rd'][7:0])
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+- **C.SEXT.B**: Compressed Sign Extend Byte
+
+    **Format**: c.sext.b rd'
+
+    **Description**: This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support.
+
+    **Pseudocode**: x[8 + rd'] = sext(x[8 + rd'][7:0])
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+- **C.ZEXT.H**: Compressed Zero Extend Halfword
+
+    **Format**: c.zext.h rd'
+
+    **Description**: This instruction takes a single source/destination operand. It zero-extends the least-significant halfword of the operand by inserting zeros into all of the bits more significant than 15. It also requires Bit-Manipulation (Zbb) extension support.
+
+    **Pseudocode**: x[8 + rd'] = zext(x[8 + rd'][15:0])
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+- **C.SEXT.H**: Compressed Sign Extend Halfword
+
+    **Format**: c.sext.h rd'
+
+    **Description**: This instruction takes a single source/destination operand. It sign-extends the least-significant halfword in the operand by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.  It also requires Bit-Manipulation (Zbb) extension support.
+
+    **Pseudocode**: x[8 + rd'] = sext(x[8 + rd'][15:0])
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+- **C.ZEXT.W**: Compressed Zero Extend Word
+
+    **Format**: c.zext.w rd'
+
+    **Description**: This instruction takes a single source/destination operand. It zero-extends the least-significant word of the operand by inserting zeros into all of the bits more significant than 31. It also requires Bit-Manipulation (Zbb) extension support.
+
+    **Pseudocode**: x[8 + rd'] = zext(x[8 + rd'][31:0])
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+- **C.NOT**: Compressed Bitwise NOT
+
+    **Format**: c.not rd'
+
+    **Description**: This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register.
+
+    **Pseudocode**: x[8 + rd'] = x[8 + rd'] ^ -1
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+- **C.MUL**: Compressed Multiply
+
+    **Format**: c.mul rd', rs2'
+
+    **Description**: performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rd' and rs2' treated as signed numbers). It also requires M extension support.
+
+    **Pseudocode**: x[8 + rd'] = (x[8 + rd'] * x[8 + rs2'])[31:0]
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+- **C.LHU**: Compressed Load Halfword Unsigned
+
+    **Format**: c.lhu rd', uimm(rs1')
+
+    **Description**: This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended and is written to rd'.
+
+    **Pseudocode**: x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1])][15:0])
+
+    **Invalid values**: NONE
+
+    **Exception raised**: an exception raised if the memory address isn't aligned (2-byte boundary).
+
+- **C.LH**: Compressed Load Halfword
+
+    **Format**: c.lh rd', uimm(rs1')
+
+    **Description**: This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended and is written to rd'.
+
+    **Pseudocode**: x[8+rd'] = sext(M[x[8+rs1'] + zext(uimm[1])][15:0])
+
+    **Invalid values**: NONE
+
+    **Exception raised**: an exception raised if the memory address isn't aligned (2-byte boundary).
+
+- **C.LBU**: Compressed Load Byte Unsigned
+
+    **Format**: c.lbu rd', uimm(rs1')
+
+    **Description**: This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended and is written to rd'.
+
+    **Pseudocode**: x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1:0])][7:0])
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+- **C.SH**: Compressed Store Halfword
+
+    **Format**: c.sh rs2', uimm(rs1')
+
+    **Description**: This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.
+
+    **Pseudocode**: M[x[8+rs1'] + zext(uimm[1])][15:0] = x[8+rs2']
+
+    **Invalid values**: NONE
+
+    **Exception raised**: an exception raised if the memory address isn't aligned (2-byte boundary).
+
+- **C.SB**: Compressed Store Byte
+
+    **Format**: c.sb rs2', uimm(rs1')
+
+    **Description**: This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.
+
+    **Pseudocode**: M[x[8+rs1'] + zext(uimm[1:0])][7:0] = x[8+rs2']
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
 RV32Zicsr Control and Status Register Instructions
 ---------------------------------------------------
 

docs/02_cva6_requirements/cva6_requirements_specification.rst

@@ -316,6 +316,10 @@ independent requirements.
 |                                   | extension(ratification pending)   |
 |                                   | version 1.0.                      |
 +-----------------------------------+-----------------------------------+
+| ISA-140                           | CVA6 should support as an         |
+|                                   | **option** the **Zcb**            |
+|                                   | extension version 1.0.            |
++-----------------------------------+-----------------------------------+
 
 
 Note to ISA-60 and ISA-70: CV64A6 cannot support the D extension with