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LINT: Initial changes for Lint warnings removal (#1158)

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Umer Imran 2023-04-24 11:22:56 +05:00 • committed by GitHub
parent 9668e0fd78
commit 45259cfb6a
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18 changed files with 207 additions and 183 deletions
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73
Makefile
View file

@ -86,6 +86,7 @@ endif
# target takes one of the following cva6 hardware configuration:
# cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv32a6_ima_sv32_fpga
# Changing the default target to cv32a60x for Step1 verification
target ?= cv64a6_imafdc_sv39
ifndef TARGET_CFG
export TARGET_CFG = $(target)
@ -138,8 +139,7 @@ endif
# this list contains the standalone components
src := core/include/$(target)_config_pkg.sv \
corev_apu/tb/ariane.sv \
src := corev_apu/tb/ariane.sv \
$(wildcard corev_apu/bootrom/*.sv) \
$(wildcard corev_apu/clint/*.sv) \
$(wildcard corev_apu/fpga/src/axi2apb/src/*.sv) \
@ -160,36 +160,31 @@ src := core/include/$(target)_config_pkg.sv
corev_apu/riscv-dbg/src/dm_top.sv \
corev_apu/riscv-dbg/debug_rom/debug_rom.sv \
corev_apu/register_interface/src/apb_to_reg.sv \
vendor/pulp-platform/axi/src/axi_multicut.sv \
vendor/pulp-platform/common_cells/src/rstgen_bypass.sv \
vendor/pulp-platform/common_cells/src/rstgen.sv \
vendor/pulp-platform/common_cells/src/stream_mux.sv \
vendor/pulp-platform/common_cells/src/stream_demux.sv \
vendor/pulp-platform/common_cells/src/exp_backoff.sv \
vendor/pulp-platform/common_cells/src/addr_decode.sv \
vendor/pulp-platform/common_cells/src/stream_register.sv \
vendor/pulp-platform/axi/src/axi_cut.sv \
vendor/pulp-platform/axi/src/axi_join.sv \
vendor/pulp-platform/axi/src/axi_delayer.sv \
vendor/pulp-platform/axi/src/axi_to_axi_lite.sv \
vendor/pulp-platform/axi/src/axi_id_prepend.sv \
vendor/pulp-platform/axi/src/axi_atop_filter.sv \
vendor/pulp-platform/axi/src/axi_err_slv.sv \
vendor/pulp-platform/axi/src/axi_mux.sv \
vendor/pulp-platform/axi/src/axi_demux.sv \
vendor/pulp-platform/axi/src/axi_xbar.sv \
vendor/pulp-platform/common_cells/src/cdc_2phase.sv \
vendor/pulp-platform/common_cells/src/spill_register_flushable.sv \
vendor/pulp-platform/common_cells/src/spill_register.sv \
vendor/pulp-platform/common_cells/src/stream_arbiter.sv \
vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv \
vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv \
vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv \
vendor/pulp-platform/common_cells/src/stream_delay.sv \
vendor/pulp-platform/common_cells/src/lfsr_16bit.sv \
vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv \
vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv \
vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv \
vendor/pulp-platform/axi/src/axi_multicut.sv \
vendor/pulp-platform/common_cells/src/rstgen_bypass.sv \
vendor/pulp-platform/common_cells/src/rstgen.sv \
vendor/pulp-platform/common_cells/src/addr_decode.sv \
vendor/pulp-platform/common_cells/src/stream_register.sv \
vendor/pulp-platform/axi/src/axi_cut.sv \
vendor/pulp-platform/axi/src/axi_join.sv \
vendor/pulp-platform/axi/src/axi_delayer.sv \
vendor/pulp-platform/axi/src/axi_to_axi_lite.sv \
vendor/pulp-platform/axi/src/axi_id_prepend.sv \
vendor/pulp-platform/axi/src/axi_atop_filter.sv \
vendor/pulp-platform/axi/src/axi_err_slv.sv \
vendor/pulp-platform/axi/src/axi_mux.sv \
vendor/pulp-platform/axi/src/axi_demux.sv \
vendor/pulp-platform/axi/src/axi_xbar.sv \
vendor/pulp-platform/common_cells/src/cdc_2phase.sv \
vendor/pulp-platform/common_cells/src/spill_register_flushable.sv \
vendor/pulp-platform/common_cells/src/spill_register.sv \
vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv \
vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv \
vendor/pulp-platform/common_cells/src/stream_delay.sv \
vendor/pulp-platform/common_cells/src/lfsr_16bit.sv \
vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv \
vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv \
vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv \
corev_apu/tb/ariane_testharness.sv \
corev_apu/tb/ariane_peripherals.sv \
corev_apu/tb/rvfi_tracer.sv \
@ -197,13 +192,6 @@ src := core/include/$(target)_config_pkg.sv
corev_apu/tb/common/SimDTM.sv \
corev_apu/tb/common/SimJTAG.sv
# SV32 MMU for CV32, SV39 MMU for CV64
ifeq ($(findstring 32, $(target)),32)
src += $(wildcard core/mmu_sv32/*.sv)
else
src += $(wildcard core/mmu_sv39/*.sv)
endif
src := $(addprefix $(root-dir), $(src))
copro_src := core/cvxif_example/include/cvxif_instr_pkg.sv \
@ -538,7 +526,7 @@ xrun-check-benchmarks:
xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchmarks
# verilator-specific
verilate_command := $(verilator) \
verilate_command := $(verilator) verilator_config.vlt \
-f core/Flist.cva6 \
$(filter-out %.vhd, $(ariane_pkg)) \
$(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
@ -547,6 +535,7 @@ verilate_command := $(verilator)
+incdir+corev_apu/axi_node \
$(if $(verilator_threads), --threads $(verilator_threads)) \
--unroll-count 256 \
-Wall \
-Werror-PINMISSING \
-Werror-IMPLICIT \
-Wno-fatal \
@ -565,9 +554,9 @@ verilate_command := $(verilator)
$(if $(TRACE_FAST), --trace $(VERILATOR_ROOT)/include/verilated_vcd_c.cpp,) \
-LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -L../corev_apu/tb/dromajo/src -ldromajo_cosim,) -lpthread $(if $(TRACE_COMPACT), -lz,)" \
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -DDROMAJO=1,) -DVL_DEBUG" \
-Wall --cc --vpi \
--cc --vpi \
$(list_incdir) --top-module ariane_testharness \
--threads-dpi none \
--threads-dpi none \
--Mdir $(ver-library) -O3 \
--exe corev_apu/tb/ariane_tb.cpp corev_apu/tb/dpi/SimDTM.cc corev_apu/tb/dpi/SimJTAG.cc \
corev_apu/tb/dpi/remote_bitbang.cc corev_apu/tb/dpi/msim_helper.cc $(if $(DROMAJO), corev_apu/tb/dpi/dromajo_cosim_dpi.cc,)

2
common/local/util/sram.sv
View file

@ -114,7 +114,7 @@ end
.addr_i ( addr_i ),
.rdata_o ( rdata_aligned[k*64 +: 64] )
);
if (USER_EN) begin : gen_mem_user
if (USER_EN > 0) begin : gen_mem_user
tc_sram_wrapper #(
.NumWords(NUM_WORDS), // Number of Words in data array
.DataWidth(64), // Data signal width

6
core/cache_subsystem/axi_adapter.sv
View file

@ -166,7 +166,7 @@ module axi_adapter #(
// its a request for the whole cache line
end else begin
// bursts of AMOs unsupported
assert (amo_i == ariane_pkg::AMO_NONE)
assert (amo_i == ariane_pkg::AMO_NONE)
else $fatal("Bursts of atomic operations are not supported");
axi_req_o.aw.len = BURST_SIZE; // number of bursts to do
@ -194,7 +194,7 @@ module axi_adapter #(
gnt_o = axi_resp_i.ar_ready;
if (type_i != ariane_axi::SINGLE_REQ) begin
assert (amo_i == ariane_pkg::AMO_NONE)
assert (amo_i == ariane_pkg::AMO_NONE)
else $fatal("Bursts of atomic operations are not supported");
axi_req_o.ar.len = BURST_SIZE;
@ -395,6 +395,8 @@ module axi_adapter #(
state_d = IDLE;
id_o = id_q;
end
default: state_d = IDLE;
endcase
end

2
core/cache_subsystem/cva6_icache_axi_wrapper.sv
View file

@ -201,4 +201,4 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #(
end
end
endmodule // cva6_icache_axi_wrapper
endmodule // cva6_icache_axi_wrapper

2
core/cache_subsystem/wt_axi_adapter.sv
View file

@ -248,8 +248,10 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
AMO_MAXU: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX};
AMO_MIN: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN};
AMO_MINU: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN};
default: ; // Do nothing
endcase
end
default: ; // Do nothing
//////////////////////////////////////
endcase
end

4
core/cache_subsystem/wt_dcache_missunit.sv
View file

@ -302,7 +302,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
end
end
DCACHE_STORE_ACK: begin
if (stores_inflight_q) begin
if (stores_inflight_q>0) begin
store_ack = 1'b1;
miss_rtrn_vld_o[NumPorts-1] = 1'b1;
end
@ -313,7 +313,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
// need to set SC backoff counter if
// this op failed
if (amo_req_i.amo_op == AMO_SC) begin
if (amo_resp_o.result) begin
if (amo_resp_o.result>0) begin
sc_fail = 1'b1;
end else begin
sc_pass = 1'b1;

1
core/cva6.sv
View file

@ -947,6 +947,7 @@ module cva6 import ariane_pkg::*; #(
riscv::PRIV_LVL_M: mode = "M";
riscv::PRIV_LVL_S: mode = "S";
riscv::PRIV_LVL_U: mode = "U";
default: ; // Do nothing
endcase
end
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin

17
core/fpu_wrap.sv
View file

@ -51,7 +51,7 @@ module fpu_wrap import ariane_pkg::*; (
// Features (enabled formats, vectors etc.)
localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
Width: riscv::XLEN, // parameterized using XLEN
Width: unsigned'(riscv::XLEN), // parameterized using XLEN
EnableVectors: ariane_pkg::XFVEC,
EnableNanBox: 1'b1,
FpFmtMask: {RVF, RVD, XF16, XF8, XF16ALT},
@ -61,10 +61,14 @@ module fpu_wrap import ariane_pkg::*; (
// Implementation (number of registers etc)
localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
PipeRegs: '{// FP32, FP64, FP16, FP8, FP16alt
'{LAT_COMP_FP32, LAT_COMP_FP64, LAT_COMP_FP16, LAT_COMP_FP8, LAT_COMP_FP16ALT}, // ADDMUL
'{default: LAT_DIVSQRT}, // DIVSQRT
'{default: LAT_NONCOMP}, // NONCOMP
'{default: LAT_CONV}}, // CONV
'{unsigned'(LAT_COMP_FP32 ),
unsigned'(LAT_COMP_FP64 ),
unsigned'(LAT_COMP_FP16 ),
unsigned'(LAT_COMP_FP8 ),
unsigned'(LAT_COMP_FP16ALT)}, // ADDMUL
'{default: unsigned'(LAT_DIVSQRT)}, // DIVSQRT
'{default: unsigned'(LAT_NONCOMP)}, // NONCOMP
'{default: unsigned'(LAT_CONV)}}, // CONV
UnitTypes: '{'{default: fpnew_pkg::PARALLEL}, // ADDMUL
'{default: fpnew_pkg::MERGED}, // DIVSQRT
'{default: fpnew_pkg::PARALLEL}, // NONCOMP
@ -253,6 +257,7 @@ module fpu_wrap import ariane_pkg::*; (
3'b010: fpu_srcfmt_d = fpnew_pkg::FP16;
3'b110: fpu_srcfmt_d = fpnew_pkg::FP16ALT;
3'b011: fpu_srcfmt_d = fpnew_pkg::FP8;
default: ; // Do nothing
endcase
end
end
@ -392,6 +397,7 @@ module fpu_wrap import ariane_pkg::*; (
fpnew_pkg::FP16,
fpnew_pkg::FP16ALT: operand_c_d = RVD ? {4{operand_c_i[15:0]}} : {2{operand_c_i[15:0]}};
fpnew_pkg::FP8: operand_c_d = RVD ? {8{operand_c_i[7:0]}} : {4{operand_c_i[7:0]}};
default: ; // Do nothing
endcase // fpu_dstfmt_d
end else begin
unique case (fpu_dstfmt_d)
@ -399,6 +405,7 @@ module fpu_wrap import ariane_pkg::*; (
fpnew_pkg::FP16,
fpnew_pkg::FP16ALT: operand_b_d = RVD ? {4{operand_b_i[15:0]}} : {2{operand_b_i[15:0]}};
fpnew_pkg::FP8: operand_b_d = RVD ? {8{operand_b_i[7:0]}} : {4{operand_b_i[7:0]}};
default: ; // Do nothing
endcase // fpu_dstfmt_d
end
end

52
core/include/ariane_pkg.sv
View file

@ -55,27 +55,27 @@ package ariane_pkg;
} ariane_cfg_t;
localparam ariane_cfg_t ArianeDefaultConfig = '{
RASDepth: cva6_config_pkg::CVA6ConfigRASDepth,
BTBEntries: cva6_config_pkg::CVA6ConfigBTBEntries,
BHTEntries: cva6_config_pkg::CVA6ConfigBHTEntries,
RASDepth: int'(cva6_config_pkg::CVA6ConfigRASDepth),
BTBEntries: int'(cva6_config_pkg::CVA6ConfigBTBEntries),
BHTEntries: int'(cva6_config_pkg::CVA6ConfigBHTEntries),
// idempotent region
NrNonIdempotentRules: 2,
NonIdempotentAddrBase: {64'b0, 64'b0},
NonIdempotentLength: {64'b0, 64'b0},
NrExecuteRegionRules: 3,
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: {64'h8000_0000, 64'h1_0000, 64'h0},
ExecuteRegionLength: {64'h40000000, 64'h10000, 64'h1000},
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: 1,
CachedRegionAddrBase: {64'h8000_0000},
CachedRegionLength: {64'h40000000},
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),
// cache config
AxiCompliant: 1'b1,
SwapEndianess: 1'b0,
// debug
DmBaseAddress: 64'h0,
NrPMPEntries: cva6_config_pkg::CVA6ConfigNrPMPEntries
NrPMPEntries: unsigned'(cva6_config_pkg::CVA6ConfigNrPMPEntries)
};
// Function being called to check parameters
@ -206,17 +206,17 @@ package ariane_pkg;
localparam riscv::xlen_t OPENHWGROUP_MVENDORID = {{riscv::XLEN-32{1'b0}}, 32'h0602};
localparam riscv::xlen_t ARIANE_MARCHID = {{riscv::XLEN-32{1'b0}}, 32'd3};
localparam riscv::xlen_t ISA_CODE = (RVA << 0) // A - Atomic Instructions extension
| (RVC << 2) // C - Compressed extension
| (RVD << 3) // D - Double precsision floating-point extension
| (RVF << 5) // F - Single precsision floating-point extension
| (1 << 8) // I - RV32I/64I/128I base ISA
| (1 << 12) // M - Integer Multiply/Divide extension
| (0 << 13) // N - User level interrupts supported
| (1 << 18) // S - Supervisor mode implemented
| (1 << 20) // U - User mode implemented
| (NSX << 23) // X - Non-standard extensions present
| ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN-2); // MXL
localparam riscv::xlen_t ISA_CODE = (riscv::XLEN'(RVA) << 0) // A - Atomic Instructions extension
| (riscv::XLEN'(RVC) << 2) // C - Compressed extension
| (riscv::XLEN'(RVD) << 3) // D - Double precsision floating-point extension
| (riscv::XLEN'(RVF) << 5) // F - Single precsision floating-point extension
| (riscv::XLEN'(1 ) << 8) // I - RV32I/64I/128I base ISA
| (riscv::XLEN'(1 ) << 12) // M - Integer Multiply/Divide extension
| (riscv::XLEN'(0 ) << 13) // N - User level interrupts supported
| (riscv::XLEN'(1 ) << 18) // S - Supervisor mode implemented
| (riscv::XLEN'(1 ) << 20) // U - User mode implemented
| (riscv::XLEN'(NSX) << 23) // X - Non-standard extensions present
| ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN-2); // MXL
// 32 registers + 1 bit for re-naming = 6
localparam REG_ADDR_SIZE = 6;
@ -888,6 +888,7 @@ package ariane_pkg;
3'b010: return 8'b0011_1100;
3'b011: return 8'b0111_1000;
3'b100: return 8'b1111_0000;
default: ; // Do nothing
endcase
end
2'b01: begin
@ -899,6 +900,7 @@ package ariane_pkg;
3'b100: return 8'b0011_0000;
3'b101: return 8'b0110_0000;
3'b110: return 8'b1100_0000;
default: ; // Do nothing
endcase
end
2'b00: begin
@ -927,7 +929,7 @@ package ariane_pkg;
2'b00: return 4'b0011;
2'b01: return 4'b0110;
2'b10: return 4'b1100;
default: ; // Do nothing
endcase
end
2'b00: begin

2
core/include/instr_tracer_pkg.sv
View file

@ -199,4 +199,4 @@ package instr_tracer_pkg;
parameter [31:0] C_SDSP = 32'b????????????????111???????????10;
endpackage
`endif
`endif

12
core/include/riscv_pkg.sv
View file

@ -333,12 +333,12 @@ package riscv;
localparam logic [XLEN-1:0] MIP_SEIP = 1 << IRQ_S_EXT;
localparam logic [XLEN-1:0] MIP_MEIP = 1 << IRQ_M_EXT;
localparam logic [XLEN-1:0] S_SW_INTERRUPT = (1 << (XLEN-1)) | IRQ_S_SOFT;
localparam logic [XLEN-1:0] M_SW_INTERRUPT = (1 << (XLEN-1)) | IRQ_M_SOFT;
localparam logic [XLEN-1:0] S_TIMER_INTERRUPT = (1 << (XLEN-1)) | IRQ_S_TIMER;
localparam logic [XLEN-1:0] M_TIMER_INTERRUPT = (1 << (XLEN-1)) | IRQ_M_TIMER;
localparam logic [XLEN-1:0] S_EXT_INTERRUPT = (1 << (XLEN-1)) | IRQ_S_EXT;
localparam logic [XLEN-1:0] M_EXT_INTERRUPT = (1 << (XLEN-1)) | IRQ_M_EXT;
localparam logic [XLEN-1:0] S_SW_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_S_SOFT);
localparam logic [XLEN-1:0] M_SW_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_M_SOFT);
localparam logic [XLEN-1:0] S_TIMER_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_S_TIMER);
localparam logic [XLEN-1:0] M_TIMER_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_M_TIMER);
localparam logic [XLEN-1:0] S_EXT_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_S_EXT);
localparam logic [XLEN-1:0] M_EXT_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_M_EXT);
// -----
// CSRs

8
core/load_unit.sv
View file

@ -241,6 +241,8 @@ module load_unit import ariane_pkg::*; #(
// we've killed the current request so we can go back to idle
state_d = IDLE;
end
default: state_d = IDLE;
endcase
// we got an exception
@ -343,16 +345,16 @@ module load_unit import ariane_pkg::*; #(
// prepare these signals for faster selection in the next cycle
assign signed_d = load_data_d.operation inside {ariane_pkg::LW, ariane_pkg::LH, ariane_pkg::LB};
assign fp_sign_d = load_data_d.operation inside {ariane_pkg::FLW, ariane_pkg::FLH, ariane_pkg::FLB};
assign idx_d = ((load_data_d.operation inside {ariane_pkg::LW, ariane_pkg::FLW}) & riscv::IS_XLEN64) ? load_data_d.address_offset + 3 :
(load_data_d.operation inside {ariane_pkg::LH, ariane_pkg::FLH}) ? load_data_d.address_offset + 1 :
load_data_d.address_offset;
for (genvar i = 0; i < (riscv::XLEN/8); i++) begin : gen_sign_bits
assign sign_bits[i] = req_port_i.data_rdata[(i+1)*8-1];
assign sign_bits[i] = req_port_i.data_rdata[(i+1)*8-1];
end
// select correct sign bit in parallel to result shifter above
// pull to 0 if unsigned

98
core/perf_counters.sv
View file

@ -15,7 +15,7 @@
module perf_counters import ariane_pkg::*; #(
parameter int unsigned NumPorts = 3 // number of miss ports
) (
) (
input logic clk_i,
input logic rst_ni,
input logic debug_mode_i, // debug mode
@ -54,17 +54,17 @@ module perf_counters import ariane_pkg::*; #(
logic [63:0] generic_counter_q[6:1];
//internal signal to keep track of exception
logic read_access_exception,update_access_exception;
logic read_access_exception,update_access_exception;
logic events[6:1];
logic events[6:1];
//internal signal for MUX select line input
logic [4:0] mhpmevent_d[6:1];
logic [4:0] mhpmevent_q[6:1];
//Multiplexer
//Multiplexer
always_comb begin : Mux
events[6:1]='{default:0};
for(int unsigned i = 1; i <= 6; i++) begin
case(mhpmevent_q[i])
5'b00000 : events[i] = 0;
@ -72,11 +72,11 @@ module perf_counters import ariane_pkg::*; #(
5'b00010 : events[i] = l1_dcache_miss_i;//L1 D-Cache misses
5'b00011 : events[i] = itlb_miss_i;//ITLB misses
5'b00100 : events[i] = dtlb_miss_i;//DTLB misses
5'b00101 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == LOAD;//Load accesses
5'b00101 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == LOAD;//Load accesses
5'b00110 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == STORE;//Store accesses
5'b00111 : events[i] = ex_i.valid;//Exceptions
5'b01000 : events[i] = eret_i;//Exception handler returns
5'b01001 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == CTRL_FLOW;//Branch instructions
5'b01001 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == CTRL_FLOW;//Branch instructions
5'b01010 : events[i] = resolved_branch_i.valid && resolved_branch_i.is_mispredict;//Branch mispredicts
5'b01011 : events[i] = branch_exceptions_i.valid;//Branch exceptions
// The standard software calling convention uses register x1 to hold the return address on a call
@ -87,7 +87,7 @@ module perf_counters import ariane_pkg::*; #(
5'b01111 : events[i] = if_empty_i;//Instruction fetch Empty
5'b10000 : events[i] = l1_icache_access_i.req;//L1 I-Cache accesses
5'b10001 : events[i] = l1_dcache_access_i[0].data_req || l1_dcache_access_i[1].data_req || l1_dcache_access_i[2].data_req;//L1 D-Cache accesses
5'b10010 : events[i] = (l1_dcache_miss_i && miss_vld_bits_i[0] == 8'hFF) || (l1_dcache_miss_i && miss_vld_bits_i[1] == 8'hFF) || (l1_dcache_miss_i && miss_vld_bits_i[2] == 8'hFF);//eviction
5'b10010 : events[i] = (l1_dcache_miss_i && miss_vld_bits_i[0] == 8'hFF) || (l1_dcache_miss_i && miss_vld_bits_i[1] == 8'hFF) || (l1_dcache_miss_i && miss_vld_bits_i[2] == 8'hFF);//eviction
5'b10011 : events[i] = i_tlb_flush_i;//I-TLB flush
5'b10100 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == ALU || commit_instr_i[j].fu == MULT;//Integer instructions
5'b10101 : for (int unsigned j = 0; j < NR_COMMIT_PORTS; j++) if (commit_ack_i[j]) events[i] = commit_instr_i[j].fu == FPU || commit_instr_i[j].fu == FPU_VEC;//Floating Point Instructions
@ -95,68 +95,68 @@ module perf_counters import ariane_pkg::*; #(
default: events[i] = 0;
endcase
end
end
end
always_comb begin : generic_counter
generic_counter_d = generic_counter_q;
data_o = 'b0;
mhpmevent_d = mhpmevent_q;
read_access_exception = 1'b0;
update_access_exception = 1'b0;
for(int unsigned i = 1; i <= 6; i++) begin
if ((!debug_mode_i) && (!we_i)) begin
for(int unsigned i = 1; i <= 6; i++) begin
if ((!debug_mode_i) && (!we_i)) begin
if (events[i] == 1)begin
generic_counter_d[i] = generic_counter_q[i] + 1'b1;end
else begin
generic_counter_d[i] = 'b0;end
generic_counter_d[i] = 'b0;end
end
end
end
//Read
unique case (addr_i)
riscv::CSR_MHPM_COUNTER_3,
riscv::CSR_MHPM_COUNTER_4,
riscv::CSR_MHPM_COUNTER_5,
riscv::CSR_MHPM_COUNTER_6,
riscv::CSR_MHPM_COUNTER_7,
riscv::CSR_MHPM_COUNTER_3,
riscv::CSR_MHPM_COUNTER_4,
riscv::CSR_MHPM_COUNTER_5,
riscv::CSR_MHPM_COUNTER_6,
riscv::CSR_MHPM_COUNTER_7,
riscv::CSR_MHPM_COUNTER_8 :begin if (riscv::XLEN == 32) data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3 + 1][31:0]; else data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3 + 1];end
riscv::CSR_MHPM_COUNTER_3H,
riscv::CSR_MHPM_COUNTER_4H,
riscv::CSR_MHPM_COUNTER_5H,
riscv::CSR_MHPM_COUNTER_6H,
riscv::CSR_MHPM_COUNTER_7H,
riscv::CSR_MHPM_COUNTER_3H,
riscv::CSR_MHPM_COUNTER_4H,
riscv::CSR_MHPM_COUNTER_5H,
riscv::CSR_MHPM_COUNTER_6H,
riscv::CSR_MHPM_COUNTER_7H,
riscv::CSR_MHPM_COUNTER_8H :begin if (riscv::XLEN == 32) data_o = generic_counter_q[addr_i-riscv::CSR_MHPM_COUNTER_3H + 1][63:32]; else read_access_exception = 1'b1;end
riscv::CSR_MHPM_EVENT_3,
riscv::CSR_MHPM_EVENT_4,
riscv::CSR_MHPM_EVENT_5,
riscv::CSR_MHPM_EVENT_6,
riscv::CSR_MHPM_EVENT_7,
riscv::CSR_MHPM_EVENT_3,
riscv::CSR_MHPM_EVENT_4,
riscv::CSR_MHPM_EVENT_5,
riscv::CSR_MHPM_EVENT_6,
riscv::CSR_MHPM_EVENT_7,
riscv::CSR_MHPM_EVENT_8 : data_o = mhpmevent_q[addr_i-riscv::CSR_MHPM_EVENT_3 + 1] ;
default: data_o = 'b0;
endcase
endcase
//Write
if(we_i) begin
unique case(addr_i)
riscv::CSR_MHPM_COUNTER_3,
riscv::CSR_MHPM_COUNTER_4,
riscv::CSR_MHPM_COUNTER_5,
riscv::CSR_MHPM_COUNTER_6,
riscv::CSR_MHPM_COUNTER_7,
riscv::CSR_MHPM_COUNTER_3,
riscv::CSR_MHPM_COUNTER_4,
riscv::CSR_MHPM_COUNTER_5,
riscv::CSR_MHPM_COUNTER_6,
riscv::CSR_MHPM_COUNTER_7,
riscv::CSR_MHPM_COUNTER_8 :begin if (riscv::XLEN == 32) generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3 + 1][31:0] = data_i; else generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3 + 1] = data_i; end
riscv::CSR_MHPM_COUNTER_3H,
riscv::CSR_MHPM_COUNTER_4H,
riscv::CSR_MHPM_COUNTER_5H,
riscv::CSR_MHPM_COUNTER_6H,
riscv::CSR_MHPM_COUNTER_7H,
riscv::CSR_MHPM_COUNTER_3H,
riscv::CSR_MHPM_COUNTER_4H,
riscv::CSR_MHPM_COUNTER_5H,
riscv::CSR_MHPM_COUNTER_6H,
riscv::CSR_MHPM_COUNTER_7H,
riscv::CSR_MHPM_COUNTER_8H :begin if (riscv::XLEN == 32) generic_counter_d[addr_i-riscv::CSR_MHPM_COUNTER_3H + 1][63:32] = data_i; else update_access_exception = 1'b1;end
riscv::CSR_MHPM_EVENT_3,
riscv::CSR_MHPM_EVENT_4,
riscv::CSR_MHPM_EVENT_5,
riscv::CSR_MHPM_EVENT_6,
riscv::CSR_MHPM_EVENT_7,
riscv::CSR_MHPM_EVENT_3,
riscv::CSR_MHPM_EVENT_4,
riscv::CSR_MHPM_EVENT_5,
riscv::CSR_MHPM_EVENT_6,
riscv::CSR_MHPM_EVENT_7,
riscv::CSR_MHPM_EVENT_8 : mhpmevent_d[addr_i-riscv::CSR_MHPM_EVENT_3 + 1] = data_i;
default: update_access_exception = 1'b1;
endcase

12
corev_apu/fpga/src/ariane_xilinx.sv
View file

@ -413,8 +413,8 @@ if (riscv::XLEN==32 ) begin
assign master[ariane_soc::Debug].r_user ='0;
assign master[ariane_soc::Debug].b_user ='0;
xlnx_axi_dwidth_converter_dm_slave i_axi_dwidth_converter_dm_slave(
xlnx_axi_dwidth_converter_dm_slave i_axi_dwidth_converter_dm_slave(
.s_axi_aclk(clk),
.s_axi_aresetn(ndmreset_n),
.s_axi_awid(master[ariane_soc::Debug].aw_id),
@ -550,7 +550,7 @@ end else begin
assign master[ariane_soc::Debug].r_ready = master_to_dm[0].r_ready;
end
end
@ -596,7 +596,7 @@ if (riscv::XLEN==32 ) begin
logic [31 : 0] dm_master_s_rdata;
assign dm_axi_m_resp.r.data = {32'h0000_0000, dm_master_s_rdata};
assign dm_axi_m_resp.r.data = {32'h0000_0000, dm_master_s_rdata};
assign slave[1].aw_user = '0;
assign slave[1].w_user = '0;
@ -606,7 +606,7 @@ if (riscv::XLEN==32 ) begin
assign slave[1].ar_id = dm_axi_m_req.ar.id;
assign slave[1].aw_atop = dm_axi_m_req.aw.atop;
xlnx_axi_dwidth_converter_dm_master i_axi_dwidth_converter_dm_master(
xlnx_axi_dwidth_converter_dm_master i_axi_dwidth_converter_dm_master(
.s_axi_aclk(clk),
.s_axi_aresetn(ndmreset_n),
.s_axi_awid(dm_axi_m_req.aw.id),
@ -777,7 +777,7 @@ if (riscv::XLEN==32 ) begin
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
end else begin
end else begin
bootrom_64 i_bootrom (
.clk_i ( clk ),
.req_i ( rom_req ),

26
corev_apu/tb/ariane_soc_pkg.sv
View file

@ -70,26 +70,26 @@ package ariane_soc;
localparam logic [NrRegion-1:0][NB_PERIPHERALS-1:0] ValidRule = {{NrRegion * NB_PERIPHERALS}{1'b1}};
localparam ariane_pkg::ariane_cfg_t ArianeSocCfg = '{
RASDepth: cva6_config_pkg::CVA6ConfigRASDepth,
BTBEntries: cva6_config_pkg::CVA6ConfigBTBEntries,
BHTEntries: cva6_config_pkg::CVA6ConfigBHTEntries,
RASDepth: int'(cva6_config_pkg::CVA6ConfigRASDepth),
BTBEntries: int'(cva6_config_pkg::CVA6ConfigBTBEntries),
BHTEntries: int'(cva6_config_pkg::CVA6ConfigBHTEntries),
// idempotent region
NrNonIdempotentRules: 1,
NonIdempotentAddrBase: {64'b0},
NonIdempotentLength: {DRAMBase},
NrExecuteRegionRules: 3,
ExecuteRegionAddrBase: {DRAMBase, ROMBase, DebugBase},
ExecuteRegionLength: {DRAMLength, ROMLength, DebugLength},
NrNonIdempotentRules: unsigned'(1),
NonIdempotentAddrBase: 1024'({64'b0}),
NonIdempotentLength: 1024'({DRAMBase}),
NrExecuteRegionRules: unsigned'(3),
ExecuteRegionAddrBase: 1024'({DRAMBase, ROMBase, DebugBase}),
ExecuteRegionLength: 1024'({DRAMLength, ROMLength, DebugLength}),
// cached region
NrCachedRegionRules: 1,
CachedRegionAddrBase: {DRAMBase},
CachedRegionLength: {DRAMLength},
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({DRAMBase}),
CachedRegionLength: 1024'({DRAMLength}),
// cache config
AxiCompliant: 1'b1,
SwapEndianess: 1'b0,
// debug
DmBaseAddress: DebugBase,
NrPMPEntries: cva6_config_pkg::CVA6ConfigNrPMPEntries
NrPMPEntries: unsigned'(cva6_config_pkg::CVA6ConfigNrPMPEntries)
};
endpackage

18
corev_apu/tb/ariane_testharness.sv
View file

@ -503,18 +503,18 @@ module ariane_testharness #(
};
localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{
NoSlvPorts: ariane_soc::NrSlaves,
NoMstPorts: ariane_soc::NB_PERIPHERALS,
MaxMstTrans: 1, // Probably requires update
MaxSlvTrans: 1, // Probably requires update
NoSlvPorts: unsigned'(ariane_soc::NrSlaves),
NoMstPorts: unsigned'(ariane_soc::NB_PERIPHERALS),
MaxMstTrans: unsigned'(1), // Probably requires update
MaxSlvTrans: unsigned'(1), // Probably requires update
FallThrough: 1'b0,
LatencyMode: axi_pkg::NO_LATENCY,
AxiIdWidthSlvPorts: ariane_soc::IdWidth,
AxiIdUsedSlvPorts: ariane_soc::IdWidth,
AxiIdWidthSlvPorts: unsigned'(ariane_soc::IdWidth),
AxiIdUsedSlvPorts: unsigned'(ariane_soc::IdWidth),
UniqueIds: 1'b0,
AxiAddrWidth: AXI_ADDRESS_WIDTH,
AxiDataWidth: AXI_DATA_WIDTH,
NoAddrRules: ariane_soc::NB_PERIPHERALS
AxiAddrWidth: unsigned'(AXI_ADDRESS_WIDTH),
AxiDataWidth: unsigned'(AXI_DATA_WIDTH),
NoAddrRules: unsigned'(ariane_soc::NB_PERIPHERALS)
};
axi_xbar_intf #(

36
docs/05_cva6_apu/cva6_testharness.md
View file

@ -2,7 +2,7 @@
`ariane_testharness` is the module where all the masters and slaves have been connected with the axi crossbar.There are two masters and ten slaves in this module.Their names and interfaces have been mentioned in the table below.
| Slaves | Interfaces | Masters | Interfaces |
| Slaves | Interfaces | Masters | Interfaces |
| ----------- | ----------- | ----------- | ----------- |
| DRAM | master[0] | ariane | slave[0] |
| GPIO | master[1] | debug | slave[1] |
@ -22,15 +22,15 @@
## Ariane
The `ariane` core is instantiated as `i_ariane` in `ariane_testharness` module. It is acting as a master in `ariane_testharness`.
The `ariane` core is instantiated as `i_ariane` in `ariane_testharness` module. It is acting as a master in `ariane_testharness`.
The following is the diagram of the `ariane` module along with its inputs/outputs ports.
![ariane](_static/ariane.png "ariane")
`ipi`, `irq` and `time_irq` are being sent to this module from the `ariane_testharness` module.
`ipi`, `irq` and `time_irq` are being sent to this module from the `ariane_testharness` module.
The AXI request and response signals that are being passed from the `ariane_testharness` to `ariane` module are the following:
> `.axi_req_o ( axi_ariane_req ),`
> `.axi_req_o ( axi_ariane_req ),`
`.axi_resp_i ( axi_ariane_resp )`
In the `ariane_testharness` module, `axi_ariane_req` and `axi_ariane_resp` structs are being linked with the `slave[0]` (AXI_BUS interface) in a way that the information of `axi_ariane_req` is being passed to the `slave[0]` and the information from the `slave[0]` is being passed to the `axi_ariane_resp` struct. The following compiler directives are being used for this purpose.
@ -44,17 +44,17 @@ In the `ariane_testharness` module, `axi_ariane_req` and `axi_ariane_resp` struc
### Master
`axi_adapter` is acting as a master for the debug module.
`axi_adapter` is acting as a master for the debug module.
The following is the diagram of the `axi_adapter` module along with its signals.
![axi_adapter](_static/axi_adapter.png "axi_adapter")
The AXI request and response that signals are being passed from the test_harness module are the following:
The AXI request and response that signals are being passed from the test_harness module are the following:
> `.axi_req_o ( dm_axi_m_req )`
> `.axi_req_o ( dm_axi_m_req )`
`.axi_resp_i ( dm_axi_m_resp )`
`Slave[1]` is the interface of AXI_BUS and it actually acts as a master for axi_protocol.
`Slave[1]` is the interface of AXI_BUS and it actually acts as a master for axi_protocol.
The `dm_axi_m_req` and `dm_axi_m_resp` are being linked with the slave[1] AXI_BUS interface in this way that the requests signals of the `dm_axi_m_req` are being passed to the `slave[1]` and the response signals from the `slave[1]` are being passed to the `dm_axi_m_resp` struct.
@ -63,7 +63,7 @@ The `dm_axi_m_req` and `dm_axi_m_resp` are being linked with the slave[1] AXI_BU
### Slave
This is the memory of debug and `axi2mem` converter is used whenever a read or write request is made to memory by the master.
This is the memory of debug and `axi2mem` converter is used whenever a read or write request is made to memory by the master.
`axi2mem` module simply waits for the ar_valid or aw_valid of the master (actual slave) interface and then passes the req_o, we_o, addr_o, be_o, user_o signals and data_o to the memory and will receive the data_i and user_i from the memory.
![axi2mem](_static/axi2mem.png "axi2mem")
@ -78,7 +78,7 @@ Clint is a slave in this SoC. The signals of the `clint` module are as follows:
![clint](_static/clint.png "clint")
`ipi_o` (inter-processing interrupt) and `timer_irq_o` (timer_interrupt request) are generated from the `clint` module and are the inputs of the ariane core.
`ipi_o` (inter-processing interrupt) and `timer_irq_o` (timer_interrupt request) are generated from the `clint` module and are the inputs of the ariane core.
This module interacts with the axi bus interface through the following assignments:
> `AXI_ASSIGN_TO_REQ(axi_clint_req, master[ariane_soc::CLINT])`
@ -87,7 +87,7 @@ This compiler directive is used to transfer the request signals of the master vi
> `AXI_ASSIGN_FROM_RESP(master[ariane_soc::CLINT], axi_clint_resp)`
This compiler directive is used to assign the response of the slave (in this case `clint` module) from the
This compiler directive is used to assign the response of the slave (in this case `clint` module) from the
`Axi_clint_resp` struct to the interface `master[ariane_soc::CLINT]`.
## Bootrom
@ -105,9 +105,9 @@ The complete sequence through which a request to SRAM is transferred is as follo
![sequence](_static/dram.png)
`dram` and `dram_delayed` are two AXI_BUS interfaces.
The slave modport of AXI_BUS interface for `Master[DRAM]` has been linked with `axi_riscv_atomics` module and the request of the master has been passed to `dram` interface (another instantiation of interface of AXI_BUS). All this is for the exclusive accesses and no burst is supported in this exclusive access.
`dram` and `dram_delayed` interfaces have also been passed to `axi_delayer_intf` module as a slave modport and master modport of the AXI_BUS interface, respectively. The `axi_delayer_intf` module is used to introduce the delay.
`dram_delayed` is also passed to the `axi2mem` module as a slave modport of AXI_BUS interface. `axi2mem` module with `dram_delayed` as an AXI_Bus interface will interact with SRAM.
The slave modport of AXI_BUS interface for `Master[DRAM]` has been linked with `axi_riscv_atomics` module and the request of the master has been passed to `dram` interface (another instantiation of interface of AXI_BUS). All this is for the exclusive accesses and no burst is supported in this exclusive access.
`dram` and `dram_delayed` interfaces have also been passed to `axi_delayer_intf` module as a slave modport and master modport of the AXI_BUS interface, respectively. The `axi_delayer_intf` module is used to introduce the delay.
`dram_delayed` is also passed to the `axi2mem` module as a slave modport of AXI_BUS interface. `axi2mem` module with `dram_delayed` as an AXI_Bus interface will interact with SRAM.
SRAM is a word addressable memory with the signals as follows:
![sram](_static/sram.png "sram")
@ -118,8 +118,8 @@ GPIO is not implemented, error slave has been added in place of it.
## UART
There are two signals for the `apb_uart` module in the `ariane_testharness`, namely `tx` and `rx` for transmitting and receiving the data.
`axi2apb_64_32`, module has been used to convert the axi protocol five channel signals to a single channel apb signals. The `axi2apb_64_32` module has been used between AXI_BUS and `apb_uart module`.
There are two signals for the `apb_uart` module in the `ariane_testharness`, namely `tx` and `rx` for transmitting and receiving the data.
`axi2apb_64_32`, module has been used to convert the axi protocol five channel signals to a single channel apb signals. The `axi2apb_64_32` module has been used between AXI_BUS and `apb_uart module`.
The signals of the `apb_uart` module have been shown in the diagram below:
![apb_uart](_static/apb_uart.png "apb_uart")
@ -132,8 +132,8 @@ PLIC is a slave in this SoC. The hiearchy through which the request is propagate
![plic_hierarchy](_static/plic.png )
`axi2apb_64_32` has been used to convert all the plic axi signals into apb signals.
apb_to_reg is used to assign the apb signals to the `reg_bus` interface which basically communicates with the `plic_top` module. In `apb_to_reg` module, the logical `AND` of `psel` and `penable` signals of apb makes the `valid` signal of `reg_bus` interface.
`axi2apb_64_32` has been used to convert all the plic axi signals into apb signals.
apb_to_reg is used to assign the apb signals to the `reg_bus` interface which basically communicates with the `plic_top` module. In `apb_to_reg` module, the logical `AND` of `psel` and `penable` signals of apb makes the `valid` signal of `reg_bus` interface.
The signals of the `plic_top` have been shown below:
![plic_top](_static/plic_top.png "plic_top")

19
verilator_config.vlt Normal file
View file

@ -0,0 +1,19 @@
// Copyright OpenHW contributors
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// common waiver rules for verilator
`verilator_config
// TODO -> Please update the configuration file according to the warnings resolution
// Timing flag issue CVA6 #1162, waiving it off
lint_off -rule STMTDLY
// Big Endian usage issue CVA6 #1176, waiving it off
lint_off -rule LITENDIAN
// New Line at the end of file in submodule register_interface, waiving it off
// Commenting this out since CI Verilator does not recognize this rule
// lint_off -rule EOFNEWLINE -file "corev_apu/*.svh"
// lint_off -file "corev_apu/*.svh"