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LINT: Initial changes for Lint warnings removal (#1158)

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Umer Imran 2023-04-24 11:22:56 +05:00 • committed by GitHub
parent 9668e0fd78
commit 45259cfb6a
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18 changed files with 207 additions and 183 deletions
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21
Makefile
View file

@ -86,6 +86,7 @@ endif
# target takes one of the following cva6 hardware configuration:
# cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv32a6_ima_sv32_fpga
# Changing the default target to cv32a60x for Step1 verification
target ?= cv64a6_imafdc_sv39
ifndef TARGET_CFG
export TARGET_CFG = $(target)
@ -138,8 +139,7 @@ endif
# this list contains the standalone components
src := core/include/$(target)_config_pkg.sv \
corev_apu/tb/ariane.sv \
src := corev_apu/tb/ariane.sv \
$(wildcard corev_apu/bootrom/*.sv) \
$(wildcard corev_apu/clint/*.sv) \
$(wildcard corev_apu/fpga/src/axi2apb/src/*.sv) \
@ -163,9 +163,6 @@ src := core/include/$(target)_config_pkg.sv
vendor/pulp-platform/axi/src/axi_multicut.sv \
vendor/pulp-platform/common_cells/src/rstgen_bypass.sv \
vendor/pulp-platform/common_cells/src/rstgen.sv \
vendor/pulp-platform/common_cells/src/stream_mux.sv \
vendor/pulp-platform/common_cells/src/stream_demux.sv \
vendor/pulp-platform/common_cells/src/exp_backoff.sv \
vendor/pulp-platform/common_cells/src/addr_decode.sv \
vendor/pulp-platform/common_cells/src/stream_register.sv \
vendor/pulp-platform/axi/src/axi_cut.sv \
@ -181,8 +178,6 @@ src := core/include/$(target)_config_pkg.sv
vendor/pulp-platform/common_cells/src/cdc_2phase.sv \
vendor/pulp-platform/common_cells/src/spill_register_flushable.sv \
vendor/pulp-platform/common_cells/src/spill_register.sv \
vendor/pulp-platform/common_cells/src/stream_arbiter.sv \
vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv \
vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv \
vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv \
vendor/pulp-platform/common_cells/src/stream_delay.sv \
@ -197,13 +192,6 @@ src := core/include/$(target)_config_pkg.sv
corev_apu/tb/common/SimDTM.sv \
corev_apu/tb/common/SimJTAG.sv
# SV32 MMU for CV32, SV39 MMU for CV64
ifeq ($(findstring 32, $(target)),32)
src += $(wildcard core/mmu_sv32/*.sv)
else
src += $(wildcard core/mmu_sv39/*.sv)
endif
src := $(addprefix $(root-dir), $(src))
copro_src := core/cvxif_example/include/cvxif_instr_pkg.sv \
@ -538,7 +526,7 @@ xrun-check-benchmarks:
xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchmarks
# verilator-specific
verilate_command := $(verilator) \
verilate_command := $(verilator) verilator_config.vlt \
-f core/Flist.cva6 \
$(filter-out %.vhd, $(ariane_pkg)) \
$(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
@ -547,6 +535,7 @@ verilate_command := $(verilator)
+incdir+corev_apu/axi_node \
$(if $(verilator_threads), --threads $(verilator_threads)) \
--unroll-count 256 \
-Wall \
-Werror-PINMISSING \
-Werror-IMPLICIT \
-Wno-fatal \
@ -565,7 +554,7 @@ verilate_command := $(verilator)
$(if $(TRACE_FAST), --trace $(VERILATOR_ROOT)/include/verilated_vcd_c.cpp,) \
-LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -L../corev_apu/tb/dromajo/src -ldromajo_cosim,) -lpthread $(if $(TRACE_COMPACT), -lz,)" \
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -DDROMAJO=1,) -DVL_DEBUG" \
-Wall --cc --vpi \
--cc --vpi \
$(list_incdir) --top-module ariane_testharness \
--threads-dpi none \
--Mdir $(ver-library) -O3 \

2
common/local/util/sram.sv
View file

@ -114,7 +114,7 @@ end
.addr_i ( addr_i ),
.rdata_o ( rdata_aligned[k*64 +: 64] )
);
if (USER_EN) begin : gen_mem_user
if (USER_EN > 0) begin : gen_mem_user
tc_sram_wrapper #(
.NumWords(NUM_WORDS), // Number of Words in data array
.DataWidth(64), // Data signal width

2
core/cache_subsystem/axi_adapter.sv
View file

@ -395,6 +395,8 @@ module axi_adapter #(
state_d = IDLE;
id_o = id_q;
end
default: state_d = IDLE;
endcase
end

2
core/cache_subsystem/wt_axi_adapter.sv
View file

@ -248,8 +248,10 @@ module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
AMO_MAXU: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX};
AMO_MIN: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN};
AMO_MINU: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN};
default: ; // Do nothing
endcase
end
default: ; // Do nothing
//////////////////////////////////////
endcase
end

4
core/cache_subsystem/wt_dcache_missunit.sv
View file

@ -302,7 +302,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
end
end
DCACHE_STORE_ACK: begin
if (stores_inflight_q) begin
if (stores_inflight_q>0) begin
store_ack = 1'b1;
miss_rtrn_vld_o[NumPorts-1] = 1'b1;
end
@ -313,7 +313,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
// need to set SC backoff counter if
// this op failed
if (amo_req_i.amo_op == AMO_SC) begin
if (amo_resp_o.result) begin
if (amo_resp_o.result>0) begin
sc_fail = 1'b1;
end else begin
sc_pass = 1'b1;

1
core/cva6.sv
View file

@ -947,6 +947,7 @@ module cva6 import ariane_pkg::*; #(
riscv::PRIV_LVL_M: mode = "M";
riscv::PRIV_LVL_S: mode = "S";
riscv::PRIV_LVL_U: mode = "U";
default: ; // Do nothing
endcase
end
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin

17
core/fpu_wrap.sv
View file

@ -51,7 +51,7 @@ module fpu_wrap import ariane_pkg::*; (
// Features (enabled formats, vectors etc.)
localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
Width: riscv::XLEN, // parameterized using XLEN
Width: unsigned'(riscv::XLEN), // parameterized using XLEN
EnableVectors: ariane_pkg::XFVEC,
EnableNanBox: 1'b1,
FpFmtMask: {RVF, RVD, XF16, XF8, XF16ALT},
@ -61,10 +61,14 @@ module fpu_wrap import ariane_pkg::*; (
// Implementation (number of registers etc)
localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
PipeRegs: '{// FP32, FP64, FP16, FP8, FP16alt
'{LAT_COMP_FP32, LAT_COMP_FP64, LAT_COMP_FP16, LAT_COMP_FP8, LAT_COMP_FP16ALT}, // ADDMUL
'{default: LAT_DIVSQRT}, // DIVSQRT
'{default: LAT_NONCOMP}, // NONCOMP
'{default: LAT_CONV}}, // CONV
'{unsigned'(LAT_COMP_FP32 ),
unsigned'(LAT_COMP_FP64 ),
unsigned'(LAT_COMP_FP16 ),
unsigned'(LAT_COMP_FP8 ),
unsigned'(LAT_COMP_FP16ALT)}, // ADDMUL
'{default: unsigned'(LAT_DIVSQRT)}, // DIVSQRT
'{default: unsigned'(LAT_NONCOMP)}, // NONCOMP
'{default: unsigned'(LAT_CONV)}}, // CONV
UnitTypes: '{'{default: fpnew_pkg::PARALLEL}, // ADDMUL
'{default: fpnew_pkg::MERGED}, // DIVSQRT
'{default: fpnew_pkg::PARALLEL}, // NONCOMP
@ -253,6 +257,7 @@ module fpu_wrap import ariane_pkg::*; (
3'b010: fpu_srcfmt_d = fpnew_pkg::FP16;
3'b110: fpu_srcfmt_d = fpnew_pkg::FP16ALT;
3'b011: fpu_srcfmt_d = fpnew_pkg::FP8;
default: ; // Do nothing
endcase
end
end
@ -392,6 +397,7 @@ module fpu_wrap import ariane_pkg::*; (
fpnew_pkg::FP16,
fpnew_pkg::FP16ALT: operand_c_d = RVD ? {4{operand_c_i[15:0]}} : {2{operand_c_i[15:0]}};
fpnew_pkg::FP8: operand_c_d = RVD ? {8{operand_c_i[7:0]}} : {4{operand_c_i[7:0]}};
default: ; // Do nothing
endcase // fpu_dstfmt_d
end else begin
unique case (fpu_dstfmt_d)
@ -399,6 +405,7 @@ module fpu_wrap import ariane_pkg::*; (
fpnew_pkg::FP16,
fpnew_pkg::FP16ALT: operand_b_d = RVD ? {4{operand_b_i[15:0]}} : {2{operand_b_i[15:0]}};
fpnew_pkg::FP8: operand_b_d = RVD ? {8{operand_b_i[7:0]}} : {4{operand_b_i[7:0]}};
default: ; // Do nothing
endcase // fpu_dstfmt_d
end
end

50
core/include/ariane_pkg.sv
View file

@ -55,27 +55,27 @@ package ariane_pkg;
} ariane_cfg_t;
localparam ariane_cfg_t ArianeDefaultConfig = '{
RASDepth: cva6_config_pkg::CVA6ConfigRASDepth,
BTBEntries: cva6_config_pkg::CVA6ConfigBTBEntries,
BHTEntries: cva6_config_pkg::CVA6ConfigBHTEntries,
RASDepth: int'(cva6_config_pkg::CVA6ConfigRASDepth),
BTBEntries: int'(cva6_config_pkg::CVA6ConfigBTBEntries),
BHTEntries: int'(cva6_config_pkg::CVA6ConfigBHTEntries),
// idempotent region
NrNonIdempotentRules: 2,
NonIdempotentAddrBase: {64'b0, 64'b0},
NonIdempotentLength: {64'b0, 64'b0},
NrExecuteRegionRules: 3,
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: {64'h8000_0000, 64'h1_0000, 64'h0},
ExecuteRegionLength: {64'h40000000, 64'h10000, 64'h1000},
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: 1,
CachedRegionAddrBase: {64'h8000_0000},
CachedRegionLength: {64'h40000000},
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000}),
// cache config
AxiCompliant: 1'b1,
SwapEndianess: 1'b0,
// debug
DmBaseAddress: 64'h0,
NrPMPEntries: cva6_config_pkg::CVA6ConfigNrPMPEntries
NrPMPEntries: unsigned'(cva6_config_pkg::CVA6ConfigNrPMPEntries)
};
// Function being called to check parameters
@ -206,16 +206,16 @@ package ariane_pkg;
localparam riscv::xlen_t OPENHWGROUP_MVENDORID = {{riscv::XLEN-32{1'b0}}, 32'h0602};
localparam riscv::xlen_t ARIANE_MARCHID = {{riscv::XLEN-32{1'b0}}, 32'd3};
localparam riscv::xlen_t ISA_CODE = (RVA << 0) // A - Atomic Instructions extension
| (RVC << 2) // C - Compressed extension
| (RVD << 3) // D - Double precsision floating-point extension
| (RVF << 5) // F - Single precsision floating-point extension
| (1 << 8) // I - RV32I/64I/128I base ISA
| (1 << 12) // M - Integer Multiply/Divide extension
| (0 << 13) // N - User level interrupts supported
| (1 << 18) // S - Supervisor mode implemented
| (1 << 20) // U - User mode implemented
| (NSX << 23) // X - Non-standard extensions present
localparam riscv::xlen_t ISA_CODE = (riscv::XLEN'(RVA) << 0) // A - Atomic Instructions extension
| (riscv::XLEN'(RVC) << 2) // C - Compressed extension
| (riscv::XLEN'(RVD) << 3) // D - Double precsision floating-point extension
| (riscv::XLEN'(RVF) << 5) // F - Single precsision floating-point extension
| (riscv::XLEN'(1 ) << 8) // I - RV32I/64I/128I base ISA
| (riscv::XLEN'(1 ) << 12) // M - Integer Multiply/Divide extension
| (riscv::XLEN'(0 ) << 13) // N - User level interrupts supported
| (riscv::XLEN'(1 ) << 18) // S - Supervisor mode implemented
| (riscv::XLEN'(1 ) << 20) // U - User mode implemented
| (riscv::XLEN'(NSX) << 23) // X - Non-standard extensions present
| ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN-2); // MXL
// 32 registers + 1 bit for re-naming = 6
@ -888,6 +888,7 @@ package ariane_pkg;
3'b010: return 8'b0011_1100;
3'b011: return 8'b0111_1000;
3'b100: return 8'b1111_0000;
default: ; // Do nothing
endcase
end
2'b01: begin
@ -899,6 +900,7 @@ package ariane_pkg;
3'b100: return 8'b0011_0000;
3'b101: return 8'b0110_0000;
3'b110: return 8'b1100_0000;
default: ; // Do nothing
endcase
end
2'b00: begin
@ -927,7 +929,7 @@ package ariane_pkg;
2'b00: return 4'b0011;
2'b01: return 4'b0110;
2'b10: return 4'b1100;
default: ; // Do nothing
endcase
end
2'b00: begin

12
core/include/riscv_pkg.sv
View file

@ -333,12 +333,12 @@ package riscv;
localparam logic [XLEN-1:0] MIP_SEIP = 1 << IRQ_S_EXT;
localparam logic [XLEN-1:0] MIP_MEIP = 1 << IRQ_M_EXT;
localparam logic [XLEN-1:0] S_SW_INTERRUPT = (1 << (XLEN-1)) | IRQ_S_SOFT;
localparam logic [XLEN-1:0] M_SW_INTERRUPT = (1 << (XLEN-1)) | IRQ_M_SOFT;
localparam logic [XLEN-1:0] S_TIMER_INTERRUPT = (1 << (XLEN-1)) | IRQ_S_TIMER;
localparam logic [XLEN-1:0] M_TIMER_INTERRUPT = (1 << (XLEN-1)) | IRQ_M_TIMER;
localparam logic [XLEN-1:0] S_EXT_INTERRUPT = (1 << (XLEN-1)) | IRQ_S_EXT;
localparam logic [XLEN-1:0] M_EXT_INTERRUPT = (1 << (XLEN-1)) | IRQ_M_EXT;
localparam logic [XLEN-1:0] S_SW_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_S_SOFT);
localparam logic [XLEN-1:0] M_SW_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_M_SOFT);
localparam logic [XLEN-1:0] S_TIMER_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_S_TIMER);
localparam logic [XLEN-1:0] M_TIMER_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_M_TIMER);
localparam logic [XLEN-1:0] S_EXT_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_S_EXT);
localparam logic [XLEN-1:0] M_EXT_INTERRUPT = (1 << (XLEN-1)) | XLEN'(IRQ_M_EXT);
// -----
// CSRs

2
core/load_unit.sv
View file

@ -241,6 +241,8 @@ module load_unit import ariane_pkg::*; #(
// we've killed the current request so we can go back to idle
state_d = IDLE;
end
default: state_d = IDLE;
endcase
// we got an exception

26
corev_apu/tb/ariane_soc_pkg.sv
View file

@ -70,26 +70,26 @@ package ariane_soc;
localparam logic [NrRegion-1:0][NB_PERIPHERALS-1:0] ValidRule = {{NrRegion * NB_PERIPHERALS}{1'b1}};
localparam ariane_pkg::ariane_cfg_t ArianeSocCfg = '{
RASDepth: cva6_config_pkg::CVA6ConfigRASDepth,
BTBEntries: cva6_config_pkg::CVA6ConfigBTBEntries,
BHTEntries: cva6_config_pkg::CVA6ConfigBHTEntries,
RASDepth: int'(cva6_config_pkg::CVA6ConfigRASDepth),
BTBEntries: int'(cva6_config_pkg::CVA6ConfigBTBEntries),
BHTEntries: int'(cva6_config_pkg::CVA6ConfigBHTEntries),
// idempotent region
NrNonIdempotentRules: 1,
NonIdempotentAddrBase: {64'b0},
NonIdempotentLength: {DRAMBase},
NrExecuteRegionRules: 3,
ExecuteRegionAddrBase: {DRAMBase, ROMBase, DebugBase},
ExecuteRegionLength: {DRAMLength, ROMLength, DebugLength},
NrNonIdempotentRules: unsigned'(1),
NonIdempotentAddrBase: 1024'({64'b0}),
NonIdempotentLength: 1024'({DRAMBase}),
NrExecuteRegionRules: unsigned'(3),
ExecuteRegionAddrBase: 1024'({DRAMBase, ROMBase, DebugBase}),
ExecuteRegionLength: 1024'({DRAMLength, ROMLength, DebugLength}),
// cached region
NrCachedRegionRules: 1,
CachedRegionAddrBase: {DRAMBase},
CachedRegionLength: {DRAMLength},
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({DRAMBase}),
CachedRegionLength: 1024'({DRAMLength}),
// cache config
AxiCompliant: 1'b1,
SwapEndianess: 1'b0,
// debug
DmBaseAddress: DebugBase,
NrPMPEntries: cva6_config_pkg::CVA6ConfigNrPMPEntries
NrPMPEntries: unsigned'(cva6_config_pkg::CVA6ConfigNrPMPEntries)
};
endpackage

18
corev_apu/tb/ariane_testharness.sv
View file

@ -503,18 +503,18 @@ module ariane_testharness #(
};
localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{
NoSlvPorts: ariane_soc::NrSlaves,
NoMstPorts: ariane_soc::NB_PERIPHERALS,
MaxMstTrans: 1, // Probably requires update
MaxSlvTrans: 1, // Probably requires update
NoSlvPorts: unsigned'(ariane_soc::NrSlaves),
NoMstPorts: unsigned'(ariane_soc::NB_PERIPHERALS),
MaxMstTrans: unsigned'(1), // Probably requires update
MaxSlvTrans: unsigned'(1), // Probably requires update
FallThrough: 1'b0,
LatencyMode: axi_pkg::NO_LATENCY,
AxiIdWidthSlvPorts: ariane_soc::IdWidth,
AxiIdUsedSlvPorts: ariane_soc::IdWidth,
AxiIdWidthSlvPorts: unsigned'(ariane_soc::IdWidth),
AxiIdUsedSlvPorts: unsigned'(ariane_soc::IdWidth),
UniqueIds: 1'b0,
AxiAddrWidth: AXI_ADDRESS_WIDTH,
AxiDataWidth: AXI_DATA_WIDTH,
NoAddrRules: ariane_soc::NB_PERIPHERALS
AxiAddrWidth: unsigned'(AXI_ADDRESS_WIDTH),
AxiDataWidth: unsigned'(AXI_DATA_WIDTH),
NoAddrRules: unsigned'(ariane_soc::NB_PERIPHERALS)
};
axi_xbar_intf #(

19
verilator_config.vlt Normal file
View file

@ -0,0 +1,19 @@
// Copyright OpenHW contributors
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// common waiver rules for verilator
`verilator_config
// TODO -> Please update the configuration file according to the warnings resolution
// Timing flag issue CVA6 #1162, waiving it off
lint_off -rule STMTDLY
// Big Endian usage issue CVA6 #1176, waiving it off
lint_off -rule LITENDIAN
// New Line at the end of file in submodule register_interface, waiving it off
// Commenting this out since CI Verilator does not recognize this rule
// lint_off -rule EOFNEWLINE -file "corev_apu/*.svh"
// lint_off -file "corev_apu/*.svh"