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Small pre-release clean-up

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This commit is contained in:
Florian Zaruba 2018-11-23 11:37:14 +01:00
parent fe67f5d60c
commit 4558960b88
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21 changed files with 2546 additions and 96 deletions
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1
Makefile
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@ -96,6 +96,7 @@ src := $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv)) \
src/common_cells/src/deprecated/pulp_sync.sv \
src/common_cells/src/deprecated/find_first_one.sv \
src/common_cells/src/rstgen_bypass.sv \
src/common_cells/src/rstgen.sv \
src/common_cells/src/stream_mux.sv \
src/common_cells/src/stream_demux.sv \
src/util/axi_connect.sv \

50
README.md
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@ -8,6 +8,24 @@ It has configurable size, separate TLBs, a hardware PTW and branch-prediction (b
![](docs/img/ariane_overview.png)
Table of Contents
=================
* [Ariane RISC-V CPU](#ariane-risc-v-cpu)
* [Getting Started](#getting-started)
* [Running User-Space Applications](#running-user-space-applications)
* [FPU Support](#fpu-support)
* [FPGA Emulation](#fpga-emulation)
* [Generating a Bistream](#generating-a-bistream)
* [Debugging](#debugging)
* [Planned Improvements](#planned-improvements)
* [Going Beyond](#going-beyond)
* [CI Testsuites and Randomized Constrained Testing with Torture](#ci-testsuites-and-randomized-constrained-testing-with-torture)
* [Re-generating the Bootcode (ZSBL)](#re-generating-the-bootcode-zsbl)
* [Contributing](#contributing)
* [Acknowledgements](#acknowledgements)
## Getting Started
@ -87,20 +105,44 @@ $ make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf b
## FPGA Emulation
We currently only provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual). Tested on Vivado 2018.2.
We currently only provide support for the [Genesys 2 board](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/reference-manual). Tested on Vivado 2018.2. The FPGA SoC currently contains the following peripherals:
- DDR3 memory controller
- SPI controller to conncet to an SDCard
- Ethernet controller
- JTAG port (see debugging section below)
- Bootrom containing zero stage bootloader and device tree.
![](docs/img/fpga_bd.png)
> The Ethernet controller and the corresponding network connection is still work in progress and not functional at the moment.
### Generating a Bistream
To generate the FPGA bitstream run:
```
$ source fpga/sourceme.sh
$ make fpga
```
TODO(zarubaf): Add further TODOS and simplify flow
This will produce a bitstream file and memory configuration file (in `fpga/work-fpga`) which you can permanently flash by:
Default baudrate is `115200`:
- Open Vivado
- Open the hardware manager and open the target board (Genesys II - `xc7k325t`)
- Tools - Add Configuration Memory Device
- Select the following Spansion SPI flash `s25fl256xxxxxx0`
- Add `ariane_xilinx.mcs`
- Press Ok. Flashing will take a couple of minutes.
- Right click on the FPGA device - Boot from Configuration Memory Device
Connect a terminal to the USB serial device opened by the FTDI chip e.g.:
```
$ screen /dev/ttyUSB0 115200
```
Default baudrate set by the bootlaoder and Linux is `115200`.
### Debugging
You can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD, both to be used with Olimex Debug adapter. The JTAG port ist mapped to PMOD `JC` on the Gensys 2 board. You will need to connect the following wires to your debug adapter:
@ -173,6 +215,8 @@ If you are on an Ubuntu based system you need to add the following udev rule to
## Planned Improvements
Check-out the issue tab which also loosely tracks planned improvements.
> Atomics are implemented for a single core environment. They will semantically fail in a multi-core setup.
## Going Beyond

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bootrom/.gitignore vendored
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@ -1 +1,3 @@
*.elf
*.img
*.dtb

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33
fpga/Makefile
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@ -1,10 +1,33 @@
all:
vivado-2018.2 vivado -mode batch -source scripts/run.tcl
VIVADO ?= vivado
VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
# ips: mig
work-dir := work-fpga
bit := $(work-dir)/ariane_xilinx.bit
mcs := $(work-dir)/ariane_xilinx.mcs
ips := xlnx_axi_clock_converter \
xlnx_axi_dwidth_converter \
xlnx_axi_quad_spi \
xlnx_clk_gen \
xlnx_mig_7_ddr
all: $(mcs)
# Generate mcs from bitstream
$(mcs): $(bit)
$(VIVADO) $(VIVADOFLAGS) -source scripts/write_cfgmem.tcl -tclargs $@ $^
$(bit):
mkdir -p $(work-dir)
$(VIVADO) $(VIVADOFLAGS) -source scripts/run.tcl
cp ariane.runs/impl_1/ariane_xilinx.bit ./$(work-dir)
$(ips):
cd xilinx/$@; make clean; make
mcs: $(mcs)
clean:
rm -rf *.log *.jou *.str
rm -rf *.log *.jou *.str $(work-dir)
.PHONY:
clean
clean

3
fpga/constraints/genesys-2.xdc
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@ -69,3 +69,6 @@ set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS33} [get_ports spi_clk_o_2]
set_property -dict {PACKAGE_PIN U28 IOSTANDARD LVCMOS33} [get_ports spi_ss_2]
set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVCMOS33} [get_ports spi_miso_2]
set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports spi_mosi_2]
# Genesys 2 has a quad SPI flash
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

25
fpga/scripts/prologue.tcl Normal file
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@ -0,0 +1,25 @@
# Copyright 2018 ETH Zurich and University of Bologna.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
set project ariane
create_project $project . -force -part $::env(XILINX_PART)
set_property board_part $::env(XILINX_BOARD) [current_project]
# set number of threads to 8 (maximum, unfortunately)
set_param general.maxThreads 8
set_msg_config -id {[Synth 8-5858]} -new_severity "info"

10
fpga/scripts/run.tcl
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@ -14,16 +14,6 @@
# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
set project ariane
create_project $project . -force -part $::env(XILINX_PART)
set_property board_part $::env(XILINX_BOARD) [current_project]
# set number of threads to 8 (maximum, unfortunately)
set_param general.maxThreads 8
set_msg_config -id {[Synth 8-5858]} -new_severity "info"
# hard-coded to Genesys 2 for the moment
add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc

7
fpga/scripts/write_cfgmem.tcl
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@ -15,6 +15,13 @@
# Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
# Description: Generate a memory configuration file from a bitstream (Genesys II only right now)
if {$argc < 2 || $argc > 4} {
puts $argc
puts {Error: Invalid number of arguments}
puts {Usage: write_cfgmem.tcl mcsfile bitfile [datafile]}
exit 1
}
lassign $argv mcsfile bitfile
# https://scholar.princeton.edu/jbalkind/blog/programming-genesys-2-qspi-spi-x4-flash

191
fpga/src/ariane_peripherals_xilinx.sv
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@ -23,6 +23,7 @@ module ariane_peripherals #(
AXI_BUS.in plic ,
AXI_BUS.in uart ,
AXI_BUS.in spi ,
input logic eth_clk_i ,
AXI_BUS.in ethernet ,
output logic [1:0] irq_o ,
// UART
@ -481,7 +482,18 @@ module ariane_peripherals #(
assign ethernet.r_user = 1'b0;
if (InclEthernet) begin : gen_ethernet
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) axi_ethernet_cdc();
wire mdio_i, mdio_o, mdio_t;
logic eth_rst_n;
logic [31:0] s_axi_eth_awaddr;
logic [7:0] s_axi_eth_awlen;
logic [2:0] s_axi_eth_awsize;
@ -509,50 +521,143 @@ module ariane_peripherals #(
logic s_axi_eth_rlast;
logic s_axi_eth_rvalid;
rstgen i_rstgen (
.clk_i ( eth_clk_i ),
.rst_ni ( rst_ni ),
.test_mode_i ( test_en ),
.rst_no ( eth_rst_n ),
.init_no ( ) // keep open
);
xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ethernet (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.s_axi_awid ( ethernet.aw_id ),
.s_axi_awaddr ( ethernet.aw_addr ),
.s_axi_awlen ( ethernet.aw_len ),
.s_axi_awsize ( ethernet.aw_size ),
.s_axi_awburst ( ethernet.aw_burst ),
.s_axi_awlock ( ethernet.aw_lock ),
.s_axi_awcache ( ethernet.aw_cache ),
.s_axi_awprot ( ethernet.aw_prot ),
.s_axi_awregion ( ethernet.aw_region ),
.s_axi_awqos ( ethernet.aw_qos ),
.s_axi_awvalid ( ethernet.aw_valid ),
.s_axi_awready ( ethernet.aw_ready ),
.s_axi_wdata ( ethernet.w_data ),
.s_axi_wstrb ( ethernet.w_strb ),
.s_axi_wlast ( ethernet.w_last ),
.s_axi_wvalid ( ethernet.w_valid ),
.s_axi_wready ( ethernet.w_ready ),
.s_axi_bid ( ethernet.b_id ),
.s_axi_bresp ( ethernet.b_resp ),
.s_axi_bvalid ( ethernet.b_valid ),
.s_axi_bready ( ethernet.b_ready ),
.s_axi_arid ( ethernet.ar_id ),
.s_axi_araddr ( ethernet.ar_addr ),
.s_axi_arlen ( ethernet.ar_len ),
.s_axi_arsize ( ethernet.ar_size ),
.s_axi_arburst ( ethernet.ar_burst ),
.s_axi_arlock ( ethernet.ar_lock ),
.s_axi_arcache ( ethernet.ar_cache ),
.s_axi_arprot ( ethernet.ar_prot ),
.s_axi_arregion ( ethernet.ar_region ),
.s_axi_arqos ( ethernet.ar_qos ),
.s_axi_arvalid ( ethernet.ar_valid ),
.s_axi_arready ( ethernet.ar_ready ),
.s_axi_rid ( ethernet.r_id ),
.s_axi_rdata ( ethernet.r_data ),
.s_axi_rresp ( ethernet.r_resp ),
.s_axi_rlast ( ethernet.r_last ),
.s_axi_rvalid ( ethernet.r_valid ),
.s_axi_rready ( ethernet.r_ready ),
// to size converter
.m_axi_aclk ( eth_clk_i ),
.m_axi_aresetn ( eth_rst_n ),
.m_axi_awid ( axi_ethernet_cdc.aw_id ),
.m_axi_awaddr ( axi_ethernet_cdc.aw_addr ),
.m_axi_awlen ( axi_ethernet_cdc.aw_len ),
.m_axi_awsize ( axi_ethernet_cdc.aw_size ),
.m_axi_awburst ( axi_ethernet_cdc.aw_burst ),
.m_axi_awlock ( axi_ethernet_cdc.aw_lock ),
.m_axi_awcache ( axi_ethernet_cdc.aw_cache ),
.m_axi_awprot ( axi_ethernet_cdc.aw_prot ),
.m_axi_awregion ( axi_ethernet_cdc.aw_region ),
.m_axi_awqos ( axi_ethernet_cdc.aw_qos ),
.m_axi_awvalid ( axi_ethernet_cdc.aw_valid ),
.m_axi_awready ( axi_ethernet_cdc.aw_ready ),
.m_axi_wdata ( axi_ethernet_cdc.w_data ),
.m_axi_wstrb ( axi_ethernet_cdc.w_strb ),
.m_axi_wlast ( axi_ethernet_cdc.w_last ),
.m_axi_wvalid ( axi_ethernet_cdc.w_valid ),
.m_axi_wready ( axi_ethernet_cdc.w_ready ),
.m_axi_bid ( axi_ethernet_cdc.b_id ),
.m_axi_bresp ( axi_ethernet_cdc.b_resp ),
.m_axi_bvalid ( axi_ethernet_cdc.b_valid ),
.m_axi_bready ( axi_ethernet_cdc.b_ready ),
.m_axi_arid ( axi_ethernet_cdc.ar_id ),
.m_axi_araddr ( axi_ethernet_cdc.ar_addr ),
.m_axi_arlen ( axi_ethernet_cdc.ar_len ),
.m_axi_arsize ( axi_ethernet_cdc.ar_size ),
.m_axi_arburst ( axi_ethernet_cdc.ar_burst ),
.m_axi_arlock ( axi_ethernet_cdc.ar_lock ),
.m_axi_arcache ( axi_ethernet_cdc.ar_cache ),
.m_axi_arprot ( axi_ethernet_cdc.ar_prot ),
.m_axi_arregion ( axi_ethernet_cdc.ar_region ),
.m_axi_arqos ( axi_ethernet_cdc.ar_qos ),
.m_axi_arvalid ( axi_ethernet_cdc.ar_valid ),
.m_axi_arready ( axi_ethernet_cdc.ar_ready ),
.m_axi_rid ( axi_ethernet_cdc.r_id ),
.m_axi_rdata ( axi_ethernet_cdc.r_data ),
.m_axi_rresp ( axi_ethernet_cdc.r_resp ),
.m_axi_rlast ( axi_ethernet_cdc.r_last ),
.m_axi_rvalid ( axi_ethernet_cdc.r_valid ),
.m_axi_rready ( axi_ethernet_cdc.r_ready )
);
// system-bus is 64-bit, convert down to 32 bit
xlnx_axi_dwidth_converter i_xlnx_axi_dwidth_converter_ethernet (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.s_axi_awid ( ethernet.aw_id ),
.s_axi_awaddr ( ethernet.aw_addr[31:0] ),
.s_axi_awlen ( ethernet.aw_len ),
.s_axi_awsize ( ethernet.aw_size ),
.s_axi_awburst ( ethernet.aw_burst ),
.s_axi_awlock ( ethernet.aw_lock ),
.s_axi_awcache ( ethernet.aw_cache ),
.s_axi_awprot ( ethernet.aw_prot ),
.s_axi_awregion ( ethernet.aw_region ),
.s_axi_awqos ( ethernet.aw_qos ),
.s_axi_awvalid ( ethernet.aw_valid ),
.s_axi_awready ( ethernet.aw_ready ),
.s_axi_wdata ( ethernet.w_data ),
.s_axi_wstrb ( ethernet.w_strb ),
.s_axi_wlast ( ethernet.w_last ),
.s_axi_wvalid ( ethernet.w_valid ),
.s_axi_wready ( ethernet.w_ready ),
.s_axi_bid ( ethernet.b_id ),
.s_axi_bresp ( ethernet.b_resp ),
.s_axi_bvalid ( ethernet.b_valid ),
.s_axi_bready ( ethernet.b_ready ),
.s_axi_arid ( ethernet.ar_id ),
.s_axi_araddr ( ethernet.ar_addr[31:0] ),
.s_axi_arlen ( ethernet.ar_len ),
.s_axi_arsize ( ethernet.ar_size ),
.s_axi_arburst ( ethernet.ar_burst ),
.s_axi_arlock ( ethernet.ar_lock ),
.s_axi_arcache ( ethernet.ar_cache ),
.s_axi_arprot ( ethernet.ar_prot ),
.s_axi_arregion ( ethernet.ar_region ),
.s_axi_arqos ( ethernet.ar_qos ),
.s_axi_arvalid ( ethernet.ar_valid ),
.s_axi_arready ( ethernet.ar_ready ),
.s_axi_rid ( ethernet.r_id ),
.s_axi_rdata ( ethernet.r_data ),
.s_axi_rresp ( ethernet.r_resp ),
.s_axi_rlast ( ethernet.r_last ),
.s_axi_rvalid ( ethernet.r_valid ),
.s_axi_rready ( ethernet.r_ready ),
.s_axi_aclk ( eth_clk_i ),
.s_axi_aresetn ( eth_rst_n ),
.s_axi_awid ( axi_ethernet_cdc.aw_id ),
.s_axi_awaddr ( axi_ethernet_cdc.aw_addr[31:0] ),
.s_axi_awlen ( axi_ethernet_cdc.aw_len ),
.s_axi_awsize ( axi_ethernet_cdc.aw_size ),
.s_axi_awburst ( axi_ethernet_cdc.aw_burst ),
.s_axi_awlock ( axi_ethernet_cdc.aw_lock ),
.s_axi_awcache ( axi_ethernet_cdc.aw_cache ),
.s_axi_awprot ( axi_ethernet_cdc.aw_prot ),
.s_axi_awregion ( axi_ethernet_cdc.aw_region ),
.s_axi_awqos ( axi_ethernet_cdc.aw_qos ),
.s_axi_awvalid ( axi_ethernet_cdc.aw_valid ),
.s_axi_awready ( axi_ethernet_cdc.aw_ready ),
.s_axi_wdata ( axi_ethernet_cdc.w_data ),
.s_axi_wstrb ( axi_ethernet_cdc.w_strb ),
.s_axi_wlast ( axi_ethernet_cdc.w_last ),
.s_axi_wvalid ( axi_ethernet_cdc.w_valid ),
.s_axi_wready ( axi_ethernet_cdc.w_ready ),
.s_axi_bid ( axi_ethernet_cdc.b_id ),
.s_axi_bresp ( axi_ethernet_cdc.b_resp ),
.s_axi_bvalid ( axi_ethernet_cdc.b_valid ),
.s_axi_bready ( axi_ethernet_cdc.b_ready ),
.s_axi_arid ( axi_ethernet_cdc.ar_id ),
.s_axi_araddr ( axi_ethernet_cdc.ar_addr[31:0] ),
.s_axi_arlen ( axi_ethernet_cdc.ar_len ),
.s_axi_arsize ( axi_ethernet_cdc.ar_size ),
.s_axi_arburst ( axi_ethernet_cdc.ar_burst ),
.s_axi_arlock ( axi_ethernet_cdc.ar_lock ),
.s_axi_arcache ( axi_ethernet_cdc.ar_cache ),
.s_axi_arprot ( axi_ethernet_cdc.ar_prot ),
.s_axi_arregion ( axi_ethernet_cdc.ar_region ),
.s_axi_arqos ( axi_ethernet_cdc.ar_qos ),
.s_axi_arvalid ( axi_ethernet_cdc.ar_valid ),
.s_axi_arready ( axi_ethernet_cdc.ar_ready ),
.s_axi_rid ( axi_ethernet_cdc.r_id ),
.s_axi_rdata ( axi_ethernet_cdc.r_data ),
.s_axi_rresp ( axi_ethernet_cdc.r_resp ),
.s_axi_rlast ( axi_ethernet_cdc.r_last ),
.s_axi_rvalid ( axi_ethernet_cdc.r_valid ),
.s_axi_rready ( axi_ethernet_cdc.r_ready ),
.m_axi_awaddr ( s_axi_eth_awaddr ),
.m_axi_awlen ( s_axi_eth_awlen ),
@ -592,8 +697,8 @@ module ariane_peripherals #(
);
xlnx_axi_ethernetlite i_xlnx_axi_ethernetlite (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.s_axi_aclk ( eth_clk_i ),
.s_axi_aresetn ( eth_rst_n ),
.ip2intc_irpt ( irq_sources[2] ),
.s_axi_awaddr ( s_axi_eth_awaddr[12:0] ),
.s_axi_awlen ( s_axi_eth_awlen ),

29
fpga/src/ariane_xilinx.sv
View file

@ -31,7 +31,7 @@ module ariane_xilinx (
output logic [ 0:0] ddr3_cs_n ,
output logic [ 3:0] ddr3_dm ,
output logic [ 0:0] ddr3_odt ,
input wire eth_txck ,
output wire eth_txck ,
input wire eth_rxck ,
input wire eth_rxctl ,
input wire [3:0] eth_rxd ,
@ -126,6 +126,7 @@ logic time_irq;
logic ipi;
logic clk;
logic eth_clk;
logic spi_clk_i;
logic ddr_sync_reset;
logic ddr_clock_out;
@ -142,8 +143,7 @@ logic cpu_reset;
assign cpu_reset = ~cpu_resetn;
`endif
assign rst_n = ~ddr_sync_reset;
assign rst = ddr_sync_reset;
logic pll_locked;
// ROM
logic rom_req;
@ -163,10 +163,20 @@ logic dmactive;
// IRQ
logic [1:0] irq;
assign test_en = 1'b0;
assign ndmreset_n = ~ndmreset ;
logic [NBSlave-1:0] pc_asserted;
rstgen i_rstgen_main (
.clk_i ( clk ),
.rst_ni ( pll_locked & (~ndmreset) ),
.test_mode_i ( test_en ),
.rst_no ( ndmreset_n ),
.init_no ( ) // keep open
);
assign rst_n = ~ddr_sync_reset;
assign rst = ddr_sync_reset;
// ---------------
// AXI Xbar
// ---------------
@ -361,6 +371,7 @@ ariane_peripherals #(
.plic ( master[ariane_soc::PLIC] ),
.uart ( master[ariane_soc::UART] ),
.spi ( master[ariane_soc::SPI] ),
.eth_clk_i ( eth_clk ),
.ethernet ( master[ariane_soc::Ethernet] ),
.irq_o ( irq ),
.rx_i ( rx ),
@ -429,7 +440,7 @@ logic s_axi_rready;
assign master[ariane_soc::DRAM].r_user = '0;
assign master[ariane_soc::DRAM].b_user = '0;
xlnx_axi_clock_converter i_xlnx_axi_clock_converter (
xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ddr (
.s_axi_aclk ( clk ),
.s_axi_aresetn ( ndmreset_n ),
.s_axi_awid ( master[ariane_soc::DRAM].aw_id ),
@ -516,9 +527,11 @@ xlnx_axi_clock_converter i_xlnx_axi_clock_converter (
);
xlnx_clk_gen i_xlnx_clk_gen (
.clk_out1 ( clk ),
.clk_out1 ( clk ), // 50MHz
.clk_out2 ( eth_txck ), // 25 MHz
.clk_out3 ( eth_clk ), // 100 MHz
.reset ( cpu_reset ),
.locked ( ), // keep open
.locked ( pll_locked ),
.clk_in1 ( ddr_clock_out )
);
@ -637,7 +650,7 @@ xlnx_mig_7_ddr3 i_ddr (
axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 (
.s_axi_aclk ( ddr_clock_out ),
.s_axi_aresetn ( rst_n ),
.s_axi_aresetn ( ndmreset_n ),
.s_axi_awid ( s_axi_awid ),
.s_axi_awaddr ( s_axi_awaddr ),

8
fpga/src/bootrom/ariane.dts
View file

@ -52,7 +52,7 @@
interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,max-priority = <7>;
riscv,ndev = <2>;
riscv,ndev = <3>;
};
debug-controller@0 {
compatible = "riscv,debug-013";
@ -74,7 +74,7 @@
compatible = "xlnx,axi-ethernetlite-3.0", "xlnx,xps-ethernetlite-1.00.a";
device_type = "network";
interrupt-parent = <&PLIC0>;
interrupts = <2 0>;
interrupts = <3 0>;
local-mac-address = [00 0a 35 00 01 22];
phy-handle = <&phy0>;
reg = <0x0 0x30000000 0x0 0x10000>;
@ -88,10 +88,6 @@
xlnx,tx-ping-pong = <0x1>;
xlnx,use-internal = <0x0>;
xlnx,has-mdio = <0x1>;
// rgmii-id: combines rgmii-rxid and rgmii-txid and thus configures the
// PHY to enable the RX and TX delays. The MAC should neither add the RX
// nor TX delay in this case.
phy-mode = "rgmii-id";
mdio {
#address-cells = <1>;
#size-cells = <0>;

BIN
fpga/src/bootrom/bootrom.elf
View file

Binary file not shown.

4
fpga/src/bootrom/bootrom.h
View file

@ -299,7 +299,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x03000000,
0x04000000,
0xfb000000,
0x02000000,
0x03000000,
0x03000000,
0x04000000,
0xb5000000,
@ -417,7 +417,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x03000000,
0x08000000,
0x25010000,
0x02000000,
0x03000000,
0x00000000,
0x03000000,
0x06000000,

BIN
fpga/src/bootrom/bootrom.img
View file

Binary file not shown.

4
fpga/src/bootrom/bootrom.sv
View file

@ -152,7 +152,7 @@ module bootrom (
64'h03000000_00002201,
64'h00350a00_47010000,
64'h06000000_03000000,
64'h00000000_02000000,
64'h00000000_03000000,
64'h25010000_08000000,
64'h03000000_02000000,
64'h14010000_04000000,
@ -211,7 +211,7 @@ module bootrom (
64'hbb000000_04000000,
64'h03000000_02000000,
64'hb5000000_04000000,
64'h03000000_02000000,
64'h03000000_03000000,
64'hfb000000_04000000,
64'h03000000_07000000,
64'he8000000_04000000,

2
fpga/xilinx/xlnx_axi_ethernetlite/tcl/run.tcl
View file

@ -8,7 +8,7 @@ set_property board_part $boardName [current_project]
create_ip -name axi_ethernetlite -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.C_S_AXI_PROTOCOL {AXI4}] [get_ips $ipName]
set_property -dict [list CONFIG.C_S_AXI_PROTOCOL {AXI4} CONFIG.AXI_ACLK_FREQ_MHZ {100}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]

2
fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
View file

@ -8,7 +8,7 @@ set_property board_part $boardName [current_project]
create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.000} CONFIG.MMCM_CLKIN2_PERIOD {10.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} CONFIG.CLKOUT1_JITTER {129.198} CONFIG.CLKOUT1_PHASE_ERROR {89.971}] [get_ips $ipName]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} CONFIG.CLKOUT2_USED {true} CONFIG.CLKOUT3_USED {true} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {25} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.000} CONFIG.MMCM_CLKIN2_PERIOD {10.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} CONFIG.MMCM_CLKOUT1_DIVIDE {40} CONFIG.MMCM_CLKOUT2_DIVIDE {10} CONFIG.NUM_OUT_CLKS {3} CONFIG.CLKOUT1_JITTER {129.198} CONFIG.CLKOUT1_PHASE_ERROR {89.971} CONFIG.CLKOUT2_JITTER {148.629} CONFIG.CLKOUT2_PHASE_ERROR {89.971} CONFIG.CLKOUT3_JITTER {112.316} CONFIG.CLKOUT3_PHASE_ERROR {89.971}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]

2
src/common_cells

@ -1 +1 @@
Subproject commit cb801849915b6bcd7af33f4aa8389c627324a31b
Subproject commit 6de11b90cde4b408adc1f27c655844c54de8080d

18
src/debug/dm_csrs.sv
View file

@ -453,17 +453,7 @@ module dm_csrs #(
logic ndmreset_n;
// if the PoR is set we want to re-set the other system as well
rstgen_bypass i_rstgen_bypass (
.clk_i ( clk_i ),
.rst_ni ( ~(dmcontrol_q.ndmreset | ~rst_ni) ),
.rst_test_mode_ni ( rst_ni ),
.test_mode_i ( testmode_i ),
.rst_no ( ndmreset_n ),
.init_no () // keep open
);
assign ndmreset_o = ~ndmreset_n;
assign ndmreset_o = dmcontrol_q.ndmreset;
// response FIFO
fifo_v2 #(
@ -538,7 +528,7 @@ module dm_csrs #(
end
///////////////////////////////////////////////////////
@ -549,8 +539,8 @@ module dm_csrs #(
//pragma translate_off
`ifndef VERILATOR
haltsum: assert property (
@(posedge clk_i) disable iff (~rst_ni) (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) |->
!({1'b0, dmi_req_i.addr} inside {dm::HaltSum0, dm::HaltSum1, dm::HaltSum2, dm::HaltSum3}))
@(posedge clk_i) disable iff (~rst_ni) (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) |->
!({1'b0, dmi_req_i.addr} inside {dm::HaltSum0, dm::HaltSum1, dm::HaltSum2, dm::HaltSum3}))
else $warning("Haltsums are not implemented yet and always return 0.");
`endif
//pragma translate_on