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👕 Remove linter warnings in CSR file
This commit is contained in:
Florian Zaruba
parent
65914ea35a
commit
4658c6f182
4 changed files with 37 additions and 29 deletions
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@ -202,7 +202,6 @@ package ariane_pkg;
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localparam ENV_CALL_MMODE = 64'hB;
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typedef enum logic [11:0] {
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CSR_SSTATUS = 12'h100,
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CSR_SIE = 12'h104,
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CSR_STVEC = 12'h105,
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@ -237,10 +236,10 @@ package ariane_pkg;
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logic [7:0] address;
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} csr_addr_t;
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`ifndef VERILATOR
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// `ifndef VERILATOR
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typedef union packed {
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csr_reg_t address;
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csr_addr_t csr_decode;
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} csr_t;
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`endif
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// `endif
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endpackage
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@ -174,7 +174,7 @@ module ariane
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exception csr_exception_csr_commit;
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// --------------
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// EX <-> CSR
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// --------------
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// --------------
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// TODO: Preliminary signal assignments
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logic flush_tlb;
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@ -339,8 +339,9 @@ module ariane
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// ---------
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csr_regfile #(
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.ASID_WIDTH ( ASID_WIDTH )
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)
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)
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csr_regfile_i (
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.flush_o ( ),
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.ex_i ( ex_commit_csr ),
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.csr_op_i ( csr_op_commit_csr ),
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.csr_addr_i ( csr_addr_ex_csr ),
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@ -22,9 +22,10 @@ import ariane_pkg::*;
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module csr_regfile #(
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parameter int ASID_WIDTH = 1
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)(
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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// send a flush request out if a CSR with a side effect has changed
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output logic flush_o,
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// Core and Cluster ID
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input logic [3:0] core_id_i,
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input logic [5:0] cluster_id_i,
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@ -42,8 +43,8 @@ module csr_regfile #(
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// raises illegal instruction exceptions.
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// Interrupts/Exceptions
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output logic [3:0] irq_enable_o,
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output logic [31:0] epc_o,
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output logic [31:0] trap_vector_base_o,
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output logic [63:0] epc_o,
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output logic [63:0] trap_vector_base_o,
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output priv_lvl_t priv_lvl_o,
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// MMU
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output logic enable_translation_o,
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@ -151,9 +152,9 @@ module csr_regfile #(
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CSR_MEPC: csr_rdata = mepc_q;
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CSR_MCAUSE: csr_rdata = mcause_q;
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CSR_MTVAL: csr_rdata = mtval_q;
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CSR_MVENDORID: csr_rdata = 63'b0; // not implemented
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CSR_MARCHID: csr_rdata = 63'b0; // PULP, anonymous source (no allocated ID yet)
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CSR_MIMPID: csr_rdata = 63'b0; // not implemented
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CSR_MVENDORID: csr_rdata = 64'b0; // not implemented
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CSR_MARCHID: csr_rdata = 64'b0; // PULP, anonymous source (no allocated ID yet)
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CSR_MIMPID: csr_rdata = 64'b0; // not implemented
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CSR_MHARTID: csr_rdata = {53'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]};
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default: read_access_exception = 1'b1;
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endcase
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@ -164,6 +165,7 @@ module csr_regfile #(
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always_comb begin : csr_update
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update_access_exception = 1'b0;
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priv_lvl_n = priv_lvl_q;
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mstatus_n = mstatus_q;
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mtvec_n = mtvec_q;
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medeleg_n = medeleg_q;
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@ -180,9 +182,10 @@ module csr_regfile #(
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stvec_n = stvec_q;
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sscratch_n = sscratch_q;
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stval_n = stval_q;
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satp_n = satp_q;
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// check for correct access rights and that we are writing
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if ((priv_lvl_q && csr_addr.csr_decode.priv_lvl) == csr_addr.csr_decode.priv_lvl && csr_we) begin
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if (((priv_lvl_q & csr_addr.csr_decode.priv_lvl) == csr_addr.csr_decode.priv_lvl) && csr_we) begin
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case (csr_addr.address)
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// sstatus is a subset of mstatus - mask it accordingly
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CSR_SSTATUS: mstatus_n = csr_wdata & 64'h3fffe1fee;
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@ -192,16 +195,18 @@ module csr_regfile #(
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CSR_SIP: mip_n = csr_wdata & (~64'h111) & mideleg_q;
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CSR_STVEC: stvec_n = {csr_wdata[63:2], 1'b0, csr_wdata[0]};
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CSR_SSCRATCH: sscratch_n = csr_wdata;
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CSR_SEPC: sepc_n = csr_wdata_i[63:1];
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CSR_SCAUSE: scause_n = csr_wdata_i;
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CSR_STVAL: stval_n = csr_wdata_i;
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CSR_SEPC: sepc_n = {csr_wdata[63:1], 1'b0};
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CSR_SCAUSE: scause_n = csr_wdata;
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CSR_STVAL: stval_n = csr_wdata;
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// supervisor address translation and protection
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CSR_SATP: satp_n = sapt_t'(csr_wdata_i);
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CSR_SATP: satp_n = sapt_t'(csr_wdata);
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CSR_MSTATUS: begin
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mstatus_n = csr_wdata;
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mstatus_n = csr_wdata;
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mstatus_n.sxl = 2'b0;
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mstatus_n.uxl = 2'b0;
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// hardwired zero registers
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mstatus_n.sd = 1'b0;
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mstatus_n.sd = 1'b0;
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mstatus_n.xs = 2'b0;
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mstatus_n.fs = 2'b0;
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mstatus_n.upie = 1'b0;
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@ -219,10 +224,10 @@ module csr_regfile #(
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CSR_MIP: mip_n = csr_wdata & (~64'h111);
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CSR_MTVEC: mtvec_n = {csr_wdata[63:2], 1'b0, csr_wdata[0]};
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CSR_MSCRATCH: mscratch_n = csr_wdata_i;
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CSR_MEPC: mepc_n = csr_wdata_i[63:1];
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CSR_MCAUSE: mcause_n = csr_wdata_i;
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CSR_MTVAL: mtval_n = csr_wdata_i;
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CSR_MSCRATCH: mscratch_n = csr_wdata;
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CSR_MEPC: mepc_n = {csr_wdata[63:1], 1'b0};
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CSR_MCAUSE: mcause_n = csr_wdata;
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CSR_MTVAL: mtval_n = csr_wdata;
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default: update_access_exception = 1'b1;
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endcase
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end else begin
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@ -234,6 +239,7 @@ module csr_regfile #(
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automatic priv_lvl_t trap_to_priv_lvl;
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// figure out where to trap to
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// a m-mode trap might be delegated
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// first figure out if this was an exception or an interrupt e.g.: look at bit 63
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if ((ex_i.cause[63] && mideleg_q[ex_i.cause[62:0]]) ||
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(~ex_i.cause[63] && mideleg_q[ex_i.cause[62:0]])) begin
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trap_to_priv_lvl = PRIV_LVL_S;
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@ -302,7 +308,7 @@ module csr_regfile #(
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assign priv_lvl_o = priv_lvl_q;
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// MMU outputs
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assign pd_ppn_o = satp_q.ppn;
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assign asid_o = satp_q.asid;
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assign asid_o = satp_q.asid[ASID_WIDTH-1:0];
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assign flag_pum_o = mstatus_q.sum;
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assign enable_translation_o = mstatus_q.tvm;
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assign flag_mxr_o = mstatus_q.mxr;
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@ -347,10 +353,11 @@ module csr_regfile #(
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stvec_q <= 64'b0;
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sscratch_q <= 64'b0;
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stval_q <= 64'b0;
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satp_q <= 64'b0;
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end else begin
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priv_lvl_q <= priv_lvl_n;
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prev_priv_lvl_q <= prev_priv_lvl_n;
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// supervisor mode registers
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// machine mode registers
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mstatus_q <= mstatus_n;
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mtvec_q <= mtvec_n;
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medeleg_q <= medeleg_n;
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@ -361,12 +368,13 @@ module csr_regfile #(
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mcause_q <= mcause_n;
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mscratch_q <= mscratch_n;
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mtval_q <= mtval_n;
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// machine mode registers
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// supervisor mode registers
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sepc_q <= sepc_n;
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scause_q <= scause_n;
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stvec_q <= stvec_n;
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sscratch_q <= sscratch_n;
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stval_q <= stval_n;
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satp_q <= satp_n;
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end
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end
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endmodule
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@ -167,8 +167,8 @@ module lsu #(
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// MMU e.g.: TLBs/PTW
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// -------------------
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mmu #(
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.INSTR_TLB_ENTRIES ( 4 ),
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.DATA_TLB_ENTRIES ( 4 ),
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.INSTR_TLB_ENTRIES ( 16 ),
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.DATA_TLB_ENTRIES ( 16 ),
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.ASID_WIDTH ( ASID_WIDTH )
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) i_mmu (
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.lsu_req_i ( translation_req ),
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