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Merge pull request #166 from jrrk/rgmii_eth

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Add RGMII ETH
This commit is contained in:
Florian Zaruba 2019-01-29 16:26:45 +01:00 • committed by GitHub
commit 46d29c4827
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GPG key ID: 4AEE18F83AFDEB23
15 changed files with 411 additions and 1265 deletions
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3
.gitmodules vendored
View file

@ -37,3 +37,6 @@
[submodule "src/fpu"]
path = src/fpu
url = https://github.com/pulp-platform/fpnew.git
[submodule "fpga/src/ariane-ethernet"]
path = fpga/src/ariane-ethernet
url = https://github.com/lowRISC/ariane-ethernet.git

2
Makefile
View file

@ -142,7 +142,7 @@ src := $(addprefix $(root-dir), $(src))
uart_src := $(wildcard fpga/src/apb_uart/src/*.vhd)
uart_src := $(addprefix $(root-dir), $(uart_src))
fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv)
fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildcard fpga/src/ariane-ethernet/*.sv)
fpga_src := $(addprefix $(root-dir), $(fpga_src))
# look for testbenches

1
fpga/Makefile
View file

@ -10,7 +10,6 @@ ips := xlnx_axi_clock_converter.xci \
xlnx_axi_quad_spi.xci \
xlnx_axi_gpio.xci \
xlnx_clk_gen.xci \
xlnx_axi_ethernetlite.xci \
xlnx_mig_7_ddr3.xci
ips := $(addprefix $(work-dir)/, $(ips))

1
fpga/scripts/run.tcl
View file

@ -20,7 +20,6 @@ add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc
read_ip xilinx/xlnx_mig_7_ddr3/ip/xlnx_mig_7_ddr3.xci
read_ip xilinx/xlnx_axi_clock_converter/ip/xlnx_axi_clock_converter.xci
read_ip xilinx/xlnx_axi_dwidth_converter/ip/xlnx_axi_dwidth_converter.xci
read_ip xilinx/xlnx_axi_ethernetlite/ip/xlnx_axi_ethernetlite.xci
read_ip xilinx/xlnx_axi_gpio/ip/xlnx_axi_gpio.xci
read_ip xilinx/xlnx_axi_quad_spi/ip/xlnx_axi_quad_spi.xci
read_ip xilinx/xlnx_clk_gen/ip/xlnx_clk_gen.xci

1
fpga/src/ariane-ethernet Submodule

@ -0,0 +1 @@
Subproject commit ac563aa57f067f135a3ff278552e4cff3b841040

370
fpga/src/ariane_peripherals_xilinx.sv
View file

@ -9,6 +9,8 @@
// specific language governing permissions and limitations under the License.
// Xilinx Peripehrals
`default_nettype none
module ariane_peripherals #(
parameter int AxiAddrWidth = -1,
parameter int AxiDataWidth = -1,
@ -40,7 +42,7 @@ module ariane_peripherals #(
output wire eth_txctl ,
output wire [3:0] eth_txd ,
output wire eth_rst_n ,
input logic phy_tx_clk_i , // 25 MHz Clock
input logic phy_tx_clk_i , // 125 MHz Clock
// MDIO Interface
inout wire eth_mdio ,
output logic eth_mdc ,
@ -484,310 +486,76 @@ module ariane_peripherals #(
// ---------------
// 4. Ethernet
// ---------------
assign ethernet.b_user = 1'b0;
assign ethernet.r_user = 1'b0;
if (InclEthernet) begin : gen_ethernet
AXI_BUS #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) axi_ethernet_cdc();
logic clk_200_int, clk_rgmii, clk_rgmii_quad;
logic eth_en, eth_we, eth_int_n, eth_pme_n, eth_mdio_i, eth_mdio_o, eth_mdio_oen;
logic [AxiAddrWidth-1:0] eth_addr;
logic [AxiDataWidth-1:0] eth_wrdata, eth_rdata;
logic [AxiDataWidth/8-1:0] eth_be;
logic s_eth_rst_n;
axi2mem #(
.AXI_ID_WIDTH ( AxiIdWidth ),
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth ),
.AXI_USER_WIDTH ( AxiUserWidth )
) i_axi2rom (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.slave ( ethernet ),
.req_o ( eth_en ),
.we_o ( eth_we ),
.addr_o ( eth_addr ),
.be_o ( eth_be ),
.data_o ( eth_wrdata ),
.data_i ( eth_rdata )
);
logic [31:0] s_axi_eth_awaddr;
logic [7:0] s_axi_eth_awlen;
logic [2:0] s_axi_eth_awsize;
logic [1:0] s_axi_eth_awburst;
logic [3:0] s_axi_eth_awcache;
logic s_axi_eth_awvalid;
logic s_axi_eth_awready;
logic [31:0] s_axi_eth_wdata;
logic [3:0] s_axi_eth_wstrb;
logic s_axi_eth_wlast;
logic s_axi_eth_wvalid;
logic s_axi_eth_wready;
logic [1:0] s_axi_eth_bresp;
logic s_axi_eth_bvalid;
logic s_axi_eth_bready;
logic [31:0] s_axi_eth_araddr;
logic [7:0] s_axi_eth_arlen;
logic [2:0] s_axi_eth_arsize;
logic [1:0] s_axi_eth_arburst;
logic [3:0] s_axi_eth_arcache;
logic s_axi_eth_arvalid;
logic s_axi_eth_arready;
logic [31:0] s_axi_eth_rdata;
logic [1:0] s_axi_eth_rresp;
logic s_axi_eth_rlast;
logic s_axi_eth_rvalid;
framing_top eth_rgmii
(
.msoc_clk(clk_i),
.core_lsu_addr(eth_addr[14:0]),
.core_lsu_wdata(eth_wrdata),
.core_lsu_be(eth_be),
.ce_d(eth_en),
.we_d(eth_en & eth_we),
.framing_sel(eth_en),
.framing_rdata(eth_rdata),
.rst_int(!rst_ni),
.clk_int(phy_tx_clk_i), // 125 MHz in-phase
.clk90_int(eth_clk_i), // 125 MHz quadrature
.clk_200_int(clk_200MHz_i),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy_rx_clk(eth_rxck),
.phy_rxd(eth_rxd),
.phy_rx_ctl(eth_rxctl),
.phy_tx_clk(eth_txck),
.phy_txd(eth_txd),
.phy_tx_ctl(eth_txctl),
.phy_reset_n(eth_rst_n),
.phy_int_n(eth_int_n),
.phy_pme_n(eth_pme_n),
.phy_mdc(eth_mdc),
.phy_mdio_i(eth_mdio_i),
.phy_mdio_o(eth_mdio_o),
.phy_mdio_oen(eth_mdio_oen),
.eth_irq(irq_sources[2])
);
rstgen i_rstgen (
.clk_i ( eth_clk_i ),
.rst_ni ( rst_ni ),
.test_mode_i ( test_en ),
.rst_no ( s_eth_rst_n ),
.init_no ( ) // keep open
);
xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ethernet (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.s_axi_awid ( ethernet.aw_id ),
.s_axi_awaddr ( ethernet.aw_addr ),
.s_axi_awlen ( ethernet.aw_len ),
.s_axi_awsize ( ethernet.aw_size ),
.s_axi_awburst ( ethernet.aw_burst ),
.s_axi_awlock ( ethernet.aw_lock ),
.s_axi_awcache ( ethernet.aw_cache ),
.s_axi_awprot ( ethernet.aw_prot ),
.s_axi_awregion ( ethernet.aw_region ),
.s_axi_awqos ( ethernet.aw_qos ),
.s_axi_awvalid ( ethernet.aw_valid ),
.s_axi_awready ( ethernet.aw_ready ),
.s_axi_wdata ( ethernet.w_data ),
.s_axi_wstrb ( ethernet.w_strb ),
.s_axi_wlast ( ethernet.w_last ),
.s_axi_wvalid ( ethernet.w_valid ),
.s_axi_wready ( ethernet.w_ready ),
.s_axi_bid ( ethernet.b_id ),
.s_axi_bresp ( ethernet.b_resp ),
.s_axi_bvalid ( ethernet.b_valid ),
.s_axi_bready ( ethernet.b_ready ),
.s_axi_arid ( ethernet.ar_id ),
.s_axi_araddr ( ethernet.ar_addr ),
.s_axi_arlen ( ethernet.ar_len ),
.s_axi_arsize ( ethernet.ar_size ),
.s_axi_arburst ( ethernet.ar_burst ),
.s_axi_arlock ( ethernet.ar_lock ),
.s_axi_arcache ( ethernet.ar_cache ),
.s_axi_arprot ( ethernet.ar_prot ),
.s_axi_arregion ( ethernet.ar_region ),
.s_axi_arqos ( ethernet.ar_qos ),
.s_axi_arvalid ( ethernet.ar_valid ),
.s_axi_arready ( ethernet.ar_ready ),
.s_axi_rid ( ethernet.r_id ),
.s_axi_rdata ( ethernet.r_data ),
.s_axi_rresp ( ethernet.r_resp ),
.s_axi_rlast ( ethernet.r_last ),
.s_axi_rvalid ( ethernet.r_valid ),
.s_axi_rready ( ethernet.r_ready ),
// to size converter
.m_axi_aclk ( eth_clk_i ),
.m_axi_aresetn ( s_eth_rst_n ),
.m_axi_awid ( axi_ethernet_cdc.aw_id ),
.m_axi_awaddr ( axi_ethernet_cdc.aw_addr ),
.m_axi_awlen ( axi_ethernet_cdc.aw_len ),
.m_axi_awsize ( axi_ethernet_cdc.aw_size ),
.m_axi_awburst ( axi_ethernet_cdc.aw_burst ),
.m_axi_awlock ( axi_ethernet_cdc.aw_lock ),
.m_axi_awcache ( axi_ethernet_cdc.aw_cache ),
.m_axi_awprot ( axi_ethernet_cdc.aw_prot ),
.m_axi_awregion ( axi_ethernet_cdc.aw_region ),
.m_axi_awqos ( axi_ethernet_cdc.aw_qos ),
.m_axi_awvalid ( axi_ethernet_cdc.aw_valid ),
.m_axi_awready ( axi_ethernet_cdc.aw_ready ),
.m_axi_wdata ( axi_ethernet_cdc.w_data ),
.m_axi_wstrb ( axi_ethernet_cdc.w_strb ),
.m_axi_wlast ( axi_ethernet_cdc.w_last ),
.m_axi_wvalid ( axi_ethernet_cdc.w_valid ),
.m_axi_wready ( axi_ethernet_cdc.w_ready ),
.m_axi_bid ( axi_ethernet_cdc.b_id ),
.m_axi_bresp ( axi_ethernet_cdc.b_resp ),
.m_axi_bvalid ( axi_ethernet_cdc.b_valid ),
.m_axi_bready ( axi_ethernet_cdc.b_ready ),
.m_axi_arid ( axi_ethernet_cdc.ar_id ),
.m_axi_araddr ( axi_ethernet_cdc.ar_addr ),
.m_axi_arlen ( axi_ethernet_cdc.ar_len ),
.m_axi_arsize ( axi_ethernet_cdc.ar_size ),
.m_axi_arburst ( axi_ethernet_cdc.ar_burst ),
.m_axi_arlock ( axi_ethernet_cdc.ar_lock ),
.m_axi_arcache ( axi_ethernet_cdc.ar_cache ),
.m_axi_arprot ( axi_ethernet_cdc.ar_prot ),
.m_axi_arregion ( axi_ethernet_cdc.ar_region ),
.m_axi_arqos ( axi_ethernet_cdc.ar_qos ),
.m_axi_arvalid ( axi_ethernet_cdc.ar_valid ),
.m_axi_arready ( axi_ethernet_cdc.ar_ready ),
.m_axi_rid ( axi_ethernet_cdc.r_id ),
.m_axi_rdata ( axi_ethernet_cdc.r_data ),
.m_axi_rresp ( axi_ethernet_cdc.r_resp ),
.m_axi_rlast ( axi_ethernet_cdc.r_last ),
.m_axi_rvalid ( axi_ethernet_cdc.r_valid ),
.m_axi_rready ( axi_ethernet_cdc.r_ready )
);
// system-bus is 64-bit, convert down to 32 bit
xlnx_axi_dwidth_converter i_xlnx_axi_dwidth_converter_ethernet (
.s_axi_aclk ( eth_clk_i ),
.s_axi_aresetn ( s_eth_rst_n ),
.s_axi_awid ( axi_ethernet_cdc.aw_id ),
.s_axi_awaddr ( axi_ethernet_cdc.aw_addr[31:0] ),
.s_axi_awlen ( axi_ethernet_cdc.aw_len ),
.s_axi_awsize ( axi_ethernet_cdc.aw_size ),
.s_axi_awburst ( axi_ethernet_cdc.aw_burst ),
.s_axi_awlock ( axi_ethernet_cdc.aw_lock ),
.s_axi_awcache ( axi_ethernet_cdc.aw_cache ),
.s_axi_awprot ( axi_ethernet_cdc.aw_prot ),
.s_axi_awregion ( axi_ethernet_cdc.aw_region ),
.s_axi_awqos ( axi_ethernet_cdc.aw_qos ),
.s_axi_awvalid ( axi_ethernet_cdc.aw_valid ),
.s_axi_awready ( axi_ethernet_cdc.aw_ready ),
.s_axi_wdata ( axi_ethernet_cdc.w_data ),
.s_axi_wstrb ( axi_ethernet_cdc.w_strb ),
.s_axi_wlast ( axi_ethernet_cdc.w_last ),
.s_axi_wvalid ( axi_ethernet_cdc.w_valid ),
.s_axi_wready ( axi_ethernet_cdc.w_ready ),
.s_axi_bid ( axi_ethernet_cdc.b_id ),
.s_axi_bresp ( axi_ethernet_cdc.b_resp ),
.s_axi_bvalid ( axi_ethernet_cdc.b_valid ),
.s_axi_bready ( axi_ethernet_cdc.b_ready ),
.s_axi_arid ( axi_ethernet_cdc.ar_id ),
.s_axi_araddr ( axi_ethernet_cdc.ar_addr[31:0] ),
.s_axi_arlen ( axi_ethernet_cdc.ar_len ),
.s_axi_arsize ( axi_ethernet_cdc.ar_size ),
.s_axi_arburst ( axi_ethernet_cdc.ar_burst ),
.s_axi_arlock ( axi_ethernet_cdc.ar_lock ),
.s_axi_arcache ( axi_ethernet_cdc.ar_cache ),
.s_axi_arprot ( axi_ethernet_cdc.ar_prot ),
.s_axi_arregion ( axi_ethernet_cdc.ar_region ),
.s_axi_arqos ( axi_ethernet_cdc.ar_qos ),
.s_axi_arvalid ( axi_ethernet_cdc.ar_valid ),
.s_axi_arready ( axi_ethernet_cdc.ar_ready ),
.s_axi_rid ( axi_ethernet_cdc.r_id ),
.s_axi_rdata ( axi_ethernet_cdc.r_data ),
.s_axi_rresp ( axi_ethernet_cdc.r_resp ),
.s_axi_rlast ( axi_ethernet_cdc.r_last ),
.s_axi_rvalid ( axi_ethernet_cdc.r_valid ),
.s_axi_rready ( axi_ethernet_cdc.r_ready ),
.m_axi_awaddr ( s_axi_eth_awaddr ),
.m_axi_awlen ( s_axi_eth_awlen ),
.m_axi_awsize ( s_axi_eth_awsize ),
.m_axi_awburst ( s_axi_eth_awburst ),
.m_axi_awlock ( ),
.m_axi_awcache ( s_axi_eth_awcache ),
.m_axi_awprot ( ),
.m_axi_awregion ( ),
.m_axi_awqos ( ),
.m_axi_awvalid ( s_axi_eth_awvalid ),
.m_axi_awready ( s_axi_eth_awready ),
.m_axi_wdata ( s_axi_eth_wdata ),
.m_axi_wstrb ( s_axi_eth_wstrb ),
.m_axi_wlast ( s_axi_eth_wlast ),
.m_axi_wvalid ( s_axi_eth_wvalid ),
.m_axi_wready ( s_axi_eth_wready ),
.m_axi_bresp ( s_axi_eth_bresp ),
.m_axi_bvalid ( s_axi_eth_bvalid ),
.m_axi_bready ( s_axi_eth_bready ),
.m_axi_araddr ( s_axi_eth_araddr ),
.m_axi_arlen ( s_axi_eth_arlen ),
.m_axi_arsize ( s_axi_eth_arsize ),
.m_axi_arburst ( s_axi_eth_arburst ),
.m_axi_arlock ( ),
.m_axi_arcache ( s_axi_eth_arcache ),
.m_axi_arprot ( ),
.m_axi_arregion ( ),
.m_axi_arqos ( ),
.m_axi_arvalid ( s_axi_eth_arvalid ),
.m_axi_arready ( s_axi_eth_arready ),
.m_axi_rdata ( s_axi_eth_rdata ),
.m_axi_rresp ( s_axi_eth_rresp ),
.m_axi_rlast ( s_axi_eth_rlast ),
.m_axi_rvalid ( s_axi_eth_rvalid ),
.m_axi_rready ( s_axi_eth_rready )
);
logic phy_rx_clk;
logic phy_crs;
logic phy_dv;
logic [3:0] phy_rx_data;
logic phy_col;
logic phy_rx_er;
logic phy_rst_n;
logic phy_tx_en;
logic [3:0] phy_tx_data;
logic phy_mdio_i;
logic phy_mdio_o;
logic phy_mdio_t;
logic phy_mdc;
xlnx_axi_ethernetlite i_xlnx_axi_ethernetlite (
.s_axi_aclk ( eth_clk_i ),
.s_axi_aresetn ( s_eth_rst_n ),
.ip2intc_irpt ( irq_sources[2] ),
.s_axi_awaddr ( s_axi_eth_awaddr[12:0] ),
.s_axi_awlen ( s_axi_eth_awlen ),
.s_axi_awsize ( s_axi_eth_awsize ),
.s_axi_awburst ( s_axi_eth_awburst ),
.s_axi_awcache ( s_axi_eth_awcache ),
.s_axi_awvalid ( s_axi_eth_awvalid ),
.s_axi_awready ( s_axi_eth_awready ),
.s_axi_wdata ( s_axi_eth_wdata ),
.s_axi_wstrb ( s_axi_eth_wstrb ),
.s_axi_wlast ( s_axi_eth_wlast ),
.s_axi_wvalid ( s_axi_eth_wvalid ),
.s_axi_wready ( s_axi_eth_wready ),
.s_axi_bresp ( s_axi_eth_bresp ),
.s_axi_bvalid ( s_axi_eth_bvalid ),
.s_axi_bready ( s_axi_eth_bready ),
.s_axi_araddr ( s_axi_eth_araddr[12:0] ),
.s_axi_arlen ( s_axi_eth_arlen ),
.s_axi_arsize ( s_axi_eth_arsize ),
.s_axi_arburst ( s_axi_eth_arburst ),
.s_axi_arcache ( s_axi_eth_arcache ),
.s_axi_arvalid ( s_axi_eth_arvalid ),
.s_axi_arready ( s_axi_eth_arready ),
.s_axi_rdata ( s_axi_eth_rdata ),
.s_axi_rresp ( s_axi_eth_rresp ),
.s_axi_rlast ( s_axi_eth_rlast ),
.s_axi_rvalid ( s_axi_eth_rvalid ),
.s_axi_rready ( s_axi_eth_rready ),
.phy_tx_clk ( phy_tx_clk_i ),
.phy_rx_clk ( phy_rx_clk ),
.phy_crs ( phy_crs ),
.phy_dv ( phy_dv ),
.phy_rx_data ( phy_rx_data ),
.phy_col ( phy_col ),
.phy_rx_er ( phy_rx_er ),
.phy_rst_n ( phy_rst_n ),
.phy_tx_en ( phy_tx_en ),
.phy_tx_data ( phy_tx_data ),
.phy_mdio_i ( phy_mdio_i ),
.phy_mdio_o ( phy_mdio_o ),
.phy_mdio_t ( phy_mdio_t ),
.phy_mdc ( phy_mdc )
);
assign phy_crs = 1'b0;
assign phy_col = 1'b0;
rgmii_to_mii_conv_xilinx i_rgmii_to_mii_conv_xilinx (
.rgmii_phy_txc ( eth_txck ),
.rgmii_phy_txctl ( eth_txctl ),
.rgmii_phy_txd ( eth_txd ),
.rgmii_phy_rxc ( eth_rxck ),
.rgmii_phy_rxctl ( eth_rxctl ),
.rgmii_phy_rxd ( eth_rxd ),
.rgmii_phy_rst_n ( eth_rst_n ),
.rgmii_phy_mdio ( eth_mdio ),
.rgmii_phy_mdc ( eth_mdc ),
.mem_clk_i ( clk_200MHz_i ),
.net_phy_rst_n ( phy_rst_n ),
.net_phy_tx_clk ( phy_tx_clk_i ),
.net_phy_tx_en ( phy_tx_en ),
.net_phy_tx_data ( phy_tx_data ),
.net_phy_rx_clk ( phy_rx_clk ),
.net_phy_dv ( phy_dv ),
.net_phy_rx_data ( phy_rx_data ),
.net_phy_rx_er ( phy_rx_er ),
.net_mdio_i ( phy_mdio_o ),
.net_mdio_o ( phy_mdio_i ),
.net_mdio_t ( phy_mdio_t ),
.net_phy_mdc ( phy_mdc )
);
IOBUF #(
.DRIVE(12), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
.O(eth_mdio_i), // Buffer output
.IO(eth_mdio), // Buffer inout port (connect directly to top-level port)
.I(eth_mdio_o), // Buffer input
.T(~eth_mdio_oen) // 3-state enable input, high=input, low=output
);
end else begin
assign irq_sources [2] = 1'b0;
@ -838,6 +606,8 @@ module ariane_peripherals #(
logic [1:0] s_axi_gpio_rresp;
logic s_axi_gpio_rlast;
logic s_axi_gpio_rvalid;
logic s_axi_gpio_rready;
// system-bus is 64-bit, convert down to 32 bit
xlnx_axi_dwidth_converter i_xlnx_axi_dwidth_converter_gpio (
.s_axi_aclk ( clk_i ),
@ -949,3 +719,5 @@ module ariane_peripherals #(
assign s_axi_gpio_wlast = 1'b1;
end
endmodule
`default_nettype wire

6
fpga/src/ariane_xilinx.sv
View file

@ -536,9 +536,9 @@ xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ddr (
);
xlnx_clk_gen i_xlnx_clk_gen (
.clk_out1 ( clk ), // 50MHz
.clk_out2 ( phy_tx_clk ), // 25 MHz
.clk_out3 ( eth_clk ), // 100 MHz
.clk_out1 ( clk ), // 50 MHz
.clk_out2 ( phy_tx_clk ), // 125 MHz (for RGMII PHY)
.clk_out3 ( eth_clk ), // 125 MHz quadrature
.reset ( cpu_reset ),
.locked ( pll_locked ),
.clk_in1 ( ddr_clock_out )

28
fpga/src/bootrom/ariane.dts
View file

@ -108,33 +108,13 @@
// //interrupt-parent = <&PLIC0>;
// };
};
xlnx_axi_ethernetlite: ethernet@30000000 {
compatible = "xlnx,axi-ethernetlite-3.0", "xlnx,xps-ethernetlite-1.00.a";
eth: lowrisc-eth@30000000 {
compatible = "lowrisc-eth";
device_type = "network";
interrupt-parent = <&PLIC0>;
interrupts = <3 0>;
local-mac-address = [00 0a 35 00 01 22];
phy-handle = <&phy0>;
reg = <0x0 0x30000000 0x0 0x10000>;
xlnx,duplex = <0x1>;
xlnx,include-global-buffers = <0x1>;
xlnx,include-internal-loopback = <0x0>;
xlnx,include-mdio = <0x1>;
xlnx,instance = "i_xlnx_axi_ethernetlite";
xlnx,rx-ping-pong = <0x1>;
xlnx,s-axi-id-width = <0x4>;
xlnx,tx-ping-pong = <0x1>;
xlnx,use-internal = <0x0>;
xlnx,has-mdio = <0x1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: axi_ethernetlite_0_mdio@1 {
compatible = "ethernet-phy-id001C.C915";
device_type = "network";
reg = <0x1>;
};
};
local-mac-address = [ee e1 e2 e3 e4 e5];
reg = <0x0 0x30000000 0x0 0x8000>;
};
xlnx_gpio: gpio@40000000 {
#gpio-cells = <2>;

414
fpga/src/bootrom/bootrom.h
View file

@ -1,6 +1,6 @@
// Auto-generated code
const int reset_vec_size = 1884;
const int reset_vec_size = 1724;
uint32_t reset_vec[reset_vec_size] = {
0x00800913,
@ -150,9 +150,9 @@ uint32_t reset_vec[reset_vec_size] = {
0x610560e2,
0xc10c8082,
0x41088082,
0x25178082,
0x15178082,
0x11010000,
0x84a50513,
0x5d250513,
0xe822ec06,
0xf0efe426,
0x07b7f05f,
@ -162,31 +162,31 @@ uint32_t reset_vec[reset_vec_size] = {
0x0437fff5,
0x07932000,
0xd03c1040,
0x25175064,
0x15175064,
0x05130000,
0xf0ef82a5,
0xf0ef5b25,
0x2481eddf,
0x02049513,
0xf0ef9101,
0x2517f53f,
0x1517f53f,
0x05130000,
0xf0ef8325,
0xf0ef5ba5,
0x0793ec5f,
0xd03c1660,
0x15175064,
0x05130000,
0xf0ef7fe5,
0xf0ef5865,
0x2481eb1f,
0x02049513,
0xf0ef9101,
0x2517f27f,
0x1517f27f,
0x05130000,
0xf0ef8065,
0xf0ef58e5,
0x4799e99f,
0x6442d03c,
0x64a260e2,
0x00001517,
0x7e050513,
0x56850513,
0xf06f6105,
0x1101e81f,
0x200007b7,
@ -204,13 +204,13 @@ uint32_t reset_vec[reset_vec_size] = {
0x240153fc,
0xe3958b85,
0x00001517,
0x7b050513,
0x53850513,
0xe3bff0ef,
0x15024088,
0xf0ef9101,
0x1517eb3f,
0x05130000,
0xf0ef7925,
0xf0ef51a5,
0x07b7e25f,
0x577d2000,
0x0ff47513,
@ -283,18 +283,18 @@ uint32_t reset_vec[reset_vec_size] = {
0xe8221101,
0x1517842a,
0x05130000,
0xec0668e5,
0xec064165,
0xf0efe42e,
0x8522cfdf,
0xcf7ff0ef,
0x00001517,
0x68850513,
0x41050513,
0xcebff0ef,
0x852e65a2,
0xda7ff0ef,
0x60e26442,
0x00001517,
0x64050513,
0x3c850513,
0xf06f6105,
0x1101cd1f,
0x6409e822,
@ -309,7 +309,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x15e3c00d,
0x1517fe99,
0x05130000,
0x45856465,
0x45853ce5,
0xf89ff0ef,
0x60e24505,
0x64a26442,
@ -347,7 +347,7 @@ uint32_t reset_vec[reset_vec_size] = {
0xe89ff0ef,
0x00001517,
0x051385a2,
0xf0ef5b85,
0xf0ef3405,
0x051bef3f,
0x60a20004,
0x157d6402,
@ -363,7 +363,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x842ae53f,
0x151785aa,
0x05130000,
0xf0ef57e5,
0xf0ef3065,
0xf0efeb3f,
0x0ce3e37f,
0x051bfc94,
@ -375,7 +375,7 @@ uint32_t reset_vec[reset_vec_size] = {
0xf0efe022,
0x1517c89f,
0x05130000,
0xf0ef5565,
0xf0ef2de5,
0x4429b91f,
0xf0ef347d,
0xfc6de03f,
@ -470,7 +470,7 @@ uint32_t reset_vec[reset_vec_size] = {
0xe7b30534,
0xe7990354,
0x00001517,
0x3f050513,
0x17850513,
0xa13ff0ef,
0x46e314fd,
0x4401f890,
@ -494,7 +494,7 @@ uint32_t reset_vec[reset_vec_size] = {
0xf0ef8b2e,
0xc51de1ff,
0x00001517,
0x39850513,
0x12050513,
0x9b3ff0ef,
0x011354fd,
0x60a6fb04,
@ -505,7 +505,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x6c026ba2,
0x80826161,
0x00001517,
0x39450513,
0x11c50513,
0x987ff0ef,
0x46057101,
0x850a4585,
@ -513,67 +513,67 @@ uint32_t reset_vec[reset_vec_size] = {
0x84aa890a,
0x1517c905,
0x05130000,
0xf0ef38e5,
0xf0ef1165,
0x1517969f,
0x05130000,
0xf0ef39a5,
0xf0ef1225,
0x852695df,
0x9d9ff0ef,
0x00001517,
0x2b850513,
0x04050513,
0x94bff0ef,
0xbf6154f9,
0x00001517,
0x39050513,
0x11850513,
0x93bff0ef,
0x00001517,
0x3a450513,
0x12c50513,
0x92fff0ef,
0x4b916502,
0x9a9ff0ef,
0x00001517,
0x3a050513,
0x12850513,
0x91bff0ef,
0xf0ef4522,
0x1517957f,
0x05130000,
0xf0ef39e5,
0xf0ef1265,
0x4532909f,
0x945ff0ef,
0x00001517,
0x39c50513,
0x12450513,
0x8f7ff0ef,
0xf0ef4542,
0x1517933f,
0x05130000,
0xf0ef39a5,
0xf0ef1225,
0x45528e5f,
0x921ff0ef,
0x00001517,
0x39850513,
0x12050513,
0x8d3ff0ef,
0xf0ef6562,
0x151794ff,
0x05130000,
0xf0ef39e5,
0xf0ef1265,
0x75028c1f,
0x93dff0ef,
0x00001517,
0x39c50513,
0x12450513,
0x8afff0ef,
0xf0ef6526,
0x151792bf,
0x05130000,
0xf0ef3aa5,
0xf0ef1325,
0x454689df,
0x8d9ff0ef,
0x00001517,
0x3b850513,
0x14050513,
0x88bff0ef,
0xf0ef4556,
0x15178c7f,
0x05130000,
0xf0ef1e65,
0xf0eff6e5,
0x2583879f,
0x71010489,
0x850a4605,
@ -581,22 +581,22 @@ uint32_t reset_vec[reset_vec_size] = {
0x89aa8a8a,
0xc50d0804,
0x00001517,
0x27c50513,
0x00450513,
0x857ff0ef,
0x00001517,
0x28850513,
0x01050513,
0x84bff0ef,
0xf0ef854e,
0x15178c7f,
0x05130000,
0xb5fd1a65,
0xb5fdf2e5,
0x00001517,
0x37c50513,
0x10450513,
0x82fff0ef,
0x0ff9f513,
0x8ebff0ef,
0x00001517,
0x38050513,
0x10850513,
0x81bff0ef,
0xff048913,
0x00094503,
@ -604,64 +604,64 @@ uint32_t reset_vec[reset_vec_size] = {
0x1be38d1f,
0x1517fe99,
0x05130000,
0xf0ef3825,
0xf0ef10a5,
0x0c13ffcf,
0x45030109,
0x09050009,
0x8b3ff0ef,
0xff2c1be3,
0x00001517,
0x38450513,
0x10c50513,
0xfdeff0ef,
0x89136888,
0x8c130284,
0xf0ef0704,
0x1517853f,
0x05130000,
0xf0ef37a5,
0xf0ef1025,
0x6c88fc4f,
0x841ff0ef,
0x00001517,
0x37850513,
0x10050513,
0xfb2ff0ef,
0xf0ef7088,
0x151782ff,
0x05130000,
0xf0ef3765,
0xf0ef0fe5,
0x4503fa0f,
0x09050009,
0x85bff0ef,
0xff2c1be3,
0x00001517,
0x0f450513,
0xe7c50513,
0xf0ef2985,
0x8493f84f,
0x93e30804,
0x1517f579,
0x05130000,
0xf0ef3565,
0xf0ef0de5,
0xa583f70f,
0x865a020a,
0xf0ef8552,
0x84aac5ff,
0x1517c50d,
0x05130000,
0xf0ef17a5,
0xf0eff025,
0x1517f54f,
0x05130000,
0xf0ef1865,
0xf0eff0e5,
0x8526f48f,
0xfc4ff0ef,
0x00001517,
0x0a450513,
0xe2c50513,
0x1517b3f5,
0x05130000,
0xf0ef32a5,
0xf0ef0b25,
0xbbb5f2cf,
0xe4061141,
0xef0ff0ef,
0x00001517,
0x04450513,
0xdcc50513,
0xf16ff0ef,
0x65a14505,
0xf0ef057e,
@ -772,15 +772,15 @@ uint32_t reset_vec[reset_vec_size] = {
0x00000000,
0x00000000,
0xedfe0dd0,
0x860e0000,
0x100c0000,
0x38000000,
0xe40a0000,
0x38090000,
0x28000000,
0x11000000,
0x10000000,
0x00000000,
0xa2030000,
0xac0a0000,
0xd8020000,
0x00090000,
0x00000000,
0x00000000,
0x00000000,
@ -1242,28 +1242,18 @@ uint32_t reset_vec[reset_vec_size] = {
0x02000000,
0x02000000,
0x01000000,
0x65687465,
0x74656e72,
0x30303340,
0x72776f6c,
0x2d637369,
0x40687465,
0x30303033,
0x30303030,
0x00000030,
0x00000000,
0x03000000,
0x37000000,
0x0c000000,
0x1b000000,
0x786e6c78,
0x6978612c,
0x6874652d,
0x656e7265,
0x74696c74,
0x2e332d65,
0x6c780030,
0x782c786e,
0x652d7370,
0x72656874,
0x6c74656e,
0x2d657469,
0x30302e31,
0x0000612e,
0x72776f6c,
0x2d637369,
0x00687465,
0x03000000,
0x08000000,
0x5b000000,
@ -1281,112 +1271,15 @@ uint32_t reset_vec[reset_vec_size] = {
0x03000000,
0x06000000,
0xf9010000,
0x00350a00,
0x00002201,
0x03000000,
0x04000000,
0x0b020000,
0x04000000,
0xe3e2e1ee,
0x0000e5e4,
0x03000000,
0x10000000,
0x67000000,
0x00000000,
0x00000030,
0x00000000,
0x00000100,
0x03000000,
0x04000000,
0x16020000,
0x01000000,
0x03000000,
0x04000000,
0x22020000,
0x01000000,
0x03000000,
0x04000000,
0x3e020000,
0x00000000,
0x03000000,
0x04000000,
0x5d020000,
0x01000000,
0x03000000,
0x18000000,
0x6f020000,
0x6c785f69,
0x615f786e,
0x655f6978,
0x72656874,
0x6c74656e,
0x00657469,
0x03000000,
0x04000000,
0x7d020000,
0x01000000,
0x03000000,
0x04000000,
0x8f020000,
0x04000000,
0x03000000,
0x04000000,
0xa3020000,
0x01000000,
0x03000000,
0x04000000,
0xb5020000,
0x00000000,
0x03000000,
0x04000000,
0xc7020000,
0x01000000,
0x01000000,
0x6f69646d,
0x00000000,
0x03000000,
0x04000000,
0x00000000,
0x01000000,
0x03000000,
0x04000000,
0x0f000000,
0x00000000,
0x01000000,
0x5f697861,
0x65687465,
0x74656e72,
0x6574696c,
0x6d5f305f,
0x406f6964,
0x00000031,
0x03000000,
0x19000000,
0x1b000000,
0x65687465,
0x74656e72,
0x7968702d,
0x3064692d,
0x2e433130,
0x35313943,
0x00000000,
0x03000000,
0x08000000,
0x5b000000,
0x7774656e,
0x006b726f,
0x03000000,
0x04000000,
0x67000000,
0x01000000,
0x03000000,
0x04000000,
0xb5000000,
0x04000000,
0x03000000,
0x04000000,
0xbb000000,
0x04000000,
0x02000000,
0x02000000,
0x00800000,
0x02000000,
0x01000000,
0x6f697067,
@ -1395,7 +1288,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x00000030,
0x03000000,
0x04000000,
0xd5020000,
0x0b020000,
0x02000000,
0x03000000,
0x15000000,
@ -1408,7 +1301,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x00000000,
0x03000000,
0x00000000,
0xe1020000,
0x17020000,
0x03000000,
0x10000000,
0x67000000,
@ -1418,43 +1311,43 @@ uint32_t reset_vec[reset_vec_size] = {
0x00000100,
0x03000000,
0x04000000,
0xf1020000,
0x27020000,
0x00000000,
0x03000000,
0x04000000,
0x01030000,
0x37020000,
0x00000000,
0x03000000,
0x04000000,
0x13030000,
0x49020000,
0x00000000,
0x03000000,
0x04000000,
0x25030000,
0x5b020000,
0x00000000,
0x03000000,
0x04000000,
0x39030000,
0x6f020000,
0x08000000,
0x03000000,
0x04000000,
0x49030000,
0x7f020000,
0x08000000,
0x03000000,
0x04000000,
0x5a030000,
0x90020000,
0x00000000,
0x03000000,
0x04000000,
0x71030000,
0xa7020000,
0x01000000,
0x03000000,
0x04000000,
0x7e030000,
0xb4020000,
0xffffffff,
0x03000000,
0x04000000,
0x8f030000,
0xc5020000,
0xffffffff,
0x03000000,
0x04000000,
@ -1598,109 +1491,58 @@ uint32_t reset_vec[reset_vec_size] = {
0x6d2d6c61,
0x612d6361,
0x65726464,
0x70007373,
0x682d7968,
0x6c646e61,
0x6c780065,
0x642c786e,
0x656c7075,
0x6c780078,
0x692c786e,
0x756c636e,
0x672d6564,
0x61626f6c,
0x75622d6c,
0x72656666,
0x6c780073,
0x692c786e,
0x756c636e,
0x692d6564,
0x7265746e,
0x2d6c616e,
0x706f6f6c,
0x6b636162,
0x6e6c7800,
0x6e692c78,
0x64756c63,
0x646d2d65,
0x78006f69,
0x23007373,
0x6f697067,
0x6c65632d,
0x6700736c,
0x2d6f6970,
0x746e6f63,
0x6c6c6f72,
0x78007265,
0x2c786e6c,
0x74736e69,
0x65636e61,
0x6e6c7800,
0x78722c78,
0x6e69702d,
0x6f702d67,
0x7800676e,
0x2d6c6c61,
0x75706e69,
0x78007374,
0x2c786e6c,
0x78612d73,
0x64692d69,
0x6469772d,
0x78006874,
0x2c786e6c,
0x702d7874,
0x2d676e69,
0x676e6f70,
0x6e6c7800,
0x73752c78,
0x6e692d65,
0x6e726574,
0x78006c61,
0x2c786e6c,
0x2d736168,
0x6f69646d,
0x70672300,
0x632d6f69,
0x736c6c65,
0x69706700,
0x6f632d6f,
0x6f72746e,
0x72656c6c,
0x6e6c7800,
0x6c612c78,
0x6e692d6c,
0x73747570,
0x6e6c7800,
0x6c612c78,
0x6e692d6c,
0x73747570,
0x7800322d,
0x2c786e6c,
0x74756f64,
0x6665642d,
0x746c7561,
0x2d6c6c61,
0x75706e69,
0x322d7374,
0x6e6c7800,
0x6f642c78,
0x642d7475,
0x75616665,
0x322d746c,
0x6e6c7800,
0x70672c78,
0x772d6f69,
0x68746469,
0x6e6c7800,
0x70672c78,
0x2d326f69,
0x74646977,
0x6c780068,
0x692c786e,
0x7265746e,
0x74707572,
0x6572702d,
0x746e6573,
0x6e6c7800,
0x73692c78,
0x6175642d,
0x6c78006c,
0x742c786e,
0x642d6972,
0x75616665,
0x7800746c,
0x2c786e6c,
0x2d697274,
0x61666564,
0x2d746c75,
0x00000032,
0x74756f64,
0x6665642d,
0x746c7561,
0x7800322d,
0x2c786e6c,
0x6f697067,
0x6469772d,
0x78006874,
0x2c786e6c,
0x6f697067,
0x69772d32,
0x00687464,
0x786e6c78,
0x746e692c,
0x75727265,
0x702d7470,
0x65736572,
0x7800746e,
0x2c786e6c,
0x642d7369,
0x006c6175,
0x786e6c78,
0x6972742c,
0x6665642d,
0x746c7561,
0x6e6c7800,
0x72742c78,
0x65642d69,
0x6c756166,
0x00322d74,
0x6c6c6548,
0x6f57206f,
0x21646c72,
@ -1884,7 +1726,5 @@ uint32_t reset_vec[reset_vec_size] = {
0x6e6f6420,
0x0a0d2165,
0x00000000,
0x00000000,
0x00000000,
0x00000000
};

448
fpga/src/bootrom/bootrom.sv
View file

@ -20,10 +20,9 @@ module bootrom (
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int RomSize = 942;
localparam int RomSize = 862;
const logic [RomSize-1:0][63:0] mem = {
64'h00000000_00000000,
64'h00000000_00000000,
64'h0a0d2165_6e6f6420,
64'h00000000_00206567,
@ -116,216 +115,142 @@ module bootrom (
64'h49505320_74696e69,
64'h00000a0d_21646c72,
64'h6f57206f_6c6c6548,
64'h00000032_2d746c75,
64'h61666564_2d697274,
64'h00322d74_6c756166,
64'h65642d69_72742c78,
64'h6e6c7800_746c7561,
64'h6665642d_6972742c,
64'h786e6c78_006c6175,
64'h642d7369_2c786e6c,
64'h7800746e_65736572,
64'h702d7470_75727265,
64'h746e692c_786e6c78,
64'h00687464_69772d32,
64'h6f697067_2c786e6c,
64'h78006874_6469772d,
64'h6f697067_2c786e6c,
64'h7800322d_746c7561,
64'h6665642d_74756f64,
64'h2c786e6c_7800746c,
64'h75616665_642d6972,
64'h742c786e_6c78006c,
64'h6175642d_73692c78,
64'h6e6c7800_746e6573,
64'h6572702d_74707572,
64'h7265746e_692c786e,
64'h6c780068_74646977,
64'h2d326f69_70672c78,
64'h6e6c7800_68746469,
64'h772d6f69_70672c78,
64'h6e6c7800_322d746c,
64'h75616665_642d7475,
64'h6f642c78_6e6c7800,
64'h746c7561_6665642d,
64'h74756f64_2c786e6c,
64'h7800322d_73747570,
64'h6e692d6c_6c612c78,
64'h6e6c7800_73747570,
64'h6e692d6c_6c612c78,
64'h6e6c7800_72656c6c,
64'h6f72746e_6f632d6f,
64'h69706700_736c6c65,
64'h632d6f69_70672300,
64'h6f69646d_2d736168,
64'h2c786e6c_78006c61,
64'h6e726574_6e692d65,
64'h73752c78_6e6c7800,
64'h676e6f70_2d676e69,
64'h702d7874_2c786e6c,
64'h78006874_6469772d,
64'h64692d69_78612d73,
64'h2c786e6c_7800676e,
64'h6f702d67_6e69702d,
64'h78722c78_6e6c7800,
64'h65636e61_74736e69,
64'h2c786e6c_78006f69,
64'h646d2d65_64756c63,
64'h6e692c78_6e6c7800,
64'h6b636162_706f6f6c,
64'h2d6c616e_7265746e,
64'h692d6564_756c636e,
64'h692c786e_6c780073,
64'h72656666_75622d6c,
64'h61626f6c_672d6564,
64'h756c636e_692c786e,
64'h6c780078_656c7075,
64'h642c786e_6c780065,
64'h6c646e61_682d7968,
64'h70007373_65726464,
64'h612d6361_6d2d6c61,
64'h636f6c00_70772d65,
64'h6c626173_69640073,
64'h65676e61_722d6567,
64'h61746c6f_76007963,
64'h322d7374_75706e69,
64'h2d6c6c61_2c786e6c,
64'h78007374_75706e69,
64'h2d6c6c61_2c786e6c,
64'h78007265_6c6c6f72,
64'h746e6f63_2d6f6970,
64'h6700736c_6c65632d,
64'h6f697067_23007373,
64'h65726464_612d6361,
64'h6d2d6c61_636f6c00,
64'h70772d65_6c626173,
64'h69640073_65676e61,
64'h722d6567_61746c6f,
64'h76007963_6e657571,
64'h6572662d_78616d2d,
64'h69707300_6f697461,
64'h722d6b63_732c786e,
64'h6c780073_7469622d,
64'h72656673_6e617274,
64'h2d6d756e_2c786e6c,
64'h78007374_69622d73,
64'h732d6d75_6e2c786e,
64'h6c780074_73697865,
64'h2d6f6669_662c786e,
64'h6c780079_6c696d61,
64'h662c786e_6c780068,
64'h74646977_2d6f692d,
64'h67657200_74666968,
64'h732d6765_72007374,
64'h70757272_65746e69,
64'h00746e65_7261702d,
64'h74707572_7265746e,
64'h69006465_6570732d,
64'h746e6572_72756300,
64'h7665646e_2c766373,
64'h69720079_7469726f,
64'h6972702d_78616d2c,
64'h76637369_72007365,
64'h6d616e2d_67657200,
64'h6465646e_65747865,
64'h2d737470_75727265,
64'h746e6900_7365676e,
64'h61720064_65646e65,
64'h70737573_2d657461,
64'h74732d6e_69617465,
64'h72007265_67676972,
64'h742d746c_75616665,
64'h642c7875_6e696c00,
64'h736f6970_6700656c,
64'h646e6168_702c7875,
64'h6e696c00_72656c6c,
64'h6f72746e_6f632d74,
64'h70757272_65746e69,
64'h00736c6c_65632d74,
64'h70757272_65746e69,
64'h23007469_6c70732d,
64'h626c7400_65707974,
64'h2d756d6d_00617369,
64'h2c766373_69720073,
64'h75746174_73006765,
64'h72006570_79745f65,
64'h63697665_64007963,
64'h6e657571_6572662d,
64'h78616d2d_69707300,
64'h6f697461_722d6b63,
64'h732c786e_6c780073,
64'h7469622d_72656673,
64'h6e617274_2d6d756e,
64'h2c786e6c_78007374,
64'h69622d73_732d6d75,
64'h6e2c786e_6c780074,
64'h73697865_2d6f6669,
64'h662c786e_6c780079,
64'h6c696d61_662c786e,
64'h6c780068_74646977,
64'h2d6f692d_67657200,
64'h74666968_732d6765,
64'h72007374_70757272,
64'h65746e69_00746e65,
64'h7261702d_74707572,
64'h7265746e_69006465,
64'h6570732d_746e6572,
64'h72756300_7665646e,
64'h2c766373_69720079,
64'h7469726f_6972702d,
64'h78616d2c_76637369,
64'h72007365_6d616e2d,
64'h67657200_6465646e,
64'h65747865_2d737470,
64'h75727265_746e6900,
64'h7365676e_61720064,
64'h65646e65_70737573,
64'h2d657461_74732d6e,
64'h69617465_72007265,
64'h67676972_742d746c,
64'h75616665_642c7875,
64'h6e696c00_736f6970,
64'h6700656c_646e6168,
64'h702c7875_6e696c00,
64'h72656c6c_6f72746e,
64'h6f632d74_70757272,
64'h65746e69_00736c6c,
64'h65632d74_70757272,
64'h65746e69_23007469,
64'h6c70732d_626c7400,
64'h65707974_2d756d6d,
64'h00617369_2c766373,
64'h69720073_75746174,
64'h73006765_72006570,
64'h79745f65_63697665,
64'h64007963_6e657571,
64'h6572662d_6b636f6c,
64'h63007963_6e657571,
64'h6572662d_65736162,
64'h656d6974_00687461,
64'h702d7475_6f647473,
64'h006c6564_6f6d0065,
64'h6c626974_61706d6f,
64'h6300736c_6c65632d,
64'h657a6973_2300736c,
64'h6c65632d_73736572,
64'h64646123_09000000,
64'h6b636f6c_63007963,
64'h6e657571_6572662d,
64'h65736162_656d6974,
64'h00687461_702d7475,
64'h6f647473_006c6564,
64'h6f6d0065_6c626974,
64'h61706d6f_6300736c,
64'h6c65632d_657a6973,
64'h2300736c_6c65632d,
64'h73736572_64646123,
64'h09000000_02000000,
64'h02000000_02000000,
64'h02000000_01000000,
64'hbb000000_04000000,
64'h03000000_01000000,
64'hb5000000_04000000,
64'h03000000_ffffffff,
64'h8f030000_04000000,
64'h03000000_ffffffff,
64'h7e030000_04000000,
64'h03000000_01000000,
64'h71030000_04000000,
64'h03000000_00000000,
64'h5a030000_04000000,
64'h03000000_08000000,
64'h49030000_04000000,
64'h03000000_08000000,
64'h39030000_04000000,
64'h03000000_00000000,
64'h25030000_04000000,
64'h03000000_00000000,
64'h13030000_04000000,
64'h03000000_00000000,
64'h01030000_04000000,
64'h03000000_00000000,
64'hf1020000_04000000,
64'h03000000_00000100,
64'h00000000_00000040,
64'h00000000_67000000,
64'h10000000_03000000,
64'he1020000_00000000,
64'h03000000_00000000,
64'h612e3030_2e312d6f,
64'h6970672d_7370782c,
64'h786e6c78_1b000000,
64'h15000000_03000000,
64'h02000000_d5020000,
64'h01000000_bb000000,
64'h04000000_03000000,
64'h00000030_30303030,
64'h30303440_6f697067,
64'h01000000_02000000,
64'h02000000_02000000,
64'h04000000_bb000000,
64'h01000000_b5000000,
64'h04000000_03000000,
64'h04000000_b5000000,
64'hffffffff_c5020000,
64'h04000000_03000000,
64'h01000000_67000000,
64'hffffffff_b4020000,
64'h04000000_03000000,
64'h006b726f_7774656e,
64'h5b000000_08000000,
64'h03000000_00000000,
64'h35313943_2e433130,
64'h3064692d_7968702d,
64'h74656e72_65687465,
64'h1b000000_19000000,
64'h03000000_00000031,
64'h406f6964_6d5f305f,
64'h6574696c_74656e72,
64'h65687465_5f697861,
64'h01000000_00000000,
64'h0f000000_04000000,
64'h03000000_01000000,
64'h00000000_04000000,
64'h03000000_00000000,
64'h6f69646d_01000000,
64'h01000000_c7020000,
64'h01000000_a7020000,
64'h04000000_03000000,
64'h00000000_b5020000,
64'h00000000_90020000,
64'h04000000_03000000,
64'h01000000_a3020000,
64'h08000000_7f020000,
64'h04000000_03000000,
64'h04000000_8f020000,
64'h08000000_6f020000,
64'h04000000_03000000,
64'h01000000_7d020000,
64'h00000000_5b020000,
64'h04000000_03000000,
64'h00657469_6c74656e,
64'h72656874_655f6978,
64'h615f786e_6c785f69,
64'h6f020000_18000000,
64'h03000000_01000000,
64'h5d020000_04000000,
64'h03000000_00000000,
64'h3e020000_04000000,
64'h03000000_01000000,
64'h22020000_04000000,
64'h03000000_01000000,
64'h16020000_04000000,
64'h03000000_00000100,
64'h00000000_49020000,
64'h04000000_03000000,
64'h00000000_37020000,
64'h04000000_03000000,
64'h00000000_27020000,
64'h04000000_03000000,
64'h00000100_00000000,
64'h00000040_00000000,
64'h67000000_10000000,
64'h03000000_17020000,
64'h00000000_03000000,
64'h00000000_612e3030,
64'h2e312d6f_6970672d,
64'h7370782c_786e6c78,
64'h1b000000_15000000,
64'h03000000_02000000,
64'h0b020000_04000000,
64'h03000000_00000030,
64'h30303030_30303440,
64'h6f697067_01000000,
64'h02000000_00800000,
64'h00000000_00000030,
64'h00000000_67000000,
64'h10000000_03000000,
64'h04000000_0b020000,
64'h04000000_03000000,
64'h00002201_00350a00,
64'h0000e5e4_e3e2e1ee,
64'hf9010000_06000000,
64'h03000000_00000000,
64'h03000000_58010000,
@ -334,18 +259,13 @@ module bootrom (
64'h04000000_03000000,
64'h006b726f_7774656e,
64'h5b000000_08000000,
64'h03000000_0000612e,
64'h30302e31_2d657469,
64'h6c74656e_72656874,
64'h652d7370_782c786e,
64'h6c780030_2e332d65,
64'h74696c74_656e7265,
64'h6874652d_6978612c,
64'h786e6c78_1b000000,
64'h37000000_03000000,
64'h00000030_30303030,
64'h30303340_74656e72,
64'h65687465_01000000,
64'h03000000_00687465,
64'h2d637369_72776f6c,
64'h1b000000_0c000000,
64'h03000000_00000000,
64'h30303030_30303033,
64'h40687465_2d637369,
64'h72776f6c_01000000,
64'h02000000_02000000,
64'hee010000_00000000,
64'h03000000_e40c0000,
@ -576,11 +496,11 @@ module bootrom (
64'h00000000_01000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'hac0a0000_a2030000,
64'h00090000_d8020000,
64'h00000000_10000000,
64'h11000000_28000000,
64'he40a0000_38000000,
64'h860e0000_edfe0dd0,
64'h38090000_38000000,
64'h100c0000_edfe0dd0,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
@ -635,91 +555,91 @@ module bootrom (
64'h00000597_01f41413,
64'h0010041b_e911d31f,
64'hf0ef057e_65a14505,
64'hf16ff0ef_04450513,
64'hf16ff0ef_dcc50513,
64'h00001517_ef0ff0ef,
64'he4061141_bbb5f2cf,
64'hf0ef32a5_05130000,
64'h1517b3f5_0a450513,
64'hf0ef0b25_05130000,
64'h1517b3f5_e2c50513,
64'h00001517_fc4ff0ef,
64'h8526f48f_f0ef1865,
64'h8526f48f_f0eff0e5,
64'h05130000_1517f54f,
64'hf0ef17a5_05130000,
64'hf0eff025_05130000,
64'h1517c50d_84aac5ff,
64'hf0ef8552_865a020a,
64'ha583f70f_f0ef3565,
64'ha583f70f_f0ef0de5,
64'h05130000_1517f579,
64'h93e30804_8493f84f,
64'hf0ef2985_0f450513,
64'hf0ef2985_e7c50513,
64'h00001517_ff2c1be3,
64'h85bff0ef_09050009,
64'h4503fa0f_f0ef3765,
64'h4503fa0f_f0ef0fe5,
64'h05130000_151782ff,
64'hf0ef7088_fb2ff0ef,
64'h37850513_00001517,
64'h10050513_00001517,
64'h841ff0ef_6c88fc4f,
64'hf0ef37a5_05130000,
64'hf0ef1025_05130000,
64'h1517853f_f0ef0704,
64'h8c130284_89136888,
64'hfdeff0ef_38450513,
64'hfdeff0ef_10c50513,
64'h00001517_ff2c1be3,
64'h8b3ff0ef_09050009,
64'h45030109_0c13ffcf,
64'hf0ef3825_05130000,
64'hf0ef10a5_05130000,
64'h1517fe99_1be38d1f,
64'hf0ef0905_00094503,
64'hff048913_81bff0ef,
64'h38050513_00001517,
64'h10850513_00001517,
64'h8ebff0ef_0ff9f513,
64'h82fff0ef_37c50513,
64'h00001517_b5fd1a65,
64'h82fff0ef_10450513,
64'h00001517_b5fdf2e5,
64'h05130000_15178c7f,
64'hf0ef854e_84bff0ef,
64'h28850513_00001517,
64'h857ff0ef_27c50513,
64'h01050513_00001517,
64'h857ff0ef_00450513,
64'h00001517_c50d0804,
64'h89aa8a8a_d65ff0ef,
64'h850a4605_71010489,
64'h2583879f_f0ef1e65,
64'h2583879f_f0eff6e5,
64'h05130000_15178c7f,
64'hf0ef4556_88bff0ef,
64'h3b850513_00001517,
64'h14050513_00001517,
64'h8d9ff0ef_454689df,
64'hf0ef3aa5_05130000,
64'hf0ef1325_05130000,
64'h151792bf_f0ef6526,
64'h8afff0ef_39c50513,
64'h8afff0ef_12450513,
64'h00001517_93dff0ef,
64'h75028c1f_f0ef39e5,
64'h75028c1f_f0ef1265,
64'h05130000_151794ff,
64'hf0ef6562_8d3ff0ef,
64'h39850513_00001517,
64'h12050513_00001517,
64'h921ff0ef_45528e5f,
64'hf0ef39a5_05130000,
64'hf0ef1225_05130000,
64'h1517933f_f0ef4542,
64'h8f7ff0ef_39c50513,
64'h8f7ff0ef_12450513,
64'h00001517_945ff0ef,
64'h4532909f_f0ef39e5,
64'h4532909f_f0ef1265,
64'h05130000_1517957f,
64'hf0ef4522_91bff0ef,
64'h3a050513_00001517,
64'h12850513_00001517,
64'h9a9ff0ef_4b916502,
64'h92fff0ef_3a450513,
64'h92fff0ef_12c50513,
64'h00001517_93bff0ef,
64'h39050513_00001517,
64'h11850513_00001517,
64'hbf6154f9_94bff0ef,
64'h2b850513_00001517,
64'h04050513_00001517,
64'h9d9ff0ef_852695df,
64'hf0ef39a5_05130000,
64'h1517969f_f0ef38e5,
64'hf0ef1225_05130000,
64'h1517969f_f0ef1165,
64'h05130000_1517c905,
64'h84aa890a_e75ff0ef,
64'h850a4585_46057101,
64'h987ff0ef_39450513,
64'h987ff0ef_11c50513,
64'h00001517_80826161,
64'h6c026ba2_6b426ae2,
64'h7a0279a2_794274e2,
64'h64068526_60a6fb04,
64'h011354fd_9b3ff0ef,
64'h39850513_00001517,
64'h12050513_00001517,
64'hc51de1ff_f0ef8b2e,
64'h8a2a0880_e062e45e,
64'hec56f44e_f84afc26,
@ -731,7 +651,7 @@ module bootrom (
64'hf0efc83f_f0ef4531,
64'h45814605_4401f890,
64'h46e314fd_a13ff0ef,
64'h3f050513_00001517,
64'h17850513_00001517,
64'he7990354_e7b30534,
64'h12632981_90411442,
64'h8c49cabf_f0ef9041,
@ -778,13 +698,13 @@ module bootrom (
64'hc51157f9_efbff0ef,
64'hc91157fd_eb7ff0ef,
64'hfc6de03f_f0ef347d,
64'h4429b91f_f0ef5565,
64'h4429b91f_f0ef2de5,
64'h05130000_1517c89f,
64'hf0efe022_e4061141,
64'h80826105_00153513,
64'h64a26442_60e20004,
64'h051bfc94_0ce3e37f,
64'hf0efeb3f_f0ef57e5,
64'hf0efeb3f_f0ef3065,
64'h05130000_151785aa,
64'h842ae53f_f0ef0290,
64'h05134000_05b70770,
@ -792,7 +712,7 @@ module bootrom (
64'he822ec06_e4261101,
64'h80820141_00153513,
64'h157d6402_60a20004,
64'h051bef3f_f0ef5b85,
64'h051bef3f_f0ef3405,
64'h051385a2_00001517,
64'he89ff0ef_842ae97f,
64'hf0efe022_e4060370,
@ -811,7 +731,7 @@ module bootrom (
64'h08700613_1101bfcd,
64'h45018082_61056902,
64'h64a26442_60e24505,
64'hf89ff0ef_45856465,
64'hf89ff0ef_45853ce5,
64'h05130000_1517fe99,
64'h15e3c00d_f25ff0ef,
64'h892a347d_f35ff0ef,
@ -819,12 +739,12 @@ module bootrom (
64'h44857104_0413e04a,
64'hec06e426_6409e822,
64'h1101cd1f_f06f6105,
64'h64050513_00001517,
64'h3c850513_00001517,
64'h60e26442_da7ff0ef,
64'h852e65a2_cebff0ef,
64'h68850513_00001517,
64'h41050513_00001517,
64'hcf7ff0ef_8522cfdf,
64'hf0efe42e_ec0668e5,
64'hf0efe42e_ec064165,
64'h05130000_1517842a,
64'he8221101_80826145,
64'h64e27402_70a2f47d,
@ -861,10 +781,10 @@ module bootrom (
64'h64a2d3b8_4719dbb8,
64'h644260e2_0ff47513,
64'h577d2000_07b7e25f,
64'hf0ef7925_05130000,
64'hf0ef51a5_05130000,
64'h1517eb3f_f0ef9101,
64'h15024088_e3bff0ef,
64'h7b050513_00001517,
64'h53850513_00001517,
64'he3958b85_240153fc,
64'h57e0ff65_8b050647,
64'h849353f8_d3b81060,
@ -873,25 +793,25 @@ module bootrom (
64'hd7a8dbb8_5779e426,
64'he822ec06_200007b7,
64'h1101e81f_f06f6105,
64'h7e050513_00001517,
64'h56850513_00001517,
64'h64a260e2_6442d03c,
64'h4799e99f_f0ef8065,
64'h05130000_2517f27f,
64'h4799e99f_f0ef58e5,
64'h05130000_1517f27f,
64'hf0ef9101_02049513,
64'h2481eb1f_f0ef7fe5,
64'h2481eb1f_f0ef5865,
64'h05130000_15175064,
64'hd03c1660_0793ec5f,
64'hf0ef8325_05130000,
64'h2517f53f_f0ef9101,
64'hf0ef5ba5_05130000,
64'h1517f53f_f0ef9101,
64'h02049513_2481eddf,
64'hf0ef82a5_05130000,
64'h25175064_d03c1040,
64'hf0ef5b25_05130000,
64'h15175064_d03c1040,
64'h07932000_0437fff5,
64'h37fd0001_47a9c3b8,
64'h47292000_07b7f05f,
64'hf0efe426_e822ec06,
64'h84a50513_11010000,
64'h25178082_41088082,
64'h5d250513_11010000,
64'h15178082_41088082,
64'hc10c8082_610560e2,
64'hee1ff0ef_00914503,
64'hee9ff0ef_00814503,

195
fpga/src/rgmii_to_mii_conv_xilinx.sv
View file

@ -1,195 +0,0 @@
// Copyright (c) 2015-2018 Princeton University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of Princeton University nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// Simplified RGMII <-> MII converter (boldly copied from OpenPiton)
// Specific to 7-series FPGA
module rgmii_to_mii_conv_xilinx (
// to PHY (RGMII)
output logic rgmii_phy_txc,
output logic rgmii_phy_txctl,
output logic [3:0] rgmii_phy_txd,
input logic rgmii_phy_rxc,
input logic rgmii_phy_rxctl,
input logic [3:0] rgmii_phy_rxd,
output logic rgmii_phy_rst_n,
inout wire rgmii_phy_mdio,
output logic rgmii_phy_mdc,
// from MAC (MII)
input logic mem_clk_i, // 200 MHz
input logic net_phy_rst_n,
input logic net_phy_tx_clk, // 25 MHz
input logic net_phy_tx_en,
input logic [3:0] net_phy_tx_data,
output logic net_phy_rx_clk,
output logic net_phy_dv,
output logic [3:0] net_phy_rx_data,
output logic net_phy_rx_er,
input logic net_mdio_i,
output logic net_mdio_o,
input logic net_mdio_t,
input logic net_phy_mdc
);
// -------------
// MDIO
// -------------
IOBUF mdio_io_iobuf (.I (net_mdio_i), .IO(rgmii_phy_mdio), .O (net_mdio_o), .T (net_mdio_t));
assign rgmii_phy_mdc = net_phy_mdc;
assign rgmii_phy_rst_n = net_phy_rst_n;
// -------------
// TX
// -------------
// net_phy_tx_clk: ___|------|______|------|______|------|______|
// rgmii_phy_txc: ---|______|------|______|------|______|------|
// net_phy_tx_en: -----_________________________________________
// rgmii_phy_txctl: _____--------------___________________________
// basically inverts the clock
ODDR net_phy_txc_oddr (
.C ( net_phy_tx_clk ), // 1-bit clock input (The CLK pin represents the clock input pin)
.CE ( 1'b1 ), // 1-bit clock enable input (CE represents the clock enable pin. When asserted Low,
.Q ( rgmii_phy_txc ), // 1-bit DDR output (ODDR register output)
// this port disables the output clock on port Q.)
.D1 ( 1'b0 ), // 1-bit data input (positive edge) (ODDR register inputs)
.D2 ( 1'b1 ), // 1-bit data input (negative edge) (ODDR register inputs)
// Synchronous/Asynchronous set/reset pin. Set/Reset is
// asserted High.
.R ( 1'b0 ), // 1-bit reset
.S ( 1'b0 ) // 1-bit set
);
// D-FF
FD net_phy_txctl_dff (
.C ( net_phy_tx_clk ),
.D ( net_phy_tx_en ),
.Q ( rgmii_phy_txctl )
);
for (genvar i = 0; i < 4; i++) begin : gen_net_phy_txd
FD net_phy_txd_dff (
.C ( net_phy_tx_clk ),
.D ( net_phy_tx_data[i] ),
.Q ( rgmii_phy_txd[i] )
);
end
// -------------
// RX
// -------------
logic net_phy_rxc_ibufg_out;
logic net_phy_rxc_delayed;
logic net_phy_rx_dv_f;
logic net_phy_rx_err_f;
logic net_phy_rx_dv_ff;
logic net_phy_rx_err_ff;
logic [3:0] net_phy_rxd_f;
logic [3:0] net_phy_rxd_ff;
IBUFG net_phy_rxc_ibufg (
.I ( rgmii_phy_rxc ),
.O ( net_phy_rxc_ibufg_out )
);
// Delay by RXC 31*78 (IDELAY_VALUE*tap_delay@200MHz) to put in RXD/RXCTL eye
(* IODELAY_GROUP = "NET_PHY_RXC" *)
IDELAYE2 #(
.CINVCTRL_SEL ( "FALSE" ), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC ( "IDATAIN" ), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE ( "FALSE" ), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE ( "FIXED" ), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE ( 31 ), // Input delay tap setting (0-31)
.PIPE_SEL ( "FALSE" ), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY ( 200.0 ), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN ( "DATA" ) // DATA, CLOCK input signal
) i_idelaye2 (
.CNTVALUEOUT ( ), // 5-bit output: Counter value output
.DATAOUT ( net_phy_rxc_delayed ), // 1-bit output: Delayed data output
.C ( 1'b0 ), // 1-bit input: Clock input
.CE ( 1'b0 ), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL ( ), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN ( 5'b0 ), // 5-bit input: Counter value input
.DATAIN ( 1'b0 ), // 1-bit input: Internal delay data input
.IDATAIN ( net_phy_rxc_ibufg_out ), // 1-bit input: Data input from the I/O
.INC ( 1'b0 ), // 1-bit input: Increment / Decrement tap delay input
.LD ( 1'b0 ), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN ( 1'b0 ), // 1-bit input: Enable PIPELINE register to load data input
.REGRST ( 1'b0 ) // 1-bit input: Active-high reset tap-delay input
);
(* IODELAY_GROUP = "NET_PHY_RXC" *)
IDELAYCTRL i_idelayctrl (
.RDY ( ), // 1-bit output: Ready output
// 200-MHz for g2, clk_mmccm drives clocks through BUFG
.REFCLK ( mem_clk_i ), // 1-bit input: Reference clock input
.RST ( 1'b0 ) // 1-bit input: Active high reset input
);
BUFG BUFG_inst (
.I ( net_phy_rxc_delayed ),
.O ( net_phy_rx_clk )
);
// The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER)
// on the falling edge.
// data valid is transmitted on positive edge
always_ff @(posedge net_phy_rx_clk) begin
if (~rgmii_phy_rst_n) begin
net_phy_rx_dv_f <= 1'b0;
end else begin
net_phy_rx_dv_f <= rgmii_phy_rxctl;
end
end
// data error is encoded on negative edge of rxctl
always_ff @(negedge net_phy_rx_clk) begin
if (~rgmii_phy_rst_n) begin
net_phy_rx_err_f <= 1'b0;
end else begin
net_phy_rx_err_f <= rgmii_phy_rxctl;
end
end
always_ff @(posedge net_phy_rx_clk) begin
if (~rgmii_phy_rst_n) begin
net_phy_rxd_f <= '0;
net_phy_rxd_ff <= '0;
net_phy_rx_dv_ff <= 1'b0;
net_phy_rx_err_ff <= 1'b0;
end else begin
net_phy_rxd_f <= rgmii_phy_rxd;
net_phy_rxd_ff <= net_phy_rxd_f;
net_phy_rx_dv_ff <= net_phy_rx_dv_f;
net_phy_rx_err_ff <= net_phy_rx_err_f;
end
end
assign net_phy_dv = net_phy_rx_dv_ff;
assign net_phy_rx_er = net_phy_rx_dv_ff ^ net_phy_rx_err_ff;
assign net_phy_rx_data = net_phy_rxd_ff;
endmodule

2
fpga/xilinx/xlnx_axi_ethernetlite/Makefile
View file

@ -1,2 +0,0 @@
PROJECT:=xlnx_axi_ethernetlite
include ../common.mk

17
fpga/xilinx/xlnx_axi_ethernetlite/tcl/run.tcl
View file

@ -1,17 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set ipName xlnx_axi_ethernetlite
create_project $ipName . -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_ethernetlite -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.C_S_AXI_PROTOCOL {AXI4} CONFIG.AXI_ACLK_FREQ_MHZ {100}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

14
fpga/xilinx/xlnx_clk_gen/tcl/run.tcl
View file

@ -8,10 +8,20 @@ set_property board_part $boardName [current_project]
create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} CONFIG.CLKOUT2_USED {true} CONFIG.CLKOUT3_USED {true} CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {25} CONFIG.CLKIN1_JITTER_PS {50.0} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} CONFIG.MMCM_CLKIN1_PERIOD {5.000} CONFIG.MMCM_CLKIN2_PERIOD {10.0} CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} CONFIG.MMCM_CLKOUT1_DIVIDE {40} CONFIG.MMCM_CLKOUT2_DIVIDE {10} CONFIG.NUM_OUT_CLKS {3} CONFIG.CLKOUT1_JITTER {129.198} CONFIG.CLKOUT1_PHASE_ERROR {89.971} CONFIG.CLKOUT2_JITTER {148.629} CONFIG.CLKOUT2_PHASE_ERROR {89.971} CONFIG.CLKOUT3_JITTER {112.316} CONFIG.CLKOUT3_PHASE_ERROR {89.971}] [get_ips $ipName]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} \
CONFIG.NUM_OUT_CLKS {4} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {125} \
CONFIG.CLKOUT3_REQUESTED_PHASE {90.000} \
CONFIG.CLKIN1_JITTER_PS {50.0} \
] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

174
tb/ariane_peripherals.sv
View file

@ -480,175 +480,11 @@ module ariane_peripherals #(
// ---------------
// 4. Ethernet
// ---------------
if (InclEthernet) begin : gen_ethernet
wire mdio_i, mdio_o, mdio_t;
logic [3:0] s_axi_eth_awid;
logic [31:0] s_axi_eth_awaddr;
logic [7:0] s_axi_eth_awlen;
logic [2:0] s_axi_eth_awsize;
logic [1:0] s_axi_eth_awburst;
logic [3:0] s_axi_eth_awcache;
logic s_axi_eth_awvalid;
logic s_axi_eth_awready;
logic [31:0] s_axi_eth_wdata;
logic [3:0] s_axi_eth_wstrb;
logic s_axi_eth_wlast;
logic s_axi_eth_wvalid;
logic s_axi_eth_wready;
logic [3:0] s_axi_eth_bid;
logic [1:0] s_axi_eth_bresp;
logic s_axi_eth_bvalid;
logic s_axi_eth_bready;
logic [3:0] s_axi_eth_arid;
logic [31:0] s_axi_eth_araddr;
logic [7:0] s_axi_eth_arlen;
logic [2:0] s_axi_eth_arsize;
logic [1:0] s_axi_eth_arburst;
logic [3:0] s_axi_eth_arcache;
logic s_axi_eth_arvalid;
logic s_axi_eth_arready;
logic [3:0] s_axi_eth_rid;
logic [31:0] s_axi_eth_rdata;
logic [1:0] s_axi_eth_rresp;
logic s_axi_eth_rlast;
logic s_axi_eth_rvalid;
assign s_axi_eth_awid = '0;
assign s_axi_eth_arid = '0;
// system-bus is 64-bit, convert down to 32 bit
xlnx_axi_clock_converter i_xlnx_axi_clock_converter_ethernet (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.s_axi_awid ( ethernet.aw_id ),
.s_axi_awaddr ( ethernet.aw_addr[31:0] ),
.s_axi_awlen ( ethernet.aw_len ),
.s_axi_awsize ( ethernet.aw_size ),
.s_axi_awburst ( ethernet.aw_burst ),
.s_axi_awlock ( ethernet.aw_lock ),
.s_axi_awcache ( ethernet.aw_cache ),
.s_axi_awprot ( ethernet.aw_prot ),
.s_axi_awregion ( ethernet.aw_region ),
.s_axi_awqos ( ethernet.aw_qos ),
.s_axi_awvalid ( ethernet.aw_valid ),
.s_axi_awready ( ethernet.aw_ready ),
.s_axi_wdata ( ethernet.w_data ),
.s_axi_wstrb ( ethernet.w_strb ),
.s_axi_wlast ( ethernet.w_last ),
.s_axi_wvalid ( ethernet.w_valid ),
.s_axi_wready ( ethernet.w_ready ),
.s_axi_bid ( ethernet.b_id ),
.s_axi_bresp ( ethernet.b_resp ),
.s_axi_bvalid ( ethernet.b_valid ),
.s_axi_bready ( ethernet.b_ready ),
.s_axi_arid ( ethernet.ar_id ),
.s_axi_araddr ( ethernet.ar_addr[31:0] ),
.s_axi_arlen ( ethernet.ar_len ),
.s_axi_arsize ( ethernet.ar_size ),
.s_axi_arburst ( ethernet.ar_burst ),
.s_axi_arlock ( ethernet.ar_lock ),
.s_axi_arcache ( ethernet.ar_cache ),
.s_axi_arprot ( ethernet.ar_prot ),
.s_axi_arregion ( ethernet.ar_region ),
.s_axi_arqos ( ethernet.ar_qos ),
.s_axi_arvalid ( ethernet.ar_valid ),
.s_axi_arready ( ethernet.ar_ready ),
.s_axi_rid ( ethernet.r_id ),
.s_axi_rdata ( ethernet.r_data ),
.s_axi_rresp ( ethernet.r_resp ),
.s_axi_rlast ( ethernet.r_last ),
.s_axi_rvalid ( ethernet.r_valid ),
.s_axi_rready ( ethernet.r_ready ),
.m_axi_awaddr ( s_axi_eth_awaddr ),
.m_axi_awlen ( s_axi_eth_awlen ),
.m_axi_awsize ( s_axi_eth_awsize ),
.m_axi_awburst ( s_axi_eth_awburst ),
.m_axi_awlock ( ),
.m_axi_awcache ( s_axi_eth_awcache ),
.m_axi_awprot ( ),
.m_axi_awregion ( ),
.m_axi_awqos ( ),
.m_axi_awvalid ( s_axi_eth_awvalid ),
.m_axi_awready ( s_axi_eth_awready ),
.m_axi_wdata ( s_axi_eth_wdata ),
.m_axi_wstrb ( s_axi_eth_wstrb ),
.m_axi_wlast ( s_axi_eth_wlast ),
.m_axi_wvalid ( s_axi_eth_wvalid ),
.m_axi_wready ( s_axi_eth_wready ),
.m_axi_bresp ( s_axi_eth_bresp ),
.m_axi_bvalid ( s_axi_eth_bvalid ),
.m_axi_bready ( s_axi_eth_bready ),
.m_axi_araddr ( s_axi_eth_araddr ),
.m_axi_arlen ( s_axi_eth_arlen ),
.m_axi_arsize ( s_axi_eth_arsize ),
.m_axi_arburst ( s_axi_eth_arburst ),
.m_axi_arlock ( ),
.m_axi_arcache ( s_axi_eth_arcache ),
.m_axi_arprot ( ),
.m_axi_arregion ( ),
.m_axi_arqos ( ),
.m_axi_arvalid ( s_axi_eth_arvalid ),
.m_axi_arready ( s_axi_eth_arready ),
.m_axi_rdata ( s_axi_eth_rdata ),
.m_axi_rresp ( s_axi_eth_rresp ),
.m_axi_rlast ( s_axi_eth_rlast ),
.m_axi_rvalid ( s_axi_eth_rvalid ),
.m_axi_rready ( m_axi_rready )
);
xlnx_axi_ethernetlite i_xlnx_axi_ethernetlite (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
.ip2intc_irpt ( irq_sources[0] ),
.s_axi_awid ( s_axi_eth_awid ),
.s_axi_awaddr ( s_axi_eth_awaddr[12:0] ),
.s_axi_awlen ( s_axi_eth_awlen ),
.s_axi_awsize ( s_axi_eth_awsize ),
.s_axi_awburst ( s_axi_eth_awburst ),
.s_axi_awcache ( s_axi_eth_awcache ),
.s_axi_awvalid ( s_axi_eth_awvalid ),
.s_axi_awready ( s_axi_eth_awready ),
.s_axi_wdata ( s_axi_eth_wdata ),
.s_axi_wstrb ( s_axi_eth_wstrb ),
.s_axi_wlast ( s_axi_eth_wlast ),
.s_axi_wvalid ( s_axi_eth_wvalid ),
.s_axi_wready ( s_axi_eth_wready ),
.s_axi_bid ( s_axi_eth_bid ),
.s_axi_bresp ( s_axi_eth_bresp ),
.s_axi_bvalid ( s_axi_eth_bvalid ),
.s_axi_bready ( s_axi_eth_bready ),
.s_axi_arid ( s_axi_eth_arid ),
.s_axi_araddr ( s_axi_eth_araddr[12:0] ),
.s_axi_arlen ( s_axi_eth_arlen ),
.s_axi_arsize ( s_axi_eth_arsize ),
.s_axi_arburst ( s_axi_eth_arburst ),
.s_axi_arcache ( s_axi_eth_arcache ),
.s_axi_arvalid ( s_axi_eth_arvalid ),
.s_axi_arready ( s_axi_eth_arready ),
.s_axi_rid ( s_axi_eth_rid ),
.s_axi_rdata ( s_axi_eth_rdata ),
.s_axi_rresp ( s_axi_eth_rresp ),
.s_axi_rlast ( s_axi_eth_rlast ),
.s_axi_rvalid ( s_axi_eth_rvalid ),
.s_axi_rready ( s_axi_eth_rready ),
.phy_tx_clk ( eth_txck ),
.phy_rx_clk ( eth_rxck ),
.phy_crs ( 1'b0 ),
.phy_dv ( eth_rxctl ),
.phy_rx_data ( eth_rxd ),
.phy_col ( 1'b0 ),
.phy_rx_er ( 1'b0 ),
.phy_rst_n ( eth_rst_n ),
.phy_tx_en ( eth_tx_en ),
.phy_tx_data ( eth_txd ),
.phy_mdio_i ( mdio_i ),
.phy_mdio_o ( mdio_o ),
.phy_mdio_t ( mdio_t ),
.phy_mdc ( eth_mdc )
);
IOBUF mdio_io_iobuf (.I (mdio_o), .IO(mdio), .O (mdio_i), .T (mdio_t));
end else begin
if (0)
begin
end
else
begin
assign irq_sources [2] = 1'b0;
assign ethernet.aw_ready = 1'b1;
assign ethernet.ar_ready = 1'b1;